gem5  v22.0.0.2
Classes | Namespaces | Macros | Functions
x86_cpu.cc File Reference
#include "arch/x86/kvm/x86_cpu.hh"
#include <linux/kvm.h>
#include <algorithm>
#include <cerrno>
#include <memory>
#include "arch/x86/cpuid.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/interrupts.hh"
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/msr.hh"
#include "arch/x86/utility.hh"
#include "base/compiler.hh"
#include "cpu/kvm/base.hh"
#include "debug/Drain.hh"
#include "debug/Kvm.hh"
#include "debug/KvmContext.hh"
#include "debug/KvmIO.hh"
#include "debug/KvmInt.hh"

Go to the source code of this file.

Classes

struct  gem5::FXSave
 

Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 

Macros

#define MSR_TSC   0x10
 
#define IO_PCI_CONF_ADDR   0xCF8
 
#define IO_PCI_CONF_DATA_BASE   0xCFC
 
#define SEG_SYS_TYPE_TSS_AVAILABLE   9
 
#define SEG_SYS_TYPE_TSS_BUSY   11
 
#define SEG_CS_TYPE_ACCESSED   9
 
#define SEG_CS_TYPE_READ_ACCESSED   11
 
#define SEG_TYPE_BIT_ACCESSED   1
 
#define FOREACH_IREG()
 
#define FOREACH_SREG()
 
#define FOREACH_DREG()
 
#define FOREACH_SEGMENT()
 
#define FOREACH_DTABLE()
 
#define APPLY_IREG(kreg, mreg)   inform("\t" # kreg ": 0x%llx\n", regs.kreg)
 
#define APPLY_SREG(kreg, mreg)   inform("\t" # kreg ": 0x%llx\n", sregs.kreg);
 
#define APPLY_SEGMENT(kreg, idx)   dumpKvm(# kreg, sregs.kreg);
 
#define APPLY_DTABLE(kreg, idx)   dumpKvm(# kreg, sregs.kreg);
 
#define APPLY_IREG(kreg, mreg)   regs.kreg = tc->getReg(mreg)
 
#define APPLY_SREG(kreg, mreg)   sregs.kreg = tc->readMiscRegNoEffect(mreg)
 
#define APPLY_SEGMENT(kreg, idx)   setKvmSegmentReg(tc, sregs.kreg, idx)
 
#define APPLY_DTABLE(kreg, idx)   setKvmDTableReg(tc, sregs.kreg, idx)
 
#define APPLY_SEGMENT(kreg, idx)   checkSeg(# kreg, idx + misc_reg::SegSelBase, sregs.kreg, sregs)
 
#define APPLY_IREG(kreg, mreg)   tc->setReg(mreg, regs.kreg)
 
#define APPLY_SREG(kreg, mreg)   tc->setMiscRegNoEffect(mreg, sregs.kreg)
 
#define APPLY_SEGMENT(kreg, idx)   setContextSegment(tc, sregs.kreg, idx)
 
#define APPLY_DTABLE(kreg, idx)   setContextSegment(tc, sregs.kreg, idx)
 

Functions

template<typename Struct , typename Entry >
static auto gem5::newVarStruct (size_t entries)
 
static void gem5::dumpKvm (const struct kvm_regs &regs)
 
static void gem5::dumpKvm (const char *reg_name, const struct kvm_segment &seg)
 
static void gem5::dumpKvm (const char *reg_name, const struct kvm_dtable &dtable)
 
static void gem5::dumpKvm (const struct kvm_sregs &sregs)
 
static void gem5::dumpFpuSpec (const struct FXSave &xs)
 
static void gem5::dumpFpuSpec (const struct kvm_fpu &fpu)
 
template<typename T >
static void gem5::dumpFpuCommon (const T &fpu)
 
static void gem5::dumpKvm (const struct kvm_fpu &fpu)
 
static void gem5::dumpKvm (const struct kvm_xsave &xsave)
 
static void gem5::dumpKvm (const struct kvm_msrs &msrs)
 
static void gem5::dumpKvm (const struct kvm_xcrs &regs)
 
static void gem5::dumpKvm (const struct kvm_vcpu_events &events)
 
static bool gem5::isCanonicalAddress (uint64_t addr)
 
static void gem5::checkSeg (const char *name, const int idx, const struct kvm_segment &seg, struct kvm_sregs sregs)
 
static void gem5::setKvmSegmentReg (ThreadContext *tc, struct kvm_segment &kvm_seg, const int index)
 
static void gem5::setKvmDTableReg (ThreadContext *tc, struct kvm_dtable &kvm_dtable, const int index)
 
static void gem5::forceSegAccessed (struct kvm_segment &seg)
 
template<typename T >
static void gem5::updateKvmStateFPUCommon (ThreadContext *tc, T &fpu)
 
void gem5::setContextSegment (ThreadContext *tc, const struct kvm_segment &kvm_seg, const int index)
 
void gem5::setContextSegment (ThreadContext *tc, const struct kvm_dtable &kvm_dtable, const int index)
 
template<typename T >
static void gem5::updateThreadContextFPUCommon (ThreadContext *tc, const T &fpu)
 
static struct kvm_cpuid_entry2 gem5::makeKvmCpuid (uint32_t function, uint32_t index, CpuidResult &result)
 

Macro Definition Documentation

◆ APPLY_DTABLE [1/3]

#define APPLY_DTABLE (   kreg,
  idx 
)    dumpKvm(# kreg, sregs.kreg);

◆ APPLY_DTABLE [2/3]

#define APPLY_DTABLE (   kreg,
  idx 
)    setKvmDTableReg(tc, sregs.kreg, idx)

◆ APPLY_DTABLE [3/3]

#define APPLY_DTABLE (   kreg,
  idx 
)    setContextSegment(tc, sregs.kreg, idx)

◆ APPLY_IREG [1/3]

#define APPLY_IREG (   kreg,
  mreg 
)    inform("\t" # kreg ": 0x%llx\n", regs.kreg)

◆ APPLY_IREG [2/3]

#define APPLY_IREG (   kreg,
  mreg 
)    regs.kreg = tc->getReg(mreg)

◆ APPLY_IREG [3/3]

#define APPLY_IREG (   kreg,
  mreg 
)    tc->setReg(mreg, regs.kreg)

◆ APPLY_SEGMENT [1/4]

#define APPLY_SEGMENT (   kreg,
  idx 
)    dumpKvm(# kreg, sregs.kreg);

◆ APPLY_SEGMENT [2/4]

#define APPLY_SEGMENT (   kreg,
  idx 
)    setKvmSegmentReg(tc, sregs.kreg, idx)

◆ APPLY_SEGMENT [3/4]

#define APPLY_SEGMENT (   kreg,
  idx 
)    checkSeg(# kreg, idx + misc_reg::SegSelBase, sregs.kreg, sregs)

◆ APPLY_SEGMENT [4/4]

#define APPLY_SEGMENT (   kreg,
  idx 
)    setContextSegment(tc, sregs.kreg, idx)

◆ APPLY_SREG [1/3]

#define APPLY_SREG (   kreg,
  mreg 
)    inform("\t" # kreg ": 0x%llx\n", sregs.kreg);

◆ APPLY_SREG [2/3]

#define APPLY_SREG (   kreg,
  mreg 
)    sregs.kreg = tc->readMiscRegNoEffect(mreg)

◆ APPLY_SREG [3/3]

#define APPLY_SREG (   kreg,
  mreg 
)    tc->setMiscRegNoEffect(mreg, sregs.kreg)

◆ FOREACH_DREG

#define FOREACH_DREG ( )
Value:
do { \
APPLY_DREG(db[0], misc_reg::Dr0); \
APPLY_DREG(db[1], misc_reg::Dr1); \
APPLY_DREG(db[2], misc_reg::Dr2); \
APPLY_DREG(db[3], misc_reg::Dr3); \
APPLY_DREG(dr6, misc_reg::Dr6); \
APPLY_DREG(dr7, misc_reg::Dr7); \
} while (0)

Definition at line 142 of file x86_cpu.cc.

◆ FOREACH_DTABLE

#define FOREACH_DTABLE ( )
Value:
do { \
APPLY_DTABLE(gdt, misc_reg::Tsg - misc_reg::SegSelBase); \
APPLY_DTABLE(idt, misc_reg::Idtr - misc_reg::SegSelBase); \
} while (0)

Definition at line 164 of file x86_cpu.cc.

◆ FOREACH_IREG

#define FOREACH_IREG ( )
Value:
do { \
APPLY_IREG(rax, int_reg::Rax); \
APPLY_IREG(rbx, int_reg::Rbx); \
APPLY_IREG(rcx, int_reg::Rcx); \
APPLY_IREG(rdx, int_reg::Rdx); \
APPLY_IREG(rsi, int_reg::Rsi); \
APPLY_IREG(rdi, int_reg::Rdi); \
APPLY_IREG(rsp, int_reg::Rsp); \
APPLY_IREG(rbp, int_reg::Rbp); \
APPLY_IREG(r8, int_reg::R8); \
APPLY_IREG(r9, int_reg::R9); \
APPLY_IREG(r10, int_reg::R10); \
APPLY_IREG(r11, int_reg::R11); \
APPLY_IREG(r12, int_reg::R12); \
APPLY_IREG(r13, int_reg::R13); \
APPLY_IREG(r14, int_reg::R14); \
APPLY_IREG(r15, int_reg::R15); \
} while (0)

Definition at line 111 of file x86_cpu.cc.

◆ FOREACH_SEGMENT

#define FOREACH_SEGMENT ( )
Value:
do { \
APPLY_SEGMENT(cs, misc_reg::Cs - misc_reg::SegSelBase); \
APPLY_SEGMENT(ds, misc_reg::Ds - misc_reg::SegSelBase); \
APPLY_SEGMENT(es, misc_reg::Es - misc_reg::SegSelBase); \
APPLY_SEGMENT(fs, misc_reg::Fs - misc_reg::SegSelBase); \
APPLY_SEGMENT(gs, misc_reg::Gs - misc_reg::SegSelBase); \
APPLY_SEGMENT(ss, misc_reg::Ss - misc_reg::SegSelBase); \
APPLY_SEGMENT(tr, misc_reg::Tr - misc_reg::SegSelBase); \
APPLY_SEGMENT(ldt, misc_reg::Tsl - misc_reg::SegSelBase); \
} while (0)

Definition at line 152 of file x86_cpu.cc.

◆ FOREACH_SREG

#define FOREACH_SREG ( )
Value:
do { \
APPLY_SREG(cr0, misc_reg::Cr0); \
APPLY_SREG(cr2, misc_reg::Cr2); \
APPLY_SREG(cr3, misc_reg::Cr3); \
APPLY_SREG(cr4, misc_reg::Cr4); \
APPLY_SREG(cr8, misc_reg::Cr8); \
APPLY_SREG(efer, misc_reg::Efer); \
APPLY_SREG(apic_base, misc_reg::ApicBase); \
} while (0)

Definition at line 131 of file x86_cpu.cc.

◆ IO_PCI_CONF_ADDR

#define IO_PCI_CONF_ADDR   0xCF8

Definition at line 58 of file x86_cpu.cc.

◆ IO_PCI_CONF_DATA_BASE

#define IO_PCI_CONF_DATA_BASE   0xCFC

Definition at line 59 of file x86_cpu.cc.

◆ MSR_TSC

#define MSR_TSC   0x10

Definition at line 56 of file x86_cpu.cc.

◆ SEG_CS_TYPE_ACCESSED

#define SEG_CS_TYPE_ACCESSED   9

Definition at line 67 of file x86_cpu.cc.

◆ SEG_CS_TYPE_READ_ACCESSED

#define SEG_CS_TYPE_READ_ACCESSED   11

Definition at line 69 of file x86_cpu.cc.

◆ SEG_SYS_TYPE_TSS_AVAILABLE

#define SEG_SYS_TYPE_TSS_AVAILABLE   9

Definition at line 62 of file x86_cpu.cc.

◆ SEG_SYS_TYPE_TSS_BUSY

#define SEG_SYS_TYPE_TSS_BUSY   11

Definition at line 64 of file x86_cpu.cc.

◆ SEG_TYPE_BIT_ACCESSED

#define SEG_TYPE_BIT_ACCESSED   1

Definition at line 73 of file x86_cpu.cc.

gem5::X86ISA::misc_reg::Dr7
@ Dr7
Definition: misc.hh:140
gem5::PowerISA::int_reg::R14
constexpr RegId R14(IntRegClass, _R14Idx)
gem5::X86ISA::misc_reg::SegSelBase
@ SegSelBase
Definition: misc.hh:304
gem5::X86ISA::misc_reg::Ss
@ Ss
Definition: misc.hh:307
gem5::X86ISA::misc_reg::Dr6
@ Dr6
Definition: misc.hh:139
gem5::X86ISA::misc_reg::Tr
@ Tr
Definition: misc.hh:316
gem5::X86ISA::misc_reg::ApicBase
@ ApicBase
Definition: misc.hh:401
gem5::X86ISA::misc_reg::Dr1
@ Dr1
Definition: misc.hh:134
gem5::X86ISA::misc_reg::Dr0
@ Dr0
Definition: misc.hh:133
gem5::X86ISA::misc_reg::Dr2
@ Dr2
Definition: misc.hh:135
gem5::PowerISA::int_reg::R10
constexpr RegId R10(IntRegClass, _R10Idx)
gem5::X86ISA::misc_reg::Cr0
@ Cr0
Definition: misc.hh:114
gem5::MipsISA::es
Bitfield< 27 > es
Definition: pra_constants.hh:313
gem5::PowerISA::int_reg::R8
constexpr RegId R8(IntRegClass, _R8Idx)
gem5::PowerISA::int_reg::R11
constexpr RegId R11(IntRegClass, _R11Idx)
gem5::PowerISA::int_reg::R9
constexpr RegId R9(IntRegClass, _R9Idx)
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::X86ISA::misc_reg::Cr2
@ Cr2
Definition: misc.hh:116
gem5::X86ISA::misc_reg::Ds
@ Ds
Definition: misc.hh:308
gem5::X86ISA::misc_reg::Tsl
@ Tsl
Definition: misc.hh:312
gem5::X86ISA::misc_reg::Cr3
@ Cr3
Definition: misc.hh:117
gem5::X86ISA::misc_reg::Cr4
@ Cr4
Definition: misc.hh:118
gem5::X86ISA::misc_reg::Cs
@ Cs
Definition: misc.hh:306
gem5::X86ISA::misc_reg::Idtr
@ Idtr
Definition: misc.hh:317
gem5::MipsISA::ds
Bitfield< 15, 13 > ds
Definition: pra_constants.hh:238
gem5::X86ISA::misc_reg::Dr3
@ Dr3
Definition: misc.hh:136
gem5::X86ISA::misc_reg::Gs
@ Gs
Definition: misc.hh:310
gem5::PowerISA::int_reg::R15
constexpr RegId R15(IntRegClass, _R15Idx)
gem5::MipsISA::gs
Bitfield< 28 > gs
Definition: mt_constants.hh:51
gem5::X86ISA::misc_reg::Es
@ Es
Definition: misc.hh:305
gem5::X86ISA::misc_reg::Cr8
@ Cr8
Definition: misc.hh:122
gem5::X86ISA::misc_reg::Efer
@ Efer
Definition: misc.hh:254
gem5::RiscvISA::fs
Bitfield< 14, 13 > fs
Definition: misc.hh:558
gem5::X86ISA::misc_reg::Fs
@ Fs
Definition: misc.hh:309
gem5::PowerISA::int_reg::R12
constexpr RegId R12(IntRegClass, _R12Idx)
gem5::PowerISA::int_reg::R13
constexpr RegId R13(IntRegClass, _R13Idx)
gem5::X86ISA::misc_reg::Tsg
@ Tsg
Definition: misc.hh:313

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