gem5  v21.1.0.2
faults.hh
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37 
38 #ifndef __ARCH_X86_FAULTS_HH__
39 #define __ARCH_X86_FAULTS_HH__
40 
41 #include <string>
42 
43 #include "arch/x86/tlb.hh"
44 #include "base/bitunion.hh"
45 #include "base/logging.hh"
46 #include "cpu/null_static_inst.hh"
47 #include "sim/faults.hh"
48 
49 namespace gem5
50 {
51 
52 namespace X86ISA
53 {
54 
55 // Base class for all x86 "faults" where faults is in the m5 sense
56 class X86FaultBase : public FaultBase
57 {
58  protected:
59  const char *faultName;
60  const char *mnem;
61  uint8_t vector;
62  uint64_t errorCode;
63 
64  X86FaultBase(const char *_faultName, const char *_mnem,
65  const uint8_t _vector, uint64_t _errorCode=(uint64_t)-1) :
66  faultName(_faultName), mnem(_mnem),
67  vector(_vector), errorCode(_errorCode)
68  {}
69 
70  const char *name() const override { return faultName; }
71  virtual bool isBenign() { return true; }
72  virtual const char *mnemonic() const { return mnem; }
73  virtual bool isSoft() { return false; }
74 
75  void invoke(ThreadContext *tc, const StaticInstPtr &inst=
76  nullStaticInstPtr) override;
77 
78  virtual std::string describe() const;
79 
80  public:
86  virtual uint8_t getVector() const { return vector; }
87 };
88 
89 // Base class for x86 faults which behave as if the underlying instruction
90 // didn't happen.
91 class X86Fault : public X86FaultBase
92 {
93  protected:
95 };
96 
97 // Base class for x86 traps which behave as if the underlying instruction
98 // completed.
99 class X86Trap : public X86FaultBase
100 {
101  protected:
103 
104  void invoke(ThreadContext *tc, const StaticInstPtr &inst=
105  nullStaticInstPtr) override;
106 };
107 
108 // Base class for x86 aborts which seem to be catastrophic failures.
109 class X86Abort : public X86FaultBase
110 {
111  protected:
113 
114  void invoke(ThreadContext *tc, const StaticInstPtr &inst=
115  nullStaticInstPtr) override;
116 };
117 
118 // Base class for x86 interrupts.
120 {
121  protected:
123 };
124 
125 class UnimpInstFault : public FaultBase
126 {
127  public:
128  const char *
129  name() const override
130  {
131  return "unimplemented_micro";
132  }
133 
134  void
136  nullStaticInstPtr) override
137  {
138  panic("Unimplemented instruction!");
139  }
140 };
141 
142 // Below is a summary of the interrupt/exception information in the
143 // architecture manuals.
144 
145 // Class | Type | vector | Cause | mnem
146 //------------------------------------------------------------------------
147 //Contrib Fault 0 Divide Error #DE
148 //Benign Either 1 Debug #DB
149 //Benign Interrupt 2 Non-Maskable-Interrupt #NMI
150 //Benign Trap 3 Breakpoint #BP
151 //Benign Trap 4 Overflow #OF
152 //Benign Fault 5 Bound-Range #BR
153 //Benign Fault 6 Invalid-Opcode #UD
154 //Benign Fault 7 Device-Not-Available #NM
155 //Benign Abort 8 Double-Fault #DF
156 // 9 Coprocessor-Segment-Overrun
157 //Contrib Fault 10 Invalid-TSS #TS
158 //Contrib Fault 11 Segment-Not-Present #NP
159 //Contrib Fault 12 Stack #SS
160 //Contrib Fault 13 General-Protection #GP
161 //Either Fault 14 Page-Fault #PF
162 // 15 Reserved
163 //Benign Fault 16 x87 Floating-Point Exception Pending #MF
164 //Benign Fault 17 Alignment-Check #AC
165 //Benign Abort 18 Machine-Check #MC
166 //Benign Fault 19 SIMD Floating-Point #XF
167 // 20-29 Reserved
168 //Contrib ? 30 Security Exception #SX
169 // 31 Reserved
170 //Benign Interrupt 0-255 External Interrupts #INTR
171 //Benign Interrupt 0-255 Software Interrupts INTn
172 
173 // Note that
174 class DivideError : public X86Fault
175 {
176  public:
177  DivideError() : X86Fault("Divide-Error", "#DE", 0) {}
178 };
179 
181 {
182  public:
183  DebugException() : X86FaultBase("Debug", "#DB", 1) {}
184 };
185 
187 {
188  public:
189  NonMaskableInterrupt(uint8_t _vector) :
190  X86Interrupt("Non Maskable Interrupt", "#NMI", 2, _vector)
191  {}
192 };
193 
194 class Breakpoint : public X86Trap
195 {
196  public:
197  Breakpoint() : X86Trap("Breakpoint", "#BP", 3) {}
198 };
199 
200 class OverflowTrap : public X86Trap
201 {
202  public:
203  OverflowTrap() : X86Trap("Overflow", "#OF", 4) {}
204 };
205 
206 class BoundRange : public X86Fault
207 {
208  public:
209  BoundRange() : X86Fault("Bound-Range", "#BR", 5) {}
210 };
211 
212 class InvalidOpcode : public X86Fault
213 {
214  public:
215  InvalidOpcode() : X86Fault("Invalid-Opcode", "#UD", 6) {}
216 
217  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
218  nullStaticInstPtr) override;
219 };
220 
222 {
223  public:
224  DeviceNotAvailable() : X86Fault("Device-Not-Available", "#NM", 7) {}
225 };
226 
227 class DoubleFault : public X86Abort
228 {
229  public:
230  DoubleFault() : X86Abort("Double-Fault", "#DF", 8, 0) {}
231 };
232 
233 class InvalidTSS : public X86Fault
234 {
235  public:
236  InvalidTSS(uint32_t _errorCode) :
237  X86Fault("Invalid-TSS", "#TS", 10, _errorCode)
238  {}
239 };
240 
242 {
243  public:
244  SegmentNotPresent(uint32_t _errorCode) :
245  X86Fault("Segment-Not-Present", "#NP", 11, _errorCode)
246  {}
247 };
248 
249 class StackFault : public X86Fault
250 {
251  public:
252  StackFault(uint32_t _errorCode) : X86Fault("Stack", "#SS", 12, _errorCode)
253  {}
254 };
255 
257 {
258  public:
259  GeneralProtection(uint32_t _errorCode) :
260  X86Fault("General-Protection", "#GP", 13, _errorCode)
261  {}
262 };
263 
264 class PageFault : public X86Fault
265 {
266  protected:
267  BitUnion32(PageFaultErrorCode)
268  Bitfield<0> present;
269  Bitfield<1> write;
270  Bitfield<2> user;
271  Bitfield<3> reserved;
272  Bitfield<4> fetch;
273  EndBitUnion(PageFaultErrorCode)
274 
275  Addr addr;
276 
277  public:
278  PageFault(Addr _addr, uint32_t _errorCode) :
279  X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr)
280  {}
281 
283  bool user, bool reserved) :
284  X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr)
285  {
286  PageFaultErrorCode code = 0;
287  code.present = present;
288  code.write = (mode == BaseMMU::Write);
289  code.user = user;
290  code.reserved = reserved;
291  code.fetch = (mode == BaseMMU::Execute);
292  errorCode = code;
293  }
294 
295  void
296  invoke(ThreadContext *tc, const StaticInstPtr &inst=
298 
299  virtual std::string describe() const;
300 };
301 
303 {
304  public:
306  X86Fault("x87 Floating-Point Exception Pending", "#MF", 16)
307  {}
308 };
309 
310 class AlignmentCheck : public X86Fault
311 {
312  public:
313  AlignmentCheck() : X86Fault("Alignment-Check", "#AC", 17, 0) {}
314 };
315 
316 class MachineCheck : public X86Abort
317 {
318  public:
319  MachineCheck() : X86Abort("Machine-Check", "#MC", 18) {}
320 };
321 
323 {
324  public:
325  SIMDFloatingPointFault() : X86Fault("SIMD Floating-Point", "#XF", 19) {}
326 };
327 
329 {
330  public:
331  SecurityException() : X86FaultBase("Security Exception", "#SX", 30) {}
332 };
333 
335 {
336  public:
337  ExternalInterrupt(uint8_t _vector) :
338  X86Interrupt("External Interrupt", "#INTR", _vector)
339  {}
340 };
341 
343 {
344  public:
346  X86Interrupt("System Management Interrupt", "#SMI", 0)
347  {}
348 };
349 
351 {
352  public:
353  InitInterrupt(uint8_t _vector) :
354  X86Interrupt("INIT Interrupt", "#INIT", _vector)
355  {}
356 
357  void invoke(ThreadContext *tc, const StaticInstPtr &inst=
358  nullStaticInstPtr) override;
359 };
360 
362 {
363  public:
364  StartupInterrupt(uint8_t _vector) :
365  X86Interrupt("Startup Interrupt", "#SIPI", _vector)
366  {}
367 
368  void invoke(ThreadContext *tc, const StaticInstPtr &inst=
369  nullStaticInstPtr) override;
370 };
371 
373 {
374  public:
375  SoftwareInterrupt(uint8_t _vector) :
376  X86Interrupt("Software Interrupt", "#INTR", _vector)
377  {}
378 
379  bool isSoft() override { return true; }
380 };
381 
382 } // namespace X86ISA
383 } // namespace gem5
384 
385 #endif // __ARCH_X86_FAULTS_HH__
gem5::X86ISA::AlignmentCheck
Definition: faults.hh:310
gem5::X86ISA::X86FaultBase::mnem
const char * mnem
Definition: faults.hh:60
gem5::X86ISA::StartupInterrupt::StartupInterrupt
StartupInterrupt(uint8_t _vector)
Definition: faults.hh:364
gem5::X86ISA::GeneralProtection::GeneralProtection
GeneralProtection(uint32_t _errorCode)
Definition: faults.hh:259
gem5::X86ISA::BoundRange
Definition: faults.hh:206
gem5::X86ISA::InitInterrupt::InitInterrupt
InitInterrupt(uint8_t _vector)
Definition: faults.hh:353
gem5::X86ISA::StackFault
Definition: faults.hh:249
gem5::X86ISA::InvalidTSS
Definition: faults.hh:233
gem5::X86ISA::SoftwareInterrupt::SoftwareInterrupt
SoftwareInterrupt(uint8_t _vector)
Definition: faults.hh:375
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::X86ISA::SegmentNotPresent
Definition: faults.hh:241
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:53
gem5::X86ISA::X86FaultBase::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:60
gem5::X86ISA::X86FaultBase::vector
uint8_t vector
Definition: faults.hh:61
gem5::X86ISA::InitInterrupt
Definition: faults.hh:350
gem5::X86ISA::PageFault::PageFault
PageFault(Addr _addr, uint32_t _errorCode)
Definition: faults.hh:278
gem5::X86ISA::NonMaskableInterrupt
Definition: faults.hh:186
gem5::X86ISA::DivideError::DivideError
DivideError()
Definition: faults.hh:177
gem5::X86ISA::InvalidOpcode::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:129
gem5::X86ISA::OverflowTrap
Definition: faults.hh:200
gem5::X86ISA::InitInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:187
gem5::X86ISA::DoubleFault::DoubleFault
DoubleFault()
Definition: faults.hh:230
gem5::X86ISA::PageFault::write
Bitfield< 1 > write
Definition: faults.hh:269
gem5::X86ISA::PageFault
Definition: faults.hh:264
gem5::X86ISA::SegmentNotPresent::SegmentNotPresent
SegmentNotPresent(uint32_t _errorCode)
Definition: faults.hh:244
faults.hh
gem5::X86ISA::X86FaultBase::errorCode
uint64_t errorCode
Definition: faults.hh:62
gem5::X86ISA::NonMaskableInterrupt::NonMaskableInterrupt
NonMaskableInterrupt(uint8_t _vector)
Definition: faults.hh:189
gem5::X86ISA::SecurityException
Definition: faults.hh:328
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:53
gem5::X86ISA::ExternalInterrupt::ExternalInterrupt
ExternalInterrupt(uint8_t _vector)
Definition: faults.hh:337
gem5::RefCountingPtr
If you want a reference counting pointer to a mutable object, create it like this:
Definition: refcnt.hh:126
gem5::X86ISA::X87FpExceptionPending
Definition: faults.hh:302
gem5::X86ISA::DeviceNotAvailable::DeviceNotAvailable
DeviceNotAvailable()
Definition: faults.hh:224
gem5::X86ISA::present
Bitfield< 7 > present
Definition: misc.hh:998
gem5::X86ISA::PageFault::PageFault
PageFault(Addr _addr, bool present, BaseMMU::Mode mode, bool user, bool reserved)
Definition: faults.hh:282
gem5::X86ISA::ExternalInterrupt
Definition: faults.hh:334
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::X86ISA::StackFault::StackFault
StackFault(uint32_t _errorCode)
Definition: faults.hh:252
gem5::X86ISA::PageFault::user
Bitfield< 2 > user
Definition: faults.hh:270
gem5::X86ISA::UnimpInstFault
Definition: faults.hh:125
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::X86ISA::PageFault::EndBitUnion
EndBitUnion(PageFaultErrorCode) Addr addr
bitunion.hh
gem5::X86ISA::Breakpoint
Definition: faults.hh:194
gem5::X86ISA::DivideError
Definition: faults.hh:174
gem5::X86ISA::X86FaultBase::getVector
virtual uint8_t getVector() const
Get the vector of an interrupt.
Definition: faults.hh:86
gem5::X86ISA::DeviceNotAvailable
Definition: faults.hh:221
gem5::X86ISA::SIMDFloatingPointFault::SIMDFloatingPointFault
SIMDFloatingPointFault()
Definition: faults.hh:325
gem5::X86ISA::SystemManagementInterrupt::SystemManagementInterrupt
SystemManagementInterrupt()
Definition: faults.hh:345
gem5::X86ISA::InvalidTSS::InvalidTSS
InvalidTSS(uint32_t _errorCode)
Definition: faults.hh:236
gem5::X86ISA::X86Fault
Definition: faults.hh:91
gem5::X86ISA::PageFault::describe
virtual std::string describe() const
Definition: faults.cc:179
gem5::X86ISA::UnimpInstFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.hh:135
gem5::X86ISA::BoundRange::BoundRange
BoundRange()
Definition: faults.hh:209
null_static_inst.hh
gem5::X86ISA::MachineCheck::MachineCheck
MachineCheck()
Definition: faults.hh:319
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::X86FaultBase::isBenign
virtual bool isBenign()
Definition: faults.hh:71
gem5::X86ISA::PageFault::BitUnion32
BitUnion32(PageFaultErrorCode) Bitfield< 0 > present
gem5::X86ISA::X86Interrupt
Definition: faults.hh:119
gem5::X86ISA::StartupInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:305
gem5::X86ISA::PageFault::reserved
Bitfield< 3 > reserved
Definition: faults.hh:271
gem5::X86ISA::SIMDFloatingPointFault
Definition: faults.hh:322
gem5::X86ISA::X86FaultBase
Definition: faults.hh:56
gem5::X86ISA::SoftwareInterrupt::isSoft
bool isSoft() override
Definition: faults.hh:379
gem5::X86ISA::X86FaultBase::name
const char * name() const override
Definition: faults.hh:70
gem5::X86ISA::StartupInterrupt
Definition: faults.hh:361
gem5::X86ISA::X86FaultBase::faultName
const char * faultName
Definition: faults.hh:59
gem5::X86ISA::SoftwareInterrupt
Definition: faults.hh:372
gem5::X86ISA::X86Trap
Definition: faults.hh:99
gem5::FaultBase
Definition: faults.hh:58
gem5::X86ISA::InvalidOpcode
Definition: faults.hh:212
gem5::X86ISA::DebugException::DebugException
DebugException()
Definition: faults.hh:183
gem5::X86ISA::InvalidOpcode::InvalidOpcode
InvalidOpcode()
Definition: faults.hh:215
logging.hh
gem5::X86ISA::SystemManagementInterrupt
Definition: faults.hh:342
gem5::X86ISA::Breakpoint::Breakpoint
Breakpoint()
Definition: faults.hh:197
gem5::X86ISA::X86FaultBase::isSoft
virtual bool isSoft()
Definition: faults.hh:73
gem5::X86ISA::DebugException
Definition: faults.hh:180
gem5::X86ISA::DoubleFault
Definition: faults.hh:227
gem5::X86ISA::X86Abort::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:123
gem5::X86ISA::X86Abort
Definition: faults.hh:109
tlb.hh
gem5::X86ISA::X87FpExceptionPending::X87FpExceptionPending
X87FpExceptionPending()
Definition: faults.hh:305
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::GeneralProtection
Definition: faults.hh:256
gem5::X86ISA::OverflowTrap::OverflowTrap
OverflowTrap()
Definition: faults.hh:203
gem5::X86ISA::X86Trap::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:110
gem5::X86ISA::AlignmentCheck::AlignmentCheck
AlignmentCheck()
Definition: faults.hh:313
gem5::X86ISA::X86FaultBase::mnemonic
virtual const char * mnemonic() const
Definition: faults.hh:72
gem5::X86ISA::X86FaultBase::describe
virtual std::string describe() const
Definition: faults.cc:99
gem5::X86ISA::SecurityException::SecurityException
SecurityException()
Definition: faults.hh:331
gem5::X86ISA::PageFault::fetch
Bitfield< 4 > fetch
Definition: faults.hh:272
gem5::X86ISA::PageFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:141
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::MachineCheck
Definition: faults.hh:316
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::X86ISA::UnimpInstFault::name
const char * name() const override
Definition: faults.hh:129
gem5::X86ISA::X86FaultBase::X86FaultBase
X86FaultBase(const char *_faultName, const char *_mnem, const uint8_t _vector, uint64_t _errorCode=(uint64_t) -1)
Definition: faults.hh:64

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