gem5  v22.0.0.2
faults.hh
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37 
38 #ifndef __ARCH_X86_FAULTS_HH__
39 #define __ARCH_X86_FAULTS_HH__
40 
41 #include <string>
42 
43 #include "arch/x86/tlb.hh"
44 #include "base/bitunion.hh"
45 #include "base/logging.hh"
46 #include "cpu/null_static_inst.hh"
47 #include "sim/faults.hh"
48 
49 namespace gem5
50 {
51 
52 namespace X86ISA
53 {
54 
55 // Base class for all x86 "faults" where faults is in the m5 sense
56 class X86FaultBase : public FaultBase
57 {
58  protected:
59  const char *faultName;
60  const char *mnem;
61  uint8_t vector;
62  uint64_t errorCode;
63 
64  X86FaultBase(const char *_faultName, const char *_mnem,
65  const uint8_t _vector, uint64_t _errorCode=(uint64_t)-1) :
66  faultName(_faultName), mnem(_mnem),
67  vector(_vector), errorCode(_errorCode)
68  {}
69 
70  const char *name() const override { return faultName; }
71  virtual bool isBenign() { return true; }
72  virtual const char *mnemonic() const { return mnem; }
73 
74  void invoke(ThreadContext *tc, const StaticInstPtr &inst=
75  nullStaticInstPtr) override;
76 
77  virtual std::string describe() const;
78 
79  public:
85  virtual uint8_t getVector() const { return vector; }
86 };
87 
88 // Base class for x86 faults which behave as if the underlying instruction
89 // didn't happen.
90 class X86Fault : public X86FaultBase
91 {
92  protected:
94 };
95 
96 // Base class for x86 traps which behave as if the underlying instruction
97 // completed.
98 class X86Trap : public X86FaultBase
99 {
100  protected:
102 
103  void invoke(ThreadContext *tc, const StaticInstPtr &inst=
104  nullStaticInstPtr) override;
105 };
106 
107 // Base class for x86 aborts which seem to be catastrophic failures.
108 class X86Abort : public X86FaultBase
109 {
110  protected:
112 
113  void invoke(ThreadContext *tc, const StaticInstPtr &inst=
114  nullStaticInstPtr) override;
115 };
116 
117 // Base class for x86 interrupts.
119 {
120  protected:
122 };
123 
124 class UnimpInstFault : public FaultBase
125 {
126  public:
127  const char *
128  name() const override
129  {
130  return "unimplemented_micro";
131  }
132 
133  void
135  nullStaticInstPtr) override
136  {
137  panic("Unimplemented instruction!");
138  }
139 };
140 
141 // Below is a summary of the interrupt/exception information in the
142 // architecture manuals.
143 
144 // Class | Type | vector | Cause | mnem
145 //------------------------------------------------------------------------
146 //Contrib Fault 0 Divide Error #DE
147 //Benign Either 1 Debug #DB
148 //Benign Interrupt 2 Non-Maskable-Interrupt #NMI
149 //Benign Trap 3 Breakpoint #BP
150 //Benign Trap 4 Overflow #OF
151 //Benign Fault 5 Bound-Range #BR
152 //Benign Fault 6 Invalid-Opcode #UD
153 //Benign Fault 7 Device-Not-Available #NM
154 //Benign Abort 8 Double-Fault #DF
155 // 9 Coprocessor-Segment-Overrun
156 //Contrib Fault 10 Invalid-TSS #TS
157 //Contrib Fault 11 Segment-Not-Present #NP
158 //Contrib Fault 12 Stack #SS
159 //Contrib Fault 13 General-Protection #GP
160 //Either Fault 14 Page-Fault #PF
161 // 15 Reserved
162 //Benign Fault 16 x87 Floating-Point Exception Pending #MF
163 //Benign Fault 17 Alignment-Check #AC
164 //Benign Abort 18 Machine-Check #MC
165 //Benign Fault 19 SIMD Floating-Point #XF
166 // 20-29 Reserved
167 //Contrib ? 30 Security Exception #SX
168 // 31 Reserved
169 //Benign Interrupt 0-255 External Interrupts #INTR
170 //Benign Interrupt 0-255 Software Interrupts INTn
171 
172 // Note that
173 class DivideError : public X86Fault
174 {
175  public:
176  DivideError() : X86Fault("Divide-Error", "#DE", 0) {}
177 };
178 
180 {
181  public:
182  DebugException() : X86FaultBase("Debug", "#DB", 1) {}
183 };
184 
186 {
187  public:
188  NonMaskableInterrupt(uint8_t _vector) :
189  X86Interrupt("Non Maskable Interrupt", "#NMI", 2, _vector)
190  {}
191 };
192 
193 class Breakpoint : public X86Trap
194 {
195  public:
196  Breakpoint() : X86Trap("Breakpoint", "#BP", 3) {}
197 };
198 
199 class OverflowTrap : public X86Trap
200 {
201  public:
202  OverflowTrap() : X86Trap("Overflow", "#OF", 4) {}
203 };
204 
205 class BoundRange : public X86Fault
206 {
207  public:
208  BoundRange() : X86Fault("Bound-Range", "#BR", 5) {}
209 };
210 
211 class InvalidOpcode : public X86Fault
212 {
213  public:
214  InvalidOpcode() : X86Fault("Invalid-Opcode", "#UD", 6) {}
215 
216  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
217  nullStaticInstPtr) override;
218 };
219 
221 {
222  public:
223  DeviceNotAvailable() : X86Fault("Device-Not-Available", "#NM", 7) {}
224 };
225 
226 class DoubleFault : public X86Abort
227 {
228  public:
229  DoubleFault() : X86Abort("Double-Fault", "#DF", 8, 0) {}
230 };
231 
232 class InvalidTSS : public X86Fault
233 {
234  public:
235  InvalidTSS(uint32_t _errorCode) :
236  X86Fault("Invalid-TSS", "#TS", 10, _errorCode)
237  {}
238 };
239 
241 {
242  public:
243  SegmentNotPresent(uint32_t _errorCode) :
244  X86Fault("Segment-Not-Present", "#NP", 11, _errorCode)
245  {}
246 };
247 
248 class StackFault : public X86Fault
249 {
250  public:
251  StackFault(uint32_t _errorCode) : X86Fault("Stack", "#SS", 12, _errorCode)
252  {}
253 };
254 
256 {
257  public:
258  GeneralProtection(uint32_t _errorCode) :
259  X86Fault("General-Protection", "#GP", 13, _errorCode)
260  {}
261 };
262 
263 class PageFault : public X86Fault
264 {
265  protected:
266  BitUnion32(PageFaultErrorCode)
267  Bitfield<0> present;
268  Bitfield<1> write;
269  Bitfield<2> user;
270  Bitfield<3> reserved;
271  Bitfield<4> fetch;
272  EndBitUnion(PageFaultErrorCode)
273 
274  Addr addr;
275 
276  public:
277  PageFault(Addr _addr, uint32_t _errorCode) :
278  X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr)
279  {}
280 
282  bool user, bool reserved) :
283  X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr)
284  {
285  PageFaultErrorCode code = 0;
286  code.present = present;
287  code.write = (mode == BaseMMU::Write);
288  code.user = user;
289  code.reserved = reserved;
290  code.fetch = (mode == BaseMMU::Execute);
291  errorCode = code;
292  }
293 
294  void
295  invoke(ThreadContext *tc, const StaticInstPtr &inst=
297 
298  virtual std::string describe() const;
299 };
300 
302 {
303  public:
305  X86Fault("x87 Floating-Point Exception Pending", "#MF", 16)
306  {}
307 };
308 
309 class AlignmentCheck : public X86Fault
310 {
311  public:
312  AlignmentCheck() : X86Fault("Alignment-Check", "#AC", 17, 0) {}
313 };
314 
315 class MachineCheck : public X86Abort
316 {
317  public:
318  MachineCheck() : X86Abort("Machine-Check", "#MC", 18) {}
319 };
320 
322 {
323  public:
324  SIMDFloatingPointFault() : X86Fault("SIMD Floating-Point", "#XF", 19) {}
325 };
326 
328 {
329  public:
330  SecurityException() : X86FaultBase("Security Exception", "#SX", 30) {}
331 };
332 
334 {
335  public:
336  ExternalInterrupt(uint8_t _vector) :
337  X86Interrupt("External Interrupt", "#INTR", _vector)
338  {}
339 };
340 
342 {
343  public:
345  X86Interrupt("System Management Interrupt", "#SMI", 0)
346  {}
347 };
348 
350 {
351  public:
352  InitInterrupt(uint8_t _vector) :
353  X86Interrupt("INIT Interrupt", "#INIT", _vector)
354  {}
355 
356  void invoke(ThreadContext *tc, const StaticInstPtr &inst=
357  nullStaticInstPtr) override;
358 };
359 
361 {
362  public:
363  StartupInterrupt(uint8_t _vector) :
364  X86Interrupt("Startup Interrupt", "#SIPI", _vector)
365  {}
366 
367  void invoke(ThreadContext *tc, const StaticInstPtr &inst=
368  nullStaticInstPtr) override;
369 };
370 
371 } // namespace X86ISA
372 } // namespace gem5
373 
374 #endif // __ARCH_X86_FAULTS_HH__
gem5::X86ISA::AlignmentCheck
Definition: faults.hh:309
gem5::X86ISA::X86FaultBase::mnem
const char * mnem
Definition: faults.hh:60
gem5::X86ISA::StartupInterrupt::StartupInterrupt
StartupInterrupt(uint8_t _vector)
Definition: faults.hh:363
gem5::X86ISA::GeneralProtection::GeneralProtection
GeneralProtection(uint32_t _errorCode)
Definition: faults.hh:258
gem5::X86ISA::BoundRange
Definition: faults.hh:205
gem5::X86ISA::mode
Bitfield< 3 > mode
Definition: types.hh:192
gem5::X86ISA::InitInterrupt::InitInterrupt
InitInterrupt(uint8_t _vector)
Definition: faults.hh:352
gem5::X86ISA::StackFault
Definition: faults.hh:248
gem5::X86ISA::InvalidTSS
Definition: faults.hh:232
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::X86ISA::SegmentNotPresent
Definition: faults.hh:240
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:56
gem5::X86ISA::X86FaultBase::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:61
gem5::X86ISA::X86FaultBase::vector
uint8_t vector
Definition: faults.hh:61
gem5::X86ISA::InitInterrupt
Definition: faults.hh:349
gem5::X86ISA::PageFault::PageFault
PageFault(Addr _addr, uint32_t _errorCode)
Definition: faults.hh:277
gem5::X86ISA::NonMaskableInterrupt
Definition: faults.hh:185
gem5::X86ISA::DivideError::DivideError
DivideError()
Definition: faults.hh:176
gem5::X86ISA::InvalidOpcode::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:124
gem5::X86ISA::OverflowTrap
Definition: faults.hh:199
gem5::X86ISA::InitInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:182
gem5::X86ISA::DoubleFault::DoubleFault
DoubleFault()
Definition: faults.hh:229
gem5::X86ISA::PageFault::write
Bitfield< 1 > write
Definition: faults.hh:268
gem5::X86ISA::PageFault
Definition: faults.hh:263
gem5::X86ISA::SegmentNotPresent::SegmentNotPresent
SegmentNotPresent(uint32_t _errorCode)
Definition: faults.hh:243
faults.hh
gem5::X86ISA::X86FaultBase::errorCode
uint64_t errorCode
Definition: faults.hh:62
gem5::X86ISA::NonMaskableInterrupt::NonMaskableInterrupt
NonMaskableInterrupt(uint8_t _vector)
Definition: faults.hh:188
gem5::X86ISA::SecurityException
Definition: faults.hh:327
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:56
gem5::X86ISA::ExternalInterrupt::ExternalInterrupt
ExternalInterrupt(uint8_t _vector)
Definition: faults.hh:336
gem5::RefCountingPtr< StaticInst >
gem5::X86ISA::X87FpExceptionPending
Definition: faults.hh:301
gem5::X86ISA::DeviceNotAvailable::DeviceNotAvailable
DeviceNotAvailable()
Definition: faults.hh:223
gem5::X86ISA::present
Bitfield< 7 > present
Definition: misc.hh:992
gem5::X86ISA::PageFault::PageFault
PageFault(Addr _addr, bool present, BaseMMU::Mode mode, bool user, bool reserved)
Definition: faults.hh:281
gem5::X86ISA::ExternalInterrupt
Definition: faults.hh:333
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::X86ISA::StackFault::StackFault
StackFault(uint32_t _errorCode)
Definition: faults.hh:251
gem5::X86ISA::PageFault::user
Bitfield< 2 > user
Definition: faults.hh:269
gem5::X86ISA::UnimpInstFault
Definition: faults.hh:124
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::X86ISA::PageFault::EndBitUnion
EndBitUnion(PageFaultErrorCode) Addr addr
bitunion.hh
gem5::X86ISA::Breakpoint
Definition: faults.hh:193
gem5::X86ISA::DivideError
Definition: faults.hh:173
gem5::X86ISA::X86FaultBase::getVector
virtual uint8_t getVector() const
Get the vector of an interrupt.
Definition: faults.hh:85
gem5::X86ISA::DeviceNotAvailable
Definition: faults.hh:220
gem5::X86ISA::SIMDFloatingPointFault::SIMDFloatingPointFault
SIMDFloatingPointFault()
Definition: faults.hh:324
gem5::X86ISA::SystemManagementInterrupt::SystemManagementInterrupt
SystemManagementInterrupt()
Definition: faults.hh:344
gem5::X86ISA::InvalidTSS::InvalidTSS
InvalidTSS(uint32_t _errorCode)
Definition: faults.hh:235
gem5::X86ISA::X86Fault
Definition: faults.hh:90
gem5::X86ISA::PageFault::describe
virtual std::string describe() const
Definition: faults.cc:174
gem5::X86ISA::UnimpInstFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.hh:134
gem5::X86ISA::BoundRange::BoundRange
BoundRange()
Definition: faults.hh:208
null_static_inst.hh
gem5::X86ISA::MachineCheck::MachineCheck
MachineCheck()
Definition: faults.hh:318
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::X86FaultBase::isBenign
virtual bool isBenign()
Definition: faults.hh:71
gem5::X86ISA::PageFault::BitUnion32
BitUnion32(PageFaultErrorCode) Bitfield< 0 > present
gem5::X86ISA::X86Interrupt
Definition: faults.hh:118
gem5::X86ISA::StartupInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:300
gem5::X86ISA::PageFault::reserved
Bitfield< 3 > reserved
Definition: faults.hh:270
gem5::X86ISA::SIMDFloatingPointFault
Definition: faults.hh:321
gem5::X86ISA::X86FaultBase
Definition: faults.hh:56
gem5::X86ISA::X86FaultBase::name
const char * name() const override
Definition: faults.hh:70
gem5::X86ISA::StartupInterrupt
Definition: faults.hh:360
gem5::X86ISA::X86FaultBase::faultName
const char * faultName
Definition: faults.hh:59
gem5::X86ISA::X86Trap
Definition: faults.hh:98
gem5::FaultBase
Definition: translation_gen.test.cc:49
gem5::X86ISA::InvalidOpcode
Definition: faults.hh:211
gem5::X86ISA::DebugException::DebugException
DebugException()
Definition: faults.hh:182
gem5::X86ISA::InvalidOpcode::InvalidOpcode
InvalidOpcode()
Definition: faults.hh:214
logging.hh
gem5::X86ISA::SystemManagementInterrupt
Definition: faults.hh:341
gem5::X86ISA::Breakpoint::Breakpoint
Breakpoint()
Definition: faults.hh:196
gem5::X86ISA::DebugException
Definition: faults.hh:179
gem5::X86ISA::DoubleFault
Definition: faults.hh:226
gem5::X86ISA::X86Abort::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:118
gem5::X86ISA::X86Abort
Definition: faults.hh:108
tlb.hh
gem5::X86ISA::X87FpExceptionPending::X87FpExceptionPending
X87FpExceptionPending()
Definition: faults.hh:304
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::GeneralProtection
Definition: faults.hh:255
gem5::X86ISA::OverflowTrap::OverflowTrap
OverflowTrap()
Definition: faults.hh:202
gem5::X86ISA::X86Trap::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:110
gem5::X86ISA::AlignmentCheck::AlignmentCheck
AlignmentCheck()
Definition: faults.hh:312
gem5::X86ISA::X86FaultBase::mnemonic
virtual const char * mnemonic() const
Definition: faults.hh:72
gem5::X86ISA::X86FaultBase::describe
virtual std::string describe() const
Definition: faults.cc:99
gem5::X86ISA::SecurityException::SecurityException
SecurityException()
Definition: faults.hh:330
gem5::X86ISA::PageFault::fetch
Bitfield< 4 > fetch
Definition: faults.hh:271
gem5::X86ISA::PageFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:136
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::MachineCheck
Definition: faults.hh:315
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::X86ISA::UnimpInstFault::name
const char * name() const override
Definition: faults.hh:128
gem5::X86ISA::X86FaultBase::X86FaultBase
X86FaultBase(const char *_faultName, const char *_mnem, const uint8_t _vector, uint64_t _errorCode=(uint64_t) -1)
Definition: faults.hh:64

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