gem5  v22.0.0.2
interrupts.hh
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49 
50 #ifndef __ARCH_X86_INTERRUPTS_HH__
51 #define __ARCH_X86_INTERRUPTS_HH__
52 
54 #include "arch/x86/faults.hh"
55 #include "arch/x86/intmessage.hh"
56 #include "arch/x86/regs/apic.hh"
57 #include "base/bitfield.hh"
58 #include "cpu/thread_context.hh"
59 #include "dev/intpin.hh"
60 #include "dev/io_device.hh"
61 #include "dev/x86/intdev.hh"
62 #include "params/X86LocalApic.hh"
63 #include "sim/eventq.hh"
64 
65 namespace gem5
66 {
67 
68 class ThreadContext;
69 class BaseCPU;
70 
71 int divideFromConf(uint32_t conf);
72 
73 namespace X86ISA
74 {
75 
77 
78 class Interrupts : public BaseInterrupts
79 {
80  protected:
81  System *sys = nullptr;
83 
84  // Storage for the APIC registers
85  uint32_t regs[NUM_APIC_REGS] = {};
86 
87  BitUnion32(LVTEntry)
88  Bitfield<7, 0> vector;
89  Bitfield<10, 8> deliveryMode;
90  Bitfield<12> status;
91  Bitfield<13> polarity;
92  Bitfield<14> remoteIRR;
93  Bitfield<15> trigger;
94  Bitfield<16> masked;
95  Bitfield<17> periodic;
96  EndBitUnion(LVTEntry)
97 
98  /*
99  * Timing related stuff.
100  */
101  EventFunctionWrapper apicTimerEvent;
102  void processApicTimerEvent();
103 
104  /*
105  * A set of variables to keep track of interrupts that don't go through
106  * the IRR.
107  */
108  bool pendingSmi = false;
109  uint8_t smiVector = 0;
110  bool pendingNmi = false;
111  uint8_t nmiVector = 0;
112  bool pendingExtInt = false;
113  uint8_t extIntVector = 0;
114  bool pendingInit = false;
115  uint8_t initVector = 0;
116  bool pendingStartup = false;
117  uint8_t startupVector = 0;
118  bool startedUp = false;
119 
120  // This is a quick check whether any of the above (except ExtInt) are set.
121  bool pendingUnmaskableInt = false;
122 
123  // A count of how many IPIs are in flight.
124  int pendingIPIs = 0;
125 
126  /*
127  * IRR and ISR maintenance.
128  */
129  uint8_t IRRV = 0;
130  uint8_t ISRV = 0;
131 
132  int
134  {
135  int offset = 7;
136  do {
137  if (regs[base + offset] != 0) {
138  return offset * 32 + findMsbSet(regs[base + offset]);
139  }
140  } while (offset--);
141  return 0;
142  }
143 
144  void
146  {
148  }
149 
150  void
152  {
154  }
155 
156  void
158  {
159  regs[base + (vector / 32)] |= (1 << (vector % 32));
160  }
161 
162  void
164  {
165  regs[base + (vector / 32)] &= ~(1 << (vector % 32));
166  }
167 
168  bool
170  {
171  return bits(regs[base + (vector / 32)], vector % 32);
172  }
173 
174  Tick clockPeriod() const { return clockDomain.clockPeriod(); }
175 
176  void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
177 
178  int initialApicId = 0;
179 
180  // Ports for interrupt messages.
183 
184  // Pins for wired interrupts.
187 
188  // Port for memory mapped register accesses.
190 
193 
194  public:
195 
196  int getInitialApicId() { return initialApicId; }
197 
198  /*
199  * Params stuff.
200  */
201  using Params = X86LocalApicParams;
202 
203  void setThreadContext(ThreadContext *_tc) override;
204 
205  /*
206  * Initialize this object by registering it with the IO APIC.
207  */
208  void init() override;
209 
210  /*
211  * Functions to interact with the interrupt port.
212  */
213  Tick read(PacketPtr pkt);
214  Tick write(PacketPtr pkt);
216  void completeIPI(PacketPtr pkt);
217 
218  bool
220  {
221  LVTEntry entry = regs[APIC_LVT_TIMER];
222  if (!entry.masked)
223  requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
224  return entry.periodic;
225  }
226 
229 
230  void raiseInterruptPin(int number);
231  void lowerInterruptPin(int number);
232 
233  Port &
234  getPort(const std::string &if_name,
235  PortID idx=InvalidPortID) override
236  {
237  if (if_name == "int_requestor") {
238  return intRequestPort;
239  } else if (if_name == "int_responder") {
240  return intResponsePort;
241  } else if (if_name == "pio") {
242  return pioPort;
243  } else if (if_name == "lint0") {
244  return lint0Pin;
245  } else if (if_name == "lint1") {
246  return lint1Pin;
247  } else {
248  return SimObject::getPort(if_name, idx);
249  }
250  }
251 
252  /*
253  * Functions to access and manipulate the APIC's registers.
254  */
255 
256  uint32_t readReg(ApicRegIndex miscReg);
257  void setReg(ApicRegIndex reg, uint32_t val);
258  void
260  {
261  regs[reg] = val;
262  }
263 
264  /*
265  * Constructor.
266  */
267 
268  Interrupts(const Params &p);
269 
270  /*
271  * Functions for retrieving interrupts for the CPU to handle.
272  */
273 
274  bool checkInterrupts() const override;
281  bool checkInterruptsRaw() const;
288  Fault getInterrupt() override;
289  void updateIntrInfo() override;
290 
291  /*
292  * Serialization.
293  */
294  void serialize(CheckpointOut &cp) const override;
295  void unserialize(CheckpointIn &cp) override;
296 
297  /*
298  * Old functions needed for compatability but which will be phased out
299  * eventually.
300  */
301  void
302  post(int int_num, int index) override
303  {
304  panic("Interrupts::post unimplemented!\n");
305  }
306 
307  void
308  clear(int int_num, int index) override
309  {
310  panic("Interrupts::clear unimplemented!\n");
311  }
312 
313  void
314  clearAll() override
315  {
316  panic("Interrupts::clearAll unimplemented!\n");
317  }
318 };
319 
320 } // namespace X86ISA
321 } // namespace gem5
322 
323 #endif // __ARCH_X86_INTERRUPTS_HH__
gem5::X86ISA::level
Bitfield< 20 > level
Definition: intmessage.hh:51
gem5::X86ISA::Interrupts::pendingStartup
bool pendingStartup
Definition: interrupts.hh:116
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::X86ISA::Interrupts::read
Tick read(PacketPtr pkt)
Definition: interrupts.cc:194
gem5::X86ISA::Interrupts::extIntVector
uint8_t extIntVector
Definition: interrupts.hh:113
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::X86ISA::Interrupts::sys
System * sys
Definition: interrupts.hh:81
gem5::X86ISA::Interrupts::clear
void clear(int int_num, int index) override
Definition: interrupts.hh:308
io_device.hh
apic.hh
gem5::X86ISA::Interrupts::smiVector
uint8_t smiVector
Definition: interrupts.hh:109
gem5::X86ISA::Interrupts::remoteIRR
Bitfield< 14 > remoteIRR
Definition: interrupts.hh:92
gem5::X86ISA::Interrupts::periodic
Bitfield< 17 > periodic
Definition: interrupts.hh:95
gem5::X86ISA::Interrupts::vector
vector
Definition: interrupts.hh:88
gem5::divideFromConf
int divideFromConf(uint32_t conf)
Definition: interrupts.cc:71
gem5::X86ISA::Interrupts::lowerInterruptPin
void lowerInterruptPin(int number)
Definition: interrupts.cc:303
gem5::X86ISA::Interrupts::intResponsePort
IntResponsePort< Interrupts > intResponsePort
Definition: interrupts.hh:181
gem5::X86ISA::Interrupts::setRegNoEffect
void setRegNoEffect(ApicRegIndex reg, uint32_t val)
Definition: interrupts.hh:259
gem5::X86ISA::Interrupts::setReg
void setReg(ApicRegIndex reg, uint32_t val)
Definition: interrupts.cc:441
gem5::X86ISA::Interrupts::checkInterrupts
bool checkInterrupts() const override
Definition: interrupts.cc:665
gem5::X86ISA::ApicRegIndex
ApicRegIndex
Definition: apic.hh:39
gem5::X86ISA::Interrupts::checkInterruptsRaw
bool checkInterruptsRaw() const
Check if there are pending interrupts without ignoring the interrupts disabled flag.
Definition: interrupts.cc:687
gem5::X86ISA::Interrupts::findRegArrayMSB
int findRegArrayMSB(ApicRegIndex base)
Definition: interrupts.hh:133
gem5::BaseInterrupts
Definition: interrupts.hh:41
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::Interrupts::pendingUnmaskableInt
bool pendingUnmaskableInt
Definition: interrupts.hh:121
gem5::X86ISA::Interrupts::setThreadContext
void setThreadContext(ThreadContext *_tc) override
Definition: interrupts.cc:312
intmessage.hh
gem5::X86ISA::decodeAddr
ApicRegIndex decodeAddr(Addr paddr)
Definition: interrupts.cc:85
gem5::X86ISA::Interrupts::EndBitUnion
EndBitUnion(LVTEntry) EventFunctionWrapper apicTimerEvent
gem5::X86ISA::offset
offset
Definition: misc.hh:1024
gem5::X86ISA::Interrupts::lint0Pin
IntSinkPin< Interrupts > lint0Pin
Definition: interrupts.hh:185
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::X86ISA::Interrupts::getInitialApicId
int getInitialApicId()
Definition: interrupts.hh:196
gem5::X86ISA::Interrupts::processApicTimerEvent
void processApicTimerEvent()
Definition: interrupts.cc:821
gem5::X86ISA::Interrupts::clockDomain
ClockDomain & clockDomain
Definition: interrupts.hh:82
gem5::X86ISA::Interrupts::trigger
Bitfield< 15 > trigger
Definition: interrupts.hh:93
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::X86ISA::Interrupts::Interrupts
Interrupts(const Params &p)
Definition: interrupts.cc:634
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:246
gem5::X86ISA::Interrupts::initialApicId
int initialApicId
Definition: interrupts.hh:178
faults.hh
gem5::X86ISA::Interrupts::updateIRRV
void updateIRRV()
Definition: interrupts.hh:145
gem5::X86ISA::Interrupts::pendingExtInt
bool pendingExtInt
Definition: interrupts.hh:112
gem5::X86ISA::Interrupts::post
void post(int int_num, int index) override
Definition: interrupts.hh:302
gem5::X86ISA::Interrupts::completeIPI
void completeIPI(PacketPtr pkt)
Definition: interrupts.cc:368
gem5::X86ISA::Interrupts::clearAll
void clearAll() override
Definition: interrupts.hh:314
gem5::X86ISA::Interrupts::pendingIPIs
int pendingIPIs
Definition: interrupts.hh:124
gem5::X86ISA::Interrupts::getIntAddrRange
AddrRangeList getIntAddrRange() const
Definition: interrupts.cc:392
gem5::X86ISA::Interrupts::lint1Pin
IntSinkPin< Interrupts > lint1Pin
Definition: interrupts.hh:186
gem5::X86ISA::Interrupts::updateIntrInfo
void updateIntrInfo() override
Definition: interrupts.cc:729
gem5::X86ISA::Interrupts::ISRV
uint8_t ISRV
Definition: interrupts.hh:130
gem5::X86ISA::IntRequestPort
Definition: intdev.hh:100
gem5::X86ISA::Interrupts::pendingSmi
bool pendingSmi
Definition: interrupts.hh:108
gem5::System
Definition: system.hh:75
gem5::X86ISA::Interrupts::intRequestPort
IntRequestPort< Interrupts > intRequestPort
Definition: interrupts.hh:182
gem5::X86ISA::Interrupts::pendingInit
bool pendingInit
Definition: interrupts.hh:114
bitfield.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::X86ISA::APIC_LVT_TIMER
@ APIC_LVT_TIMER
Definition: apic.hh:60
intdev.hh
gem5::ClockDomain
The ClockDomain provides clock to group of clocked objects bundled under the same clock domain.
Definition: clock_domain.hh:71
gem5::MaxAddr
const Addr MaxAddr
Definition: types.hh:171
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::Interrupts::raiseInterruptPin
void raiseInterruptPin(int number)
Definition: interrupts.cc:278
gem5::X86ISA::Interrupts::pioPort
PioPort< Interrupts > pioPort
Definition: interrupts.hh:189
gem5::X86ISA::Interrupts::IRRV
uint8_t IRRV
Definition: interrupts.hh:129
gem5::X86ISA::Interrupts::nmiVector
uint8_t nmiVector
Definition: interrupts.hh:111
gem5::X86ISA::Interrupts::triggerTimerInterrupt
bool triggerTimerInterrupt()
Definition: interrupts.hh:219
gem5::X86ISA::APIC_INTERRUPT_REQUEST_BASE
@ APIC_INTERRUPT_REQUEST_BASE
Definition: apic.hh:55
gem5::X86ISA::Interrupts
Definition: interrupts.hh:78
gem5::X86ISA::Interrupts::deliveryMode
Bitfield< 10, 8 > deliveryMode
Definition: interrupts.hh:89
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::X86ISA::Interrupts::getRegArrayBit
bool getRegArrayBit(ApicRegIndex base, uint8_t vector)
Definition: interrupts.hh:169
gem5::X86ISA::Interrupts::masked
Bitfield< 16 > masked
Definition: interrupts.hh:94
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::Interrupts::pendingNmi
bool pendingNmi
Definition: interrupts.hh:110
gem5::X86ISA::Interrupts::regs
uint32_t regs[NUM_APIC_REGS]
Definition: interrupts.hh:85
gem5::X86ISA::Interrupts::readReg
uint32_t readReg(ApicRegIndex miscReg)
Definition: interrupts.cc:403
gem5::X86ISA::Interrupts::hasPendingUnmaskable
bool hasPendingUnmaskable() const
Check if there are pending unmaskable interrupts.
Definition: interrupts.hh:287
gem5::X86ISA::Interrupts::BitUnion32
BitUnion32(LVTEntry) Bitfield< 7
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::X86ISA::Interrupts::startupVector
uint8_t startupVector
Definition: interrupts.hh:117
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::X86ISA::Interrupts::pioDelay
Tick pioDelay
Definition: interrupts.hh:191
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::IntResponsePort
Definition: intdev.hh:59
gem5::X86ISA::Interrupts::requestInterrupt
void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level)
Definition: interrupts.cc:228
gem5::X86ISA::Interrupts::write
Tick write(PacketPtr pkt)
Definition: interrupts.cc:211
gem5::X86ISA::APIC_IN_SERVICE_BASE
@ APIC_IN_SERVICE_BASE
Definition: apic.hh:51
gem5::X86ISA::Interrupts::getInterrupt
Fault getInterrupt() override
Definition: interrupts.cc:695
gem5::IntSinkPin
Definition: intpin.hh:78
interrupts.hh
gem5::X86ISA::Interrupts::Params
X86LocalApicParams Params
Definition: interrupts.hh:201
gem5::X86ISA::Interrupts::status
Bitfield< 12 > status
Definition: interrupts.hh:90
gem5::X86ISA::Interrupts::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: interrupts.cc:327
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::findMsbSet
constexpr int findMsbSet(uint64_t val)
Returns the bit position of the MSB that is set in the input.
Definition: bitfield.hh:260
gem5::X86ISA::Interrupts::pioAddr
Addr pioAddr
Definition: interrupts.hh:192
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
intpin.hh
gem5::X86ISA::Interrupts::clearRegArrayBit
void clearRegArrayBit(ApicRegIndex base, uint8_t vector)
Definition: interrupts.hh:163
std::list< AddrRange >
gem5::X86ISA::Interrupts::updateISRV
void updateISRV()
Definition: interrupts.hh:151
gem5::BaseInterrupts::Params
BaseInterruptsParams Params
Definition: interrupts.hh:47
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::Interrupts::setRegArrayBit
void setRegArrayBit(ApicRegIndex base, uint8_t vector)
Definition: interrupts.hh:157
gem5::ClockDomain::clockPeriod
Tick clockPeriod() const
Get the clock period.
Definition: clock_domain.hh:108
gem5::X86ISA::Interrupts::polarity
Bitfield< 13 > polarity
Definition: interrupts.hh:91
gem5::X86ISA::Interrupts::startedUp
bool startedUp
Definition: interrupts.hh:118
gem5::X86ISA::Interrupts::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: interrupts.hh:234
gem5::X86ISA::Interrupts::recvMessage
Tick recvMessage(PacketPtr pkt)
Definition: interrupts.cc:340
gem5::X86ISA::Interrupts::getAddrRanges
AddrRangeList getAddrRanges() const
Definition: interrupts.cc:382
gem5::PioPort
The PioPort class is a programmed i/o port that all devices that are sensitive to an address range us...
Definition: io_device.hh:63
thread_context.hh
gem5::X86ISA::Interrupts::clockPeriod
Tick clockPeriod() const
Definition: interrupts.hh:174
gem5::X86ISA::Interrupts::initVector
uint8_t initVector
Definition: interrupts.hh:115
gem5::X86ISA::Interrupts::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: interrupts.cc:789
gem5::X86ISA::Interrupts::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: interrupts.cc:764
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::NUM_APIC_REGS
@ NUM_APIC_REGS
Definition: apic.hh:72
eventq.hh

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