gem5  v21.1.0.2
interrupts.hh
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49 
50 #ifndef __ARCH_X86_INTERRUPTS_HH__
51 #define __ARCH_X86_INTERRUPTS_HH__
52 
54 #include "arch/x86/faults.hh"
55 #include "arch/x86/intmessage.hh"
56 #include "arch/x86/regs/apic.hh"
57 #include "base/bitfield.hh"
58 #include "cpu/thread_context.hh"
59 #include "dev/io_device.hh"
60 #include "dev/x86/intdev.hh"
61 #include "params/X86LocalApic.hh"
62 #include "sim/eventq.hh"
63 
64 namespace gem5
65 {
66 
67 class ThreadContext;
68 class BaseCPU;
69 
70 int divideFromConf(uint32_t conf);
71 
72 namespace X86ISA
73 {
74 
76 
77 class Interrupts : public BaseInterrupts
78 {
79  protected:
82 
83  // Storage for the APIC registers
84  uint32_t regs[NUM_APIC_REGS];
85 
86  BitUnion32(LVTEntry)
87  Bitfield<7, 0> vector;
88  Bitfield<10, 8> deliveryMode;
89  Bitfield<12> status;
90  Bitfield<13> polarity;
91  Bitfield<14> remoteIRR;
92  Bitfield<15> trigger;
93  Bitfield<16> masked;
94  Bitfield<17> periodic;
95  EndBitUnion(LVTEntry)
96 
97  /*
98  * Timing related stuff.
99  */
100  EventFunctionWrapper apicTimerEvent;
101  void processApicTimerEvent();
102 
103  /*
104  * A set of variables to keep track of interrupts that don't go through
105  * the IRR.
106  */
108  uint8_t smiVector;
110  uint8_t nmiVector;
112  uint8_t extIntVector;
114  uint8_t initVector;
116  uint8_t startupVector;
117  bool startedUp;
118 
119  // This is a quick check whether any of the above (except ExtInt) are set.
121 
122  // A count of how many IPIs are in flight.
124 
125  /*
126  * IRR and ISR maintenance.
127  */
128  uint8_t IRRV;
129  uint8_t ISRV;
130 
131  int
133  {
134  int offset = 7;
135  do {
136  if (regs[base + offset] != 0) {
137  return offset * 32 + findMsbSet(regs[base + offset]);
138  }
139  } while (offset--);
140  return 0;
141  }
142 
143  void
145  {
147  }
148 
149  void
151  {
153  }
154 
155  void
157  {
158  regs[base + (vector / 32)] |= (1 << (vector % 32));
159  }
160 
161  void
163  {
164  regs[base + (vector / 32)] &= ~(1 << (vector % 32));
165  }
166 
167  bool
169  {
170  return bits(regs[base + (vector / 32)], vector % 32);
171  }
172 
173  Tick clockPeriod() const { return clockDomain.clockPeriod(); }
174 
175  void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
176 
178 
179  // Ports for interrupts.
182 
183  // Port for memory mapped register accesses.
185 
188 
189  public:
190 
191  int getInitialApicId() { return initialApicId; }
192 
193  /*
194  * Params stuff.
195  */
196  using Params = X86LocalApicParams;
197 
198  void setThreadContext(ThreadContext *_tc) override;
199 
200  /*
201  * Initialize this object by registering it with the IO APIC.
202  */
203  void init() override;
204 
205  /*
206  * Functions to interact with the interrupt port.
207  */
208  Tick read(PacketPtr pkt);
209  Tick write(PacketPtr pkt);
211  void completeIPI(PacketPtr pkt);
212 
213  bool
215  {
216  LVTEntry entry = regs[APIC_LVT_TIMER];
217  if (!entry.masked)
218  requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
219  return entry.periodic;
220  }
221 
224 
225  Port &getPort(const std::string &if_name,
226  PortID idx=InvalidPortID) override
227  {
228  if (if_name == "int_requestor") {
229  return intRequestPort;
230  } else if (if_name == "int_responder") {
231  return intResponsePort;
232  } else if (if_name == "pio") {
233  return pioPort;
234  }
235  return SimObject::getPort(if_name, idx);
236  }
237 
238  /*
239  * Functions to access and manipulate the APIC's registers.
240  */
241 
242  uint32_t readReg(ApicRegIndex miscReg);
243  void setReg(ApicRegIndex reg, uint32_t val);
244  void
246  {
247  regs[reg] = val;
248  }
249 
250  /*
251  * Constructor.
252  */
253 
254  Interrupts(const Params &p);
255 
256  /*
257  * Functions for retrieving interrupts for the CPU to handle.
258  */
259 
260  bool checkInterrupts() const override;
267  bool checkInterruptsRaw() const;
274  Fault getInterrupt() override;
275  void updateIntrInfo() override;
276 
277  /*
278  * Serialization.
279  */
280  void serialize(CheckpointOut &cp) const override;
281  void unserialize(CheckpointIn &cp) override;
282 
283  /*
284  * Old functions needed for compatability but which will be phased out
285  * eventually.
286  */
287  void
288  post(int int_num, int index) override
289  {
290  panic("Interrupts::post unimplemented!\n");
291  }
292 
293  void
294  clear(int int_num, int index) override
295  {
296  panic("Interrupts::clear unimplemented!\n");
297  }
298 
299  void
300  clearAll() override
301  {
302  panic("Interrupts::clearAll unimplemented!\n");
303  }
304 };
305 
306 } // namespace X86ISA
307 } // namespace gem5
308 
309 #endif // __ARCH_X86_INTERRUPTS_HH__
gem5::X86ISA::level
Bitfield< 20 > level
Definition: intmessage.hh:51
gem5::X86ISA::Interrupts::pendingStartup
bool pendingStartup
Definition: interrupts.hh:115
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::X86ISA::Interrupts::read
Tick read(PacketPtr pkt)
Definition: interrupts.cc:193
gem5::X86ISA::Interrupts::extIntVector
uint8_t extIntVector
Definition: interrupts.hh:112
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::X86ISA::Interrupts::sys
System * sys
Definition: interrupts.hh:80
gem5::X86ISA::Interrupts::clear
void clear(int int_num, int index) override
Definition: interrupts.hh:294
io_device.hh
apic.hh
gem5::X86ISA::Interrupts::smiVector
uint8_t smiVector
Definition: interrupts.hh:108
gem5::X86ISA::Interrupts::remoteIRR
Bitfield< 14 > remoteIRR
Definition: interrupts.hh:91
gem5::X86ISA::Interrupts::periodic
Bitfield< 17 > periodic
Definition: interrupts.hh:94
gem5::X86ISA::Interrupts::vector
vector
Definition: interrupts.hh:87
gem5::divideFromConf
int divideFromConf(uint32_t conf)
Definition: interrupts.cc:70
gem5::X86ISA::Interrupts::intResponsePort
IntResponsePort< Interrupts > intResponsePort
Definition: interrupts.hh:180
gem5::X86ISA::Interrupts::setRegNoEffect
void setRegNoEffect(ApicRegIndex reg, uint32_t val)
Definition: interrupts.hh:245
gem5::X86ISA::Interrupts::setReg
void setReg(ApicRegIndex reg, uint32_t val)
Definition: interrupts.cc:406
gem5::X86ISA::Interrupts::checkInterrupts
bool checkInterrupts() const override
Definition: interrupts.cc:624
gem5::X86ISA::ApicRegIndex
ApicRegIndex
Definition: apic.hh:39
gem5::X86ISA::Interrupts::checkInterruptsRaw
bool checkInterruptsRaw() const
Check if there are pending interrupts without ignoring the interrupts disabled flag.
Definition: interrupts.cc:646
gem5::X86ISA::Interrupts::findRegArrayMSB
int findRegArrayMSB(ApicRegIndex base)
Definition: interrupts.hh:132
gem5::BaseInterrupts
Definition: interrupts.hh:41
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::Interrupts::pendingUnmaskableInt
bool pendingUnmaskableInt
Definition: interrupts.hh:120
gem5::X86ISA::Interrupts::setThreadContext
void setThreadContext(ThreadContext *_tc) override
Definition: interrupts.cc:277
intmessage.hh
gem5::X86ISA::decodeAddr
ApicRegIndex decodeAddr(Addr paddr)
Definition: interrupts.cc:84
gem5::X86ISA::Interrupts::EndBitUnion
EndBitUnion(LVTEntry) EventFunctionWrapper apicTimerEvent
gem5::X86ISA::offset
offset
Definition: misc.hh:1030
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::X86ISA::Interrupts::getInitialApicId
int getInitialApicId()
Definition: interrupts.hh:191
gem5::X86ISA::Interrupts::processApicTimerEvent
void processApicTimerEvent()
Definition: interrupts.cc:780
gem5::X86ISA::Interrupts::clockDomain
ClockDomain & clockDomain
Definition: interrupts.hh:81
gem5::X86ISA::Interrupts::trigger
Bitfield< 15 > trigger
Definition: interrupts.hh:92
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::X86ISA::Interrupts::Interrupts
Interrupts(const Params &p)
Definition: interrupts.cc:599
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::X86ISA::Interrupts::initialApicId
int initialApicId
Definition: interrupts.hh:177
faults.hh
gem5::X86ISA::Interrupts::updateIRRV
void updateIRRV()
Definition: interrupts.hh:144
gem5::X86ISA::Interrupts::pendingExtInt
bool pendingExtInt
Definition: interrupts.hh:111
gem5::X86ISA::Interrupts::post
void post(int int_num, int index) override
Definition: interrupts.hh:288
gem5::X86ISA::Interrupts::completeIPI
void completeIPI(PacketPtr pkt)
Definition: interrupts.cc:333
gem5::X86ISA::Interrupts::clearAll
void clearAll() override
Definition: interrupts.hh:300
gem5::X86ISA::Interrupts::pendingIPIs
int pendingIPIs
Definition: interrupts.hh:123
gem5::X86ISA::Interrupts::getIntAddrRange
AddrRangeList getIntAddrRange() const
Definition: interrupts.cc:357
gem5::X86ISA::Interrupts::updateIntrInfo
void updateIntrInfo() override
Definition: interrupts.cc:688
gem5::X86ISA::Interrupts::ISRV
uint8_t ISRV
Definition: interrupts.hh:129
gem5::X86ISA::IntRequestPort
Definition: intdev.hh:100
gem5::X86ISA::Interrupts::pendingSmi
bool pendingSmi
Definition: interrupts.hh:107
gem5::System
Definition: system.hh:77
gem5::X86ISA::Interrupts::intRequestPort
IntRequestPort< Interrupts > intRequestPort
Definition: interrupts.hh:181
gem5::X86ISA::Interrupts::pendingInit
bool pendingInit
Definition: interrupts.hh:113
bitfield.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::X86ISA::APIC_LVT_TIMER
@ APIC_LVT_TIMER
Definition: apic.hh:60
intdev.hh
gem5::ClockDomain
The ClockDomain provides clock to group of clocked objects bundled under the same clock domain.
Definition: clock_domain.hh:71
gem5::MaxAddr
const Addr MaxAddr
Definition: types.hh:171
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::Interrupts::pioPort
PioPort< Interrupts > pioPort
Definition: interrupts.hh:184
gem5::X86ISA::Interrupts::IRRV
uint8_t IRRV
Definition: interrupts.hh:128
gem5::X86ISA::Interrupts::nmiVector
uint8_t nmiVector
Definition: interrupts.hh:110
gem5::X86ISA::Interrupts::triggerTimerInterrupt
bool triggerTimerInterrupt()
Definition: interrupts.hh:214
gem5::X86ISA::APIC_INTERRUPT_REQUEST_BASE
@ APIC_INTERRUPT_REQUEST_BASE
Definition: apic.hh:55
gem5::X86ISA::Interrupts
Definition: interrupts.hh:77
gem5::X86ISA::Interrupts::deliveryMode
Bitfield< 10, 8 > deliveryMode
Definition: interrupts.hh:88
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::X86ISA::Interrupts::getRegArrayBit
bool getRegArrayBit(ApicRegIndex base, uint8_t vector)
Definition: interrupts.hh:168
gem5::X86ISA::Interrupts::masked
Bitfield< 16 > masked
Definition: interrupts.hh:93
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::Interrupts::pendingNmi
bool pendingNmi
Definition: interrupts.hh:109
gem5::X86ISA::Interrupts::regs
uint32_t regs[NUM_APIC_REGS]
Definition: interrupts.hh:84
gem5::X86ISA::Interrupts::readReg
uint32_t readReg(ApicRegIndex miscReg)
Definition: interrupts.cc:368
gem5::X86ISA::Interrupts::hasPendingUnmaskable
bool hasPendingUnmaskable() const
Check if there are pending unmaskable interrupts.
Definition: interrupts.hh:273
gem5::X86ISA::Interrupts::BitUnion32
BitUnion32(LVTEntry) Bitfield< 7
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::X86ISA::Interrupts::startupVector
uint8_t startupVector
Definition: interrupts.hh:116
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::X86ISA::Interrupts::pioDelay
Tick pioDelay
Definition: interrupts.hh:186
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::IntResponsePort
Definition: intdev.hh:59
gem5::X86ISA::Interrupts::requestInterrupt
void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level)
Definition: interrupts.cc:227
gem5::X86ISA::Interrupts::write
Tick write(PacketPtr pkt)
Definition: interrupts.cc:210
gem5::X86ISA::APIC_IN_SERVICE_BASE
@ APIC_IN_SERVICE_BASE
Definition: apic.hh:51
gem5::X86ISA::Interrupts::getInterrupt
Fault getInterrupt() override
Definition: interrupts.cc:654
interrupts.hh
gem5::X86ISA::Interrupts::Params
X86LocalApicParams Params
Definition: interrupts.hh:196
gem5::X86ISA::Interrupts::status
Bitfield< 12 > status
Definition: interrupts.hh:89
gem5::X86ISA::Interrupts::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: interrupts.cc:292
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::findMsbSet
constexpr int findMsbSet(uint64_t val)
Returns the bit position of the MSB that is set in the input.
Definition: bitfield.hh:263
gem5::X86ISA::Interrupts::pioAddr
Addr pioAddr
Definition: interrupts.hh:187
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::X86ISA::Interrupts::clearRegArrayBit
void clearRegArrayBit(ApicRegIndex base, uint8_t vector)
Definition: interrupts.hh:162
std::list< AddrRange >
gem5::X86ISA::Interrupts::updateISRV
void updateISRV()
Definition: interrupts.hh:150
gem5::BaseInterrupts::Params
BaseInterruptsParams Params
Definition: interrupts.hh:47
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::Interrupts::setRegArrayBit
void setRegArrayBit(ApicRegIndex base, uint8_t vector)
Definition: interrupts.hh:156
gem5::ClockDomain::clockPeriod
Tick clockPeriod() const
Get the clock period.
Definition: clock_domain.hh:108
gem5::X86ISA::Interrupts::polarity
Bitfield< 13 > polarity
Definition: interrupts.hh:90
gem5::X86ISA::Interrupts::startedUp
bool startedUp
Definition: interrupts.hh:117
gem5::X86ISA::Interrupts::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: interrupts.hh:225
gem5::X86ISA::Interrupts::recvMessage
Tick recvMessage(PacketPtr pkt)
Definition: interrupts.cc:305
gem5::X86ISA::Interrupts::getAddrRanges
AddrRangeList getAddrRanges() const
Definition: interrupts.cc:347
gem5::PioPort
The PioPort class is a programmed i/o port that all devices that are sensitive to an address range us...
Definition: io_device.hh:63
thread_context.hh
gem5::X86ISA::Interrupts::clockPeriod
Tick clockPeriod() const
Definition: interrupts.hh:173
gem5::X86ISA::Interrupts::initVector
uint8_t initVector
Definition: interrupts.hh:114
gem5::X86ISA::Interrupts::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: interrupts.cc:748
gem5::X86ISA::Interrupts::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: interrupts.cc:723
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::NUM_APIC_REGS
@ NUM_APIC_REGS
Definition: apic.hh:72
eventq.hh

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