gem5  v20.1.0.0
gic_v3_cpu_interface.hh
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40 
41 #ifndef __DEV_ARM_GICV3_CPU_INTERFACE_H__
42 #define __DEV_ARM_GICV3_CPU_INTERFACE_H__
43 
44 #include "arch/arm/isa_device.hh"
45 #include "dev/arm/gic_v3.hh"
46 
47 class Gicv3Distributor;
48 class Gicv3Redistributor;
49 
51 {
52  private:
53 
54  friend class Gicv3Distributor;
55  friend class Gicv3Redistributor;
56 
57  protected:
58 
62  uint32_t cpuId;
63 
65 
66  BitUnion64(ICC_CTLR_EL1)
67  Bitfield<63, 20> res0_3;
68  Bitfield<19> ExtRange;
69  Bitfield<18> RSS;
70  Bitfield<17, 16> res0_2;
71  Bitfield<15> A3V;
72  Bitfield<14> SEIS;
73  Bitfield<13, 11> IDbits;
74  Bitfield<10, 8> PRIbits;
75  Bitfield<7> res0_1;
76  Bitfield<6> PMHE;
77  Bitfield<5, 2> res0_0;
78  Bitfield<1> EOImode;
79  Bitfield<0> CBPR;
80  EndBitUnion(ICC_CTLR_EL1)
81 
82  BitUnion64(ICC_CTLR_EL3)
83  Bitfield<63, 20> res0_2;
84  Bitfield<19> ExtRange;
85  Bitfield<18> RSS;
86  Bitfield<17> nDS;
87  Bitfield<16> res0_1;
88  Bitfield<15> A3V;
89  Bitfield<14> SEIS;
90  Bitfield<13, 11> IDbits;
91  Bitfield<10, 8> PRIbits;
92  Bitfield<7> res0_0;
93  Bitfield<6> PMHE;
94  Bitfield<5> RM;
95  Bitfield<4> EOImode_EL1NS;
96  Bitfield<3> EOImode_EL1S;
97  Bitfield<2> EOImode_EL3;
98  Bitfield<1> CBPR_EL1NS;
99  Bitfield<0> CBPR_EL1S;
100  EndBitUnion(ICC_CTLR_EL3)
101 
102  BitUnion64(ICC_IGRPEN0_EL1)
103  Bitfield<63, 1> res0;
104  Bitfield<0> Enable;
105  EndBitUnion(ICC_IGRPEN0_EL1)
106 
107  BitUnion64(ICC_IGRPEN1_EL1)
108  Bitfield<63, 1> res0;
109  Bitfield<0> Enable;
110  EndBitUnion(ICC_IGRPEN1_EL1)
111 
112  BitUnion64(ICC_IGRPEN1_EL3)
113  Bitfield<63, 2> res0;
114  Bitfield<1> EnableGrp1S;
115  Bitfield<0> EnableGrp1NS;
116  EndBitUnion(ICC_IGRPEN1_EL3)
117 
118  BitUnion64(ICC_SRE_EL1)
119  Bitfield<63, 3> res0;
120  Bitfield<2> DIB;
121  Bitfield<1> DFB;
122  Bitfield<0> SRE;
123  EndBitUnion(ICC_SRE_EL1)
124 
125  BitUnion64(ICC_SRE_EL2)
126  Bitfield<63, 4> res0;
127  Bitfield<3> Enable;
128  Bitfield<2> DIB;
129  Bitfield<1> DFB;
130  Bitfield<0> SRE;
131  EndBitUnion(ICC_SRE_EL2)
132 
133  BitUnion64(ICC_SRE_EL3)
134  Bitfield<63, 4> res0;
135  Bitfield<3> Enable;
136  Bitfield<2> DIB;
137  Bitfield<1> DFB;
138  Bitfield<0> SRE;
139  EndBitUnion(ICC_SRE_EL3)
140 
141  static const uint8_t PRIORITY_BITS = 5;
142 
143  // Minimum BPR for Secure, or when security not enabled
144  static const uint8_t GIC_MIN_BPR = 2;
145  // Minimum BPR for Nonsecure when security is enabled
146  static const uint8_t GIC_MIN_BPR_NS = GIC_MIN_BPR + 1;
147 
148  static const uint8_t VIRTUAL_PRIORITY_BITS = 5;
149  static const uint8_t VIRTUAL_PREEMPTION_BITS = 5;
150  static const uint8_t VIRTUAL_NUM_LIST_REGS = 16;
151 
152  static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS;
153 
154  typedef struct {
155  uint32_t intid;
156  uint8_t prio;
158  } hppi_t;
159 
161 
162  // GIC CPU interface memory mapped control registers (legacy)
163  enum {
164  GICC_CTLR = 0x0000,
165  GICC_PMR = 0x0004,
166  GICC_BPR = 0x0008,
167  GICC_IAR = 0x000C,
168  GICC_EOIR = 0x0010,
169  GICC_RPR = 0x0014,
170  GICC_HPPI = 0x0018,
171  GICC_ABPR = 0x001C,
172  GICC_AIAR = 0x0020,
173  GICC_AEOIR = 0x0024,
174  GICC_AHPPIR = 0x0028,
175  GICC_STATUSR = 0x002C,
176  GICC_IIDR = 0x00FC,
177  };
178 
179  static const AddrRange GICC_APR;
180  static const AddrRange GICC_NSAPR;
181 
182  // GIC CPU virtual interface memory mapped control registers (legacy)
183  enum {
184  GICH_HCR = 0x0000,
185  GICH_VTR = 0x0004,
186  GICH_VMCR = 0x0008,
187  GICH_MISR = 0x0010,
188  GICH_EISR = 0x0020,
189  GICH_ELRSR = 0x0030,
190  };
191 
192  static const AddrRange GICH_APR;
193  static const AddrRange GICH_LR;
194 
195  BitUnion64(ICH_HCR_EL2)
196  Bitfield<63, 32> res0_2;
197  Bitfield<31, 27> EOIcount;
198  Bitfield<26, 15> res0_1;
199  Bitfield<14> TDIR;
200  Bitfield<13> TSEI;
201  Bitfield<12> TALL1;
202  Bitfield<11> TALL0;
203  Bitfield<10> TC;
204  Bitfield<9, 8> res0_0;
205  Bitfield<7> VGrp1DIE;
206  Bitfield<6> VGrp1EIE;
207  Bitfield<5> VGrp0DIE;
208  Bitfield<4> VGrp0EIE;
209  Bitfield<3> NPIE;
210  Bitfield<2> LRENPIE;
211  Bitfield<1> UIE;
212  Bitfield<0> En;
213  EndBitUnion(ICH_HCR_EL2)
214 
215  BitUnion64(ICH_LR_EL2)
216  Bitfield<63, 62> State;
217  Bitfield<61> HW;
218  Bitfield<60> Group;
219  Bitfield<59, 56> res0_1;
220  Bitfield<55, 48> Priority;
221  Bitfield<47, 45> res0_0;
222  Bitfield<44, 32> pINTID;
223  Bitfield<41> EOI;
224  Bitfield<31, 0> vINTID;
225  EndBitUnion(ICH_LR_EL2)
226 
227  static const uint64_t ICH_LR_EL2_STATE_INVALID = 0;
228  static const uint64_t ICH_LR_EL2_STATE_PENDING = 1;
229  static const uint64_t ICH_LR_EL2_STATE_ACTIVE = 2;
230  static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING = 3;
231 
232  BitUnion32(ICH_LRC)
233  Bitfield<31, 30> State;
234  Bitfield<29> HW;
235  Bitfield<28> Group;
236  Bitfield<27, 24> res0_1;
237  Bitfield<23, 16> Priority;
238  Bitfield<15, 13> res0_0;
239  Bitfield<12, 0> pINTID;
240  Bitfield<9> EOI;
241  EndBitUnion(ICH_LRC)
242 
243  BitUnion64(ICH_MISR_EL2)
244  Bitfield<63, 8> res0;
245  Bitfield<7> VGrp1D;
246  Bitfield<6> VGrp1E;
247  Bitfield<5> VGrp0D;
248  Bitfield<4> VGrp0E;
249  Bitfield<3> NP;
250  Bitfield<2> LRENP;
251  Bitfield<1> U;
252  Bitfield<0> EOI;
253  EndBitUnion(ICH_MISR_EL2)
254 
255  BitUnion64(ICH_VMCR_EL2)
256  Bitfield<63, 32> res0_2;
257  Bitfield<31, 24> VPMR;
258  Bitfield<23, 21> VBPR0;
259  Bitfield<20, 18> VBPR1;
260  Bitfield<17, 10> res0_1;
261  Bitfield<9> VEOIM;
262  Bitfield<8, 5> res0_0;
263  Bitfield<4> VCBPR;
264  Bitfield<3> VFIQEn;
265  Bitfield<2> VAckCtl;
266  Bitfield<1> VENG1;
267  Bitfield<0> VENG0;
268  EndBitUnion(ICH_VMCR_EL2)
269 
270  BitUnion64(ICH_VTR_EL2)
271  Bitfield<63, 32> res0_1;
272  Bitfield<31, 29> PRIbits;
273  Bitfield<28, 26> PREbits;
274  Bitfield<25, 23> IDbits;
275  Bitfield<22> SEIS;
276  Bitfield<21> A3V;
277  Bitfield<20> res1;
278  Bitfield<19> TDS;
279  Bitfield<18, 5> res0_0;
280  Bitfield<4, 0> ListRegs;
281  EndBitUnion(ICH_VTR_EL2)
282 
283  BitUnion64(ICV_CTLR_EL1)
284  Bitfield<63, 19> res0_2;
285  Bitfield<18> RSS;
286  Bitfield<17, 16> res0_1;
287  Bitfield<15> A3V;
288  Bitfield<14> SEIS;
289  Bitfield<13, 11> IDbits;
290  Bitfield<10, 8> PRIbits;
291  Bitfield<7, 2> res0_0;
292  Bitfield<1> EOImode;
293  Bitfield<0> CBPR;
294  EndBitUnion(ICV_CTLR_EL1)
295 
296  protected:
297 
298  void activateIRQ(uint32_t intid, Gicv3::GroupId group);
299  void generateSGI(RegVal val, Gicv3::GroupId group);
300  int currEL() const;
301  void deactivateIRQ(uint32_t intid, Gicv3::GroupId group);
302  void dropPriority(Gicv3::GroupId group);
303  uint64_t eoiMaintenanceInterruptStatus() const;
304  bool getHCREL2FMO() const;
305  bool getHCREL2IMO() const;
306  uint32_t getHPPIR0() const;
307  uint32_t getHPPIR1() const;
308  int getHPPVILR() const;
309  bool groupEnabled(Gicv3::GroupId group) const;
310  uint32_t groupPriorityMask(Gicv3::GroupId group);
311  bool haveEL(ArmISA::ExceptionLevel el) const;
312  int highestActiveGroup() const;
313  uint8_t highestActivePriority() const;
314  bool hppiCanPreempt();
315  bool hppviCanPreempt(int lrIdx) const;
316  bool inSecureState() const;
317  ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;
318  bool isAA64() const;
319  bool isEL3OrMon() const;
320  bool isEOISplitMode() const;
321  bool isSecureBelowEL3() const;
322  ICH_MISR_EL2 maintenanceInterruptStatus() const;
323  void resetHppi(uint32_t intid);
324  void serialize(CheckpointOut & cp) const override;
325  void unserialize(CheckpointIn & cp) override;
326  void update();
327  void updateDistributor();
328  void virtualActivateIRQ(uint32_t lrIdx);
329  void virtualDeactivateIRQ(int lrIdx);
330  uint8_t virtualDropPriority();
331  int virtualFindActive(uint32_t intid) const;
332  uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const;
333  uint8_t virtualHighestActivePriority() const;
335  bool virtualIsEOISplitMode() const;
336  void virtualUpdate();
337  RegVal bpr1(Gicv3::GroupId group);
338  bool havePendingInterrupts(void) const;
339  void clearPendingInterrupts(void);
340  void assertWakeRequest(void);
341  void deassertWakeRequest(void);
342 
343  RegVal readBankedMiscReg(ArmISA::MiscRegIndex misc_reg) const;
344  void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const;
345  public:
346 
347  Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
348 
349  void init();
350 
351  public: // BaseISADevice
352  RegVal readMiscReg(int misc_reg) override;
353  void setMiscReg(int misc_reg, RegVal val) override;
354  void setThreadContext(ThreadContext *tc) override;
355 };
356 
357 #endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__
isa_device.hh
Gicv3CPUInterface::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Write to a system register belonging to this device.
Definition: gic_v3_cpu_interface.cc:737
Gicv3CPUInterface::VGrp1DIE
Bitfield< 7 > VGrp1DIE
Definition: gic_v3_cpu_interface.hh:205
Gicv3Redistributor::activateIRQ
void activateIRQ(uint32_t int_id)
Definition: gic_v3_redistributor.cc:995
Gicv3CPUInterface::DIB
Bitfield< 2 > DIB
Definition: gic_v3_cpu_interface.hh:120
Gicv3CPUInterface::res1
Bitfield< 20 > res1
Definition: gic_v3_cpu_interface.hh:277
Gicv3CPUInterface::EOIcount
Bitfield< 31, 27 > EOIcount
Definition: gic_v3_cpu_interface.hh:197
Gicv3CPUInterface::U
Bitfield< 1 > U
Definition: gic_v3_cpu_interface.hh:251
Gicv3CPUInterface::nDS
Bitfield< 17 > nDS
Definition: gic_v3_cpu_interface.hh:86
Gicv3CPUInterface::isSecureBelowEL3
bool isSecureBelowEL3() const
Definition: gic_v3_cpu_interface.cc:2388
Gicv3CPUInterface::updateDistributor
void updateDistributor()
Definition: gic_v3_cpu_interface.cc:2024
Gicv3CPUInterface::CBPR_EL1S
Bitfield< 0 > CBPR_EL1S
Definition: gic_v3_cpu_interface.hh:99
Gicv3CPUInterface::deactivateIRQ
void deactivateIRQ(uint32_t intid, Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:1882
Gicv3CPUInterface::setThreadContext
void setThreadContext(ThreadContext *tc) override
Definition: gic_v3_cpu_interface.cc:81
Gicv3CPUInterface::ExtRange
Bitfield< 19 > ExtRange
Definition: gic_v3_cpu_interface.hh:68
Gicv3CPUInterface::EnableGrp1S
Bitfield< 1 > EnableGrp1S
Definition: gic_v3_cpu_interface.hh:114
Gicv3CPUInterface::VEOIM
Bitfield< 9 > VEOIM
Definition: gic_v3_cpu_interface.hh:261
Gicv3CPUInterface::VGrp0E
Bitfield< 4 > VGrp0E
Definition: gic_v3_cpu_interface.hh:248
ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:58
Gicv3CPUInterface::HW
Bitfield< 61 > HW
Definition: gic_v3_cpu_interface.hh:217
Gicv3CPUInterface::GICH_LR
static const AddrRange GICH_LR
Definition: gic_v3_cpu_interface.hh:193
Gicv3CPUInterface::virtualUpdate
void virtualUpdate()
Definition: gic_v3_cpu_interface.cc:2064
Gicv3CPUInterface::isEOISplitMode
bool isEOISplitMode() const
Definition: gic_v3_cpu_interface.cc:1978
Gicv3CPUInterface::cpuId
uint32_t cpuId
Definition: gic_v3_cpu_interface.hh:62
Gicv3CPUInterface::getHCREL2IMO
bool getHCREL2IMO() const
Definition: gic_v3_cpu_interface.cc:103
Gicv3CPUInterface::hppi
hppi_t hppi
Definition: gic_v3_cpu_interface.hh:160
Gicv3CPUInterface::res0_0
Bitfield< 5, 2 > res0_0
Definition: gic_v3_cpu_interface.hh:77
Gicv3CPUInterface::GIC_MIN_BPR_NS
static const uint8_t GIC_MIN_BPR_NS
Definition: gic_v3_cpu_interface.hh:146
Gicv3CPUInterface::EOI
Bitfield< 41 > EOI
Definition: gic_v3_cpu_interface.hh:223
Gicv3CPUInterface::VFIQEn
Bitfield< 3 > VFIQEn
Definition: gic_v3_cpu_interface.hh:264
Serializable
Basic support for object serialization.
Definition: serialize.hh:172
Gicv3CPUInterface::EOImode_EL1S
Bitfield< 3 > EOImode_EL1S
Definition: gic_v3_cpu_interface.hh:96
Gicv3CPUInterface::TALL0
Bitfield< 11 > TALL0
Definition: gic_v3_cpu_interface.hh:202
Gicv3CPUInterface::DFB
Bitfield< 1 > DFB
Definition: gic_v3_cpu_interface.hh:121
Gicv3CPUInterface::ICH_LR_EL2_STATE_ACTIVE
static const uint64_t ICH_LR_EL2_STATE_ACTIVE
Definition: gic_v3_cpu_interface.hh:229
Gicv3CPUInterface::VBPR0
Bitfield< 23, 21 > VBPR0
Definition: gic_v3_cpu_interface.hh:258
Gicv3CPUInterface::VCBPR
Bitfield< 4 > VCBPR
Definition: gic_v3_cpu_interface.hh:263
Gicv3CPUInterface::EndBitUnion
EndBitUnion(ICC_CTLR_EL1) BitUnion64(ICC_CTLR_EL3) Bitfield< 63
Gicv3CPUInterface::IDbits
Bitfield< 13, 11 > IDbits
Definition: gic_v3_cpu_interface.hh:73
Gicv3CPUInterface::CBPR_EL1NS
Bitfield< 1 > CBPR_EL1NS
Definition: gic_v3_cpu_interface.hh:98
Gicv3CPUInterface::VGrp0EIE
Bitfield< 4 > VGrp0EIE
Definition: gic_v3_cpu_interface.hh:208
Gicv3CPUInterface::virtualActivateIRQ
void virtualActivateIRQ(uint32_t lrIdx)
Definition: gic_v3_cpu_interface.cc:1861
Gicv3CPUInterface::virtualGroupPriorityMask
uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const
Definition: gic_v3_cpu_interface.cc:1952
Gicv3CPUInterface::resetHppi
void resetHppi(uint32_t intid)
Definition: gic_v3_cpu_interface.cc:74
Gicv3CPUInterface::GICH_APR
static const AddrRange GICH_APR
Definition: gic_v3_cpu_interface.hh:192
Gicv3CPUInterface::GICH_EISR
@ GICH_EISR
Definition: gic_v3_cpu_interface.hh:188
Gicv3CPUInterface::PREbits
Bitfield< 28, 26 > PREbits
Definition: gic_v3_cpu_interface.hh:273
Gicv3CPUInterface::VGrp0DIE
Bitfield< 5 > VGrp0DIE
Definition: gic_v3_cpu_interface.hh:207
Gicv3CPUInterface::virtualHighestActivePriority
uint8_t virtualHighestActivePriority() const
Definition: gic_v3_cpu_interface.cc:2193
Gicv3CPUInterface::eoiMaintenanceInterruptStatus
uint64_t eoiMaintenanceInterruptStatus() const
Definition: gic_v3_cpu_interface.cc:2420
Gicv3CPUInterface::GICC_IIDR
@ GICC_IIDR
Definition: gic_v3_cpu_interface.hh:176
Gicv3CPUInterface::GICC_ABPR
@ GICC_ABPR
Definition: gic_v3_cpu_interface.hh:171
Gicv3CPUInterface::LRENP
Bitfield< 2 > LRENP
Definition: gic_v3_cpu_interface.hh:250
Gicv3CPUInterface::bpr1
RegVal bpr1(Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:2541
Gicv3CPUInterface::currEL
int currEL() const
Definition: gic_v3_cpu_interface.cc:2343
Gicv3CPUInterface::getHPPIR1
uint32_t getHPPIR1() const
Definition: gic_v3_cpu_interface.cc:1677
Gicv3CPUInterface::BitUnion64
BitUnion64(ICC_CTLR_EL1) Bitfield< 63
Gicv3CPUInterface::isAA64
bool isAA64() const
Definition: gic_v3_cpu_interface.cc:2395
ArmISA
Definition: ccregs.hh:41
Gicv3CPUInterface::highestActiveGroup
int highestActiveGroup() const
Definition: gic_v3_cpu_interface.cc:2002
Gicv3CPUInterface::ICH_LR_EL2_STATE_PENDING
static const uint64_t ICH_LR_EL2_STATE_PENDING
Definition: gic_v3_cpu_interface.hh:228
Gicv3CPUInterface::hppi_t
Definition: gic_v3_cpu_interface.hh:154
Gicv3CPUInterface::res0_3
res0_3
Definition: gic_v3_cpu_interface.hh:67
Gicv3CPUInterface::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: gic_v3_cpu_interface.cc:2620
Gicv3CPUInterface::GIC_MIN_VBPR
static const uint8_t GIC_MIN_VBPR
Definition: gic_v3_cpu_interface.hh:152
Gicv3CPUInterface::GICC_CTLR
@ GICC_CTLR
Definition: gic_v3_cpu_interface.hh:164
Gicv3CPUInterface::GICH_VTR
@ GICH_VTR
Definition: gic_v3_cpu_interface.hh:185
Gicv3CPUInterface::readMiscReg
RegVal readMiscReg(int misc_reg) override
Read a system register belonging to this device.
Definition: gic_v3_cpu_interface.cc:117
Gicv3CPUInterface::CBPR
Bitfield< 0 > CBPR
Definition: gic_v3_cpu_interface.hh:79
Gicv3CPUInterface::TALL1
Bitfield< 12 > TALL1
Definition: gic_v3_cpu_interface.hh:201
Gicv3CPUInterface::inSecureState
bool inSecureState() const
Definition: gic_v3_cpu_interface.cc:2331
Gicv3CPUInterface::VGrp0D
Bitfield< 5 > VGrp0D
Definition: gic_v3_cpu_interface.hh:247
Gicv3CPUInterface::hppi_t::group
Gicv3::GroupId group
Definition: gic_v3_cpu_interface.hh:157
Gicv3CPUInterface::intSignalType
ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const
Definition: gic_v3_cpu_interface.cc:2226
cp
Definition: cprintf.cc:40
Gicv3CPUInterface::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: gic_v3_cpu_interface.cc:2612
Gicv3CPUInterface::GICC_EOIR
@ GICC_EOIR
Definition: gic_v3_cpu_interface.hh:168
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
Gicv3CPUInterface::VIRTUAL_NUM_LIST_REGS
static const uint8_t VIRTUAL_NUM_LIST_REGS
Definition: gic_v3_cpu_interface.hh:150
AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:68
Gicv3CPUInterface::EOImode_EL1NS
Bitfield< 4 > EOImode_EL1NS
Definition: gic_v3_cpu_interface.hh:95
Gicv3CPUInterface::VIRTUAL_PREEMPTION_BITS
static const uint8_t VIRTUAL_PREEMPTION_BITS
Definition: gic_v3_cpu_interface.hh:149
Gicv3CPUInterface::EOImode
Bitfield< 1 > EOImode
Definition: gic_v3_cpu_interface.hh:78
Gicv3CPUInterface::VBPR1
Bitfield< 20, 18 > VBPR1
Definition: gic_v3_cpu_interface.hh:259
ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:621
Gicv3CPUInterface::TSEI
Bitfield< 13 > TSEI
Definition: gic_v3_cpu_interface.hh:200
Gicv3CPUInterface::GIC_MIN_BPR
static const uint8_t GIC_MIN_BPR
Definition: gic_v3_cpu_interface.hh:144
Gicv3CPUInterface::TDS
Bitfield< 19 > TDS
Definition: gic_v3_cpu_interface.hh:278
Gicv3CPUInterface::Group
Bitfield< 60 > Group
Definition: gic_v3_cpu_interface.hh:218
Gicv3CPUInterface::assertWakeRequest
void assertWakeRequest(void)
Definition: gic_v3_cpu_interface.cc:2595
Gicv3CPUInterface::groupPriorityMask
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Definition: gic_v3_cpu_interface.cc:1921
Gicv3CPUInterface::EOImode_EL3
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Definition: gic_v3_cpu_interface.hh:97
Gicv3CPUInterface::deassertWakeRequest
void deassertWakeRequest(void)
Definition: gic_v3_cpu_interface.cc:2605
ArmISA::el
Bitfield< 3, 2 > el
Definition: miscregs_types.hh:69
ArmISA::InterruptTypes
InterruptTypes
Definition: interrupts.hh:57
Gicv3CPUInterface::SEIS
Bitfield< 14 > SEIS
Definition: gic_v3_cpu_interface.hh:72
Gicv3
Definition: gic_v3.hh:53
Gicv3CPUInterface::pINTID
Bitfield< 44, 32 > pINTID
Definition: gic_v3_cpu_interface.hh:222
Gicv3CPUInterface::res0_1
Bitfield< 26, 15 > res0_1
Definition: gic_v3_cpu_interface.hh:198
Gicv3CPUInterface::VENG1
Bitfield< 1 > VENG1
Definition: gic_v3_cpu_interface.hh:266
Gicv3CPUInterface::update
void update()
Definition: gic_v3_cpu_interface.cc:2030
Gicv3CPUInterface::getHCREL2FMO
bool getHCREL2FMO() const
Definition: gic_v3_cpu_interface.cc:89
Gicv3CPUInterface::State
State
Definition: gic_v3_cpu_interface.hh:216
Gicv3CPUInterface::VENG0
Bitfield< 0 > VENG0
Definition: gic_v3_cpu_interface.hh:267
Gicv3::GroupId
GroupId
Definition: gic_v3.hh:90
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Gicv3Distributor * distributor
Definition: gic_v3_cpu_interface.hh:61
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
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int getHPPVILR() const
Definition: gic_v3_cpu_interface.cc:2113
Gicv3CPUInterface::BitUnion32
BitUnion32(ICH_LRC) Bitfield< 31
Gicv3CPUInterface::GICC_HPPI
@ GICC_HPPI
Definition: gic_v3_cpu_interface.hh:170
Gicv3CPUInterface::PRIbits
Bitfield< 10, 8 > PRIbits
Definition: gic_v3_cpu_interface.hh:74
Gicv3CPUInterface::VGrp1E
Bitfield< 6 > VGrp1E
Definition: gic_v3_cpu_interface.hh:246
Gicv3CPUInterface::TC
Bitfield< 10 > TC
Definition: gic_v3_cpu_interface.hh:203
Gicv3CPUInterface::VAckCtl
Bitfield< 2 > VAckCtl
Definition: gic_v3_cpu_interface.hh:265
Gicv3CPUInterface::GICC_BPR
@ GICC_BPR
Definition: gic_v3_cpu_interface.hh:166
Gicv3CPUInterface::GICC_AIAR
@ GICC_AIAR
Definition: gic_v3_cpu_interface.hh:172
Gicv3CPUInterface::highestActivePriority
uint8_t highestActivePriority() const
Definition: gic_v3_cpu_interface.cc:2289
Gicv3CPUInterface::PMHE
Bitfield< 6 > PMHE
Definition: gic_v3_cpu_interface.hh:76
Gicv3CPUInterface::virtualIncrementEOICount
void virtualIncrementEOICount()
Definition: gic_v3_cpu_interface.cc:2214
Gicv3CPUInterface::groupEnabled
bool groupEnabled(Gicv3::GroupId group) const
Definition: gic_v3_cpu_interface.cc:2304
Gicv3CPUInterface::GICH_VMCR
@ GICH_VMCR
Definition: gic_v3_cpu_interface.hh:186
Gicv3CPUInterface::GICC_RPR
@ GICC_RPR
Definition: gic_v3_cpu_interface.hh:169
Gicv3CPUInterface::VIRTUAL_PRIORITY_BITS
static const uint8_t VIRTUAL_PRIORITY_BITS
Definition: gic_v3_cpu_interface.hh:148
Gicv3CPUInterface
Definition: gic_v3_cpu_interface.hh:50
Gicv3CPUInterface::GICC_PMR
@ GICC_PMR
Definition: gic_v3_cpu_interface.hh:165
Gicv3CPUInterface::generateSGI
EndBitUnion(ICV_CTLR_EL1) protected void generateSGI(RegVal val, Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:1771
Gicv3CPUInterface::VGrp1EIE
Bitfield< 6 > VGrp1EIE
Definition: gic_v3_cpu_interface.hh:206
Gicv3CPUInterface::A3V
Bitfield< 15 > A3V
Definition: gic_v3_cpu_interface.hh:71
Gicv3CPUInterface::UIE
Bitfield< 1 > UIE
Definition: gic_v3_cpu_interface.hh:211
Gicv3CPUInterface::TDIR
Bitfield< 14 > TDIR
Definition: gic_v3_cpu_interface.hh:199
Gicv3CPUInterface::GICC_AHPPIR
@ GICC_AHPPIR
Definition: gic_v3_cpu_interface.hh:174
Gicv3CPUInterface::dropPriority
void dropPriority(Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:1712
Gicv3CPUInterface::RM
Bitfield< 5 > RM
Definition: gic_v3_cpu_interface.hh:94
Gicv3CPUInterface::GICC_IAR
@ GICC_IAR
Definition: gic_v3_cpu_interface.hh:167
Gicv3CPUInterface::virtualFindActive
int virtualFindActive(uint32_t intid) const
Definition: gic_v3_cpu_interface.cc:1634
Gicv3CPUInterface::clearPendingInterrupts
void clearPendingInterrupts(void)
Definition: gic_v3_cpu_interface.cc:2588
Gicv3CPUInterface::SRE
Bitfield< 0 > SRE
Definition: gic_v3_cpu_interface.hh:122
Gicv3CPUInterface::readBankedMiscReg
RegVal readBankedMiscReg(ArmISA::MiscRegIndex misc_reg) const
Definition: gic_v3_cpu_interface.cc:1620
Gicv3CPUInterface::En
Bitfield< 0 > En
Definition: gic_v3_cpu_interface.hh:212
Gicv3CPUInterface::EnableGrp1NS
Bitfield< 0 > EnableGrp1NS
Definition: gic_v3_cpu_interface.hh:115
Gicv3Distributor
Definition: gic_v3_distributor.hh:48
ArmInterruptPin
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:176
ArmISA::MiscRegIndex
MiscRegIndex
Definition: miscregs.hh:56
Gicv3CPUInterface::maintenanceInterrupt
ArmInterruptPin * maintenanceInterrupt
Definition: gic_v3_cpu_interface.hh:64
Gicv3CPUInterface::gic
Gicv3 * gic
Definition: gic_v3_cpu_interface.hh:59
Gicv3CPUInterface::GICH_ELRSR
@ GICH_ELRSR
Definition: gic_v3_cpu_interface.hh:189
Gicv3CPUInterface::hppi_t::intid
uint32_t intid
Definition: gic_v3_cpu_interface.hh:155
Gicv3CPUInterface::virtualDeactivateIRQ
void virtualDeactivateIRQ(int lrIdx)
Definition: gic_v3_cpu_interface.cc:1896
Gicv3CPUInterface::NPIE
Bitfield< 3 > NPIE
Definition: gic_v3_cpu_interface.hh:209
Gicv3CPUInterface::virtualIsEOISplitMode
bool virtualIsEOISplitMode() const
Definition: gic_v3_cpu_interface.cc:1995
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
Gicv3CPUInterface::GICC_APR
static const AddrRange GICC_APR
Definition: gic_v3_cpu_interface.hh:179
Gicv3CPUInterface::VGrp1D
Bitfield< 7 > VGrp1D
Definition: gic_v3_cpu_interface.hh:245
Gicv3CPUInterface::LRENPIE
Bitfield< 2 > LRENPIE
Definition: gic_v3_cpu_interface.hh:210
Gicv3CPUInterface::getHPPIR0
uint32_t getHPPIR0() const
Definition: gic_v3_cpu_interface.cc:1651
Gicv3CPUInterface::GICH_HCR
@ GICH_HCR
Definition: gic_v3_cpu_interface.hh:184
Gicv3CPUInterface::GICC_NSAPR
static const AddrRange GICC_NSAPR
Definition: gic_v3_cpu_interface.hh:180
Gicv3CPUInterface::setBankedMiscReg
void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const
Definition: gic_v3_cpu_interface.cc:1627
Gicv3CPUInterface::GICH_MISR
@ GICH_MISR
Definition: gic_v3_cpu_interface.hh:187
Gicv3CPUInterface::hppviCanPreempt
bool hppviCanPreempt(int lrIdx) const
Definition: gic_v3_cpu_interface.cc:2157
Gicv3CPUInterface::haveEL
bool haveEL(ArmISA::ExceptionLevel el) const
Definition: gic_v3_cpu_interface.cc:2368
Gicv3CPUInterface::ListRegs
Bitfield< 4, 0 > ListRegs
Definition: gic_v3_cpu_interface.hh:280
Gicv3CPUInterface::init
void init()
Definition: gic_v3_cpu_interface.cc:67
Gicv3CPUInterface::res0_0
Bitfield< 9, 8 > res0_0
Definition: gic_v3_cpu_interface.hh:204
Gicv3CPUInterface::hppiCanPreempt
bool hppiCanPreempt()
Definition: gic_v3_cpu_interface.cc:2256
Gicv3CPUInterface::havePendingInterrupts
bool havePendingInterrupts(void) const
Definition: gic_v3_cpu_interface.cc:2582
Gicv3CPUInterface::res0
res0
Definition: gic_v3_cpu_interface.hh:103
CheckpointIn
Definition: serialize.hh:67
Gicv3CPUInterface::redistributor
Gicv3Redistributor * redistributor
Definition: gic_v3_cpu_interface.hh:60
Gicv3CPUInterface::res0_1
Bitfield< 7 > res0_1
Definition: gic_v3_cpu_interface.hh:75
Gicv3CPUInterface::hppi_t::prio
uint8_t prio
Definition: gic_v3_cpu_interface.hh:156
Gicv3CPUInterface::isEL3OrMon
bool isEL3OrMon() const
Definition: gic_v3_cpu_interface.cc:2402
Gicv3CPUInterface::res0_2
Bitfield< 17, 16 > res0_2
Definition: gic_v3_cpu_interface.hh:70
Gicv3CPUInterface::vINTID
Bitfield< 31, 0 > vINTID
Definition: gic_v3_cpu_interface.hh:224
gic_v3.hh
Gicv3Redistributor
Definition: gic_v3_redistributor.hh:52
Gicv3CPUInterface::GICC_STATUSR
@ GICC_STATUSR
Definition: gic_v3_cpu_interface.hh:175
Gicv3CPUInterface::Priority
Bitfield< 55, 48 > Priority
Definition: gic_v3_cpu_interface.hh:220
Gicv3CPUInterface::VPMR
Bitfield< 31, 24 > VPMR
Definition: gic_v3_cpu_interface.hh:257
Gicv3CPUInterface::GICC_AEOIR
@ GICC_AEOIR
Definition: gic_v3_cpu_interface.hh:173
Gicv3CPUInterface::virtualDropPriority
uint8_t virtualDropPriority()
Definition: gic_v3_cpu_interface.cc:1741
RegVal
uint64_t RegVal
Definition: types.hh:168
Gicv3CPUInterface::Enable
Bitfield< 0 > Enable
Definition: gic_v3_cpu_interface.hh:104
Gicv3CPUInterface::ICH_LR_EL2_STATE_ACTIVE_PENDING
static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING
Definition: gic_v3_cpu_interface.hh:230
Gicv3CPUInterface::maintenanceInterruptStatus
ICH_MISR_EL2 maintenanceInterruptStatus() const
Definition: gic_v3_cpu_interface.cc:2453
Gicv3CPUInterface::NP
Bitfield< 3 > NP
Definition: gic_v3_cpu_interface.hh:249
Gicv3CPUInterface::RSS
Bitfield< 18 > RSS
Definition: gic_v3_cpu_interface.hh:69

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