gem5  v20.1.0.0
op_encodings.hh
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1 /*
2  * Copyright (c) 2016-2017 Advanced Micro Devices, Inc.
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5  * For use for simulation and test purposes only
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19  * software without specific prior written permission.
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21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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33  * Authors: Anthony Gutierrez
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35 
36 #ifndef __ARCH_GCN3_INSTS_OP_ENCODINGS_HH__
37 #define __ARCH_GCN3_INSTS_OP_ENCODINGS_HH__
38 
39 #include "arch/gcn3/gpu_decoder.hh"
42 #include "arch/gcn3/operand.hh"
43 #include "debug/GCN3.hh"
44 #include "debug/GPUExec.hh"
46 
47 namespace Gcn3ISA
48 {
50  {
51  uint64_t baseAddr : 48;
52  uint32_t stride : 14;
53  uint32_t cacheSwizzle : 1;
54  uint32_t swizzleEn : 1;
55  uint32_t numRecords : 32;
56  uint32_t dstSelX : 3;
57  uint32_t dstSelY : 3;
58  uint32_t dstSelZ : 3;
59  uint32_t dstSelW : 3;
60  uint32_t numFmt : 3;
61  uint32_t dataFmt : 4;
62  uint32_t elemSize : 2;
63  uint32_t idxStride : 2;
64  uint32_t addTidEn : 1;
65  uint32_t atc : 1;
66  uint32_t hashEn : 1;
67  uint32_t heap : 1;
68  uint32_t mType : 3;
69  uint32_t type : 2;
70  };
71 
72  // --- purely virtual instruction classes ---
73 
75  {
76  public:
77  Inst_SOP2(InFmt_SOP2*, const std::string &opcode);
78 
79  int instSize() const override;
80  void generateDisassembly() override;
81 
82  bool isScalarRegister(int opIdx) override;
83  bool isVectorRegister(int opIdx) override;
84  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
85 
86  protected:
87  // first instruction DWORD
89  // possible second DWORD
91  uint32_t varSize;
92 
93  private:
94  bool hasSecondDword(InFmt_SOP2 *);
95  }; // Inst_SOP2
96 
98  {
99  public:
100  Inst_SOPK(InFmt_SOPK*, const std::string &opcode);
101  ~Inst_SOPK();
102 
103  int instSize() const override;
104  void generateDisassembly() override;
105 
106  bool isScalarRegister(int opIdx) override;
107  bool isVectorRegister(int opIdx) override;
108  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
109 
110  protected:
111  // first instruction DWORD
113  // possible second DWORD
115  uint32_t varSize;
116 
117  private:
118  bool hasSecondDword(InFmt_SOPK *);
119  }; // Inst_SOPK
120 
122  {
123  public:
124  Inst_SOP1(InFmt_SOP1*, const std::string &opcode);
125  ~Inst_SOP1();
126 
127  int instSize() const override;
128  void generateDisassembly() override;
129 
130  bool isScalarRegister(int opIdx) override;
131  bool isVectorRegister(int opIdx) override;
132  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
133 
134  protected:
135  // first instruction DWORD
137  // possible second DWORD
139  uint32_t varSize;
140 
141  private:
142  bool hasSecondDword(InFmt_SOP1 *);
143  }; // Inst_SOP1
144 
146  {
147  public:
148  Inst_SOPC(InFmt_SOPC*, const std::string &opcode);
149  ~Inst_SOPC();
150 
151  int instSize() const override;
152  void generateDisassembly() override;
153 
154  bool isScalarRegister(int opIdx) override;
155  bool isVectorRegister(int opIdx) override;
156  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
157 
158  protected:
159  // first instruction DWORD
161  // possible second DWORD
163  uint32_t varSize;
164 
165  private:
166  bool hasSecondDword(InFmt_SOPC *);
167  }; // Inst_SOPC
168 
170  {
171  public:
172  Inst_SOPP(InFmt_SOPP*, const std::string &opcode);
173  ~Inst_SOPP();
174 
175  int instSize() const override;
176  void generateDisassembly() override;
177 
178  bool isScalarRegister(int opIdx) override;
179  bool isVectorRegister(int opIdx) override;
180  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
181 
182  protected:
183  // first instruction DWORD
185  }; // Inst_SOPP
186 
188  {
189  public:
190  Inst_SMEM(InFmt_SMEM*, const std::string &opcode);
191  ~Inst_SMEM();
192 
193  int instSize() const override;
194  void generateDisassembly() override;
195 
196  bool isScalarRegister(int opIdx) override;
197  bool isVectorRegister(int opIdx) override;
198  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
199 
200  protected:
204  template<int N>
205  void
207  {
208  initMemReqScalarHelper<ScalarRegU32, N>(gpuDynInst,
210  }
211 
215  template<int N>
216  void
218  {
219  initMemReqScalarHelper<ScalarRegU32, N>(gpuDynInst,
221  }
222 
226  void
229  {
230  Addr vaddr = ((addr.rawData() + offset) & ~0x3);
231  gpu_dyn_inst->scalarAddr = vaddr;
232  }
233 
239  void
240  calcAddr(GPUDynInstPtr gpu_dyn_inst,
242  {
243  BufferRsrcDescriptor rsrc_desc;
244  ScalarRegU32 clamped_offset(offset);
245  std::memcpy((void*)&rsrc_desc, s_rsrc_desc.rawDataPtr(),
246  sizeof(BufferRsrcDescriptor));
247 
253  if (!rsrc_desc.stride && offset >= rsrc_desc.numRecords) {
254  clamped_offset = rsrc_desc.numRecords;
255  } else if (rsrc_desc.stride && offset
256  > (rsrc_desc.stride * rsrc_desc.numRecords)) {
257  clamped_offset = (rsrc_desc.stride * rsrc_desc.numRecords);
258  }
259 
260  Addr vaddr = ((rsrc_desc.baseAddr + clamped_offset) & ~0x3);
261  gpu_dyn_inst->scalarAddr = vaddr;
262  }
263 
264  // first instruction DWORD
266  // second instruction DWORD
268  }; // Inst_SMEM
269 
271  {
272  public:
273  Inst_VOP2(InFmt_VOP2*, const std::string &opcode);
274  ~Inst_VOP2();
275 
276  int instSize() const override;
277  void generateDisassembly() override;
278 
279  bool isScalarRegister(int opIdx) override;
280  bool isVectorRegister(int opIdx) override;
281  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
282 
283  protected:
284  // first instruction DWORD
286  // possible second DWORD
288  uint32_t varSize;
289 
290  private:
291  bool hasSecondDword(InFmt_VOP2 *);
292  }; // Inst_VOP2
293 
295  {
296  public:
297  Inst_VOP1(InFmt_VOP1*, const std::string &opcode);
298  ~Inst_VOP1();
299 
300  int instSize() const override;
301  void generateDisassembly() override;
302 
303  bool isScalarRegister(int opIdx) override;
304  bool isVectorRegister(int opIdx) override;
305  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
306 
307  protected:
308  // first instruction DWORD
310  // possible second DWORD
312  uint32_t varSize;
313 
314  private:
315  bool hasSecondDword(InFmt_VOP1 *);
316  }; // Inst_VOP1
317 
319  {
320  public:
321  Inst_VOPC(InFmt_VOPC*, const std::string &opcode);
322  ~Inst_VOPC();
323 
324  int instSize() const override;
325  void generateDisassembly() override;
326 
327  bool isScalarRegister(int opIdx) override;
328  bool isVectorRegister(int opIdx) override;
329  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
330 
331  protected:
332  // first instruction DWORD
334  // possible second DWORD
336  uint32_t varSize;
337 
338  private:
339  bool hasSecondDword(InFmt_VOPC *);
340  }; // Inst_VOPC
341 
343  {
344  public:
345  Inst_VINTRP(InFmt_VINTRP*, const std::string &opcode);
346  ~Inst_VINTRP();
347 
348  int instSize() const override;
349 
350  protected:
351  // first instruction DWORD
353  }; // Inst_VINTRP
354 
356  {
357  public:
358  Inst_VOP3(InFmt_VOP3*, const std::string &opcode, bool sgpr_dst);
359  ~Inst_VOP3();
360 
361  int instSize() const override;
362  void generateDisassembly() override;
363 
364  bool isScalarRegister(int opIdx) override;
365  bool isVectorRegister(int opIdx) override;
366  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
367 
368  protected:
369  // first instruction DWORD
371  // second instruction DWORD
373 
374  private:
375  bool hasSecondDword(InFmt_VOP3 *);
386  const bool sgprDst;
387  }; // Inst_VOP3
388 
390  {
391  public:
392  Inst_VOP3_SDST_ENC(InFmt_VOP3_SDST_ENC*, const std::string &opcode);
394 
395  int instSize() const override;
396  void generateDisassembly() override;
397 
398  bool isScalarRegister(int opIdx) override;
399  bool isVectorRegister(int opIdx) override;
400  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
401 
402  protected:
403  // first instruction DWORD
405  // second instruction DWORD
407 
408  private:
410  }; // Inst_VOP3_SDST_ENC
411 
412  class Inst_DS : public GCN3GPUStaticInst
413  {
414  public:
415  Inst_DS(InFmt_DS*, const std::string &opcode);
416  ~Inst_DS();
417 
418  int instSize() const override;
419  void generateDisassembly() override;
420 
421  bool isScalarRegister(int opIdx) override;
422  bool isVectorRegister(int opIdx) override;
423  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
424 
425  protected:
426  template<typename T>
427  void
429  {
430  Wavefront *wf = gpuDynInst->wavefront();
431 
432  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
433  if (gpuDynInst->exec_mask[lane]) {
434  Addr vaddr = gpuDynInst->addr[lane] + offset;
435 
436  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane]
437  = wf->ldsChunk->read<T>(vaddr);
438  }
439  }
440  }
441 
442  template<typename T>
443  void
444  initDualMemRead(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
445  {
446  Wavefront *wf = gpuDynInst->wavefront();
447 
448  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
449  if (gpuDynInst->exec_mask[lane]) {
450  Addr vaddr0 = gpuDynInst->addr[lane] + offset0;
451  Addr vaddr1 = gpuDynInst->addr[lane] + offset1;
452 
453  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane * 2]
454  = wf->ldsChunk->read<T>(vaddr0);
455  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane * 2 + 1]
456  = wf->ldsChunk->read<T>(vaddr1);
457  }
458  }
459  }
460 
461  template<typename T>
462  void
464  {
465  Wavefront *wf = gpuDynInst->wavefront();
466 
467  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
468  if (gpuDynInst->exec_mask[lane]) {
469  Addr vaddr = gpuDynInst->addr[lane] + offset;
470  wf->ldsChunk->write<T>(vaddr,
471  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane]);
472  }
473  }
474  }
475 
476  template<typename T>
477  void
478  initDualMemWrite(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
479  {
480  Wavefront *wf = gpuDynInst->wavefront();
481 
482  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
483  if (gpuDynInst->exec_mask[lane]) {
484  Addr vaddr0 = gpuDynInst->addr[lane] + offset0;
485  Addr vaddr1 = gpuDynInst->addr[lane] + offset1;
486  wf->ldsChunk->write<T>(vaddr0, (reinterpret_cast<T*>(
487  gpuDynInst->d_data))[lane * 2]);
488  wf->ldsChunk->write<T>(vaddr1, (reinterpret_cast<T*>(
489  gpuDynInst->d_data))[lane * 2 + 1]);
490  }
491  }
492  }
493 
494  void
496  {
497  Wavefront *wf = gpuDynInst->wavefront();
498 
499  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
500  if (wf->execMask(lane)) {
501  gpuDynInst->addr.at(lane) = (Addr)addr[lane];
502  }
503  }
504  }
505 
506  // first instruction DWORD
508  // second instruction DWORD
510  }; // Inst_DS
511 
513  {
514  public:
515  Inst_MUBUF(InFmt_MUBUF*, const std::string &opcode);
516  ~Inst_MUBUF();
517 
518  int instSize() const override;
519  void generateDisassembly() override;
520 
521  bool isScalarRegister(int opIdx) override;
522  bool isVectorRegister(int opIdx) override;
523  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
524 
525  protected:
526  template<typename T>
527  void
529  {
530  // temporarily modify exec_mask to supress memory accesses to oob
531  // regions. Only issue memory requests for lanes that have their
532  // exec_mask set and are not out of bounds.
533  VectorMask old_exec_mask = gpuDynInst->exec_mask;
534  gpuDynInst->exec_mask &= ~oobMask;
535  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::ReadReq);
536  gpuDynInst->exec_mask = old_exec_mask;
537  }
538 
539 
540  template<int N>
541  void
543  {
544  // temporarily modify exec_mask to supress memory accesses to oob
545  // regions. Only issue memory requests for lanes that have their
546  // exec_mask set and are not out of bounds.
547  VectorMask old_exec_mask = gpuDynInst->exec_mask;
548  gpuDynInst->exec_mask &= ~oobMask;
549  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::ReadReq);
550  gpuDynInst->exec_mask = old_exec_mask;
551  }
552 
553  template<typename T>
554  void
556  {
557  // temporarily modify exec_mask to supress memory accesses to oob
558  // regions. Only issue memory requests for lanes that have their
559  // exec_mask set and are not out of bounds.
560  VectorMask old_exec_mask = gpuDynInst->exec_mask;
561  gpuDynInst->exec_mask &= ~oobMask;
562  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::WriteReq);
563  gpuDynInst->exec_mask = old_exec_mask;
564  }
565 
566  template<int N>
567  void
569  {
570  // temporarily modify exec_mask to supress memory accesses to oob
571  // regions. Only issue memory requests for lanes that have their
572  // exec_mask set and are not out of bounds.
573  VectorMask old_exec_mask = gpuDynInst->exec_mask;
574  gpuDynInst->exec_mask &= ~oobMask;
575  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::WriteReq);
576  gpuDynInst->exec_mask = old_exec_mask;
577  }
578 
579  void
581  {
582  // create request and set flags
583  gpuDynInst->resetEntireStatusVector();
584  gpuDynInst->setStatusVector(0, 1);
585  RequestPtr req = std::make_shared<Request>(0, 0, 0,
586  gpuDynInst->computeUnit()->
587  requestorId(), 0,
588  gpuDynInst->wfDynId);
589  gpuDynInst->setRequestFlags(req);
590  gpuDynInst->computeUnit()->
591  injectGlobalMemFence(gpuDynInst, false, req);
592  }
593 
614  template<typename VOFF, typename VIDX, typename SRSRC, typename SOFF>
615  void
616  calcAddr(GPUDynInstPtr gpuDynInst, VOFF v_off, VIDX v_idx,
617  SRSRC s_rsrc_desc, SOFF s_offset, int inst_offset)
618  {
619  Addr vaddr = 0;
620  Addr base_addr = 0;
621  Addr stride = 0;
622  Addr buf_idx = 0;
623  Addr buf_off = 0;
624  BufferRsrcDescriptor rsrc_desc;
625 
626  std::memcpy((void*)&rsrc_desc, s_rsrc_desc.rawDataPtr(),
627  sizeof(BufferRsrcDescriptor));
628 
629  base_addr = rsrc_desc.baseAddr;
630 
631  stride = rsrc_desc.addTidEn ? ((rsrc_desc.dataFmt << 14)
632  + rsrc_desc.stride) : rsrc_desc.stride;
633 
634  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
635  if (gpuDynInst->exec_mask[lane]) {
636  vaddr = base_addr + s_offset.rawData();
642  buf_idx = v_idx[lane] + (rsrc_desc.addTidEn ? lane : 0);
643 
644  buf_off = v_off[lane] + inst_offset;
645 
646 
654  if (stride == 0 || !rsrc_desc.swizzleEn) {
655  if (buf_off + stride * buf_idx >=
656  rsrc_desc.numRecords - s_offset.rawData()) {
657  DPRINTF(GCN3, "mubuf out-of-bounds condition 1: "
658  "lane = %d, buffer_offset = %llx, "
659  "const_stride = %llx, "
660  "const_num_records = %llx\n",
661  lane, buf_off + stride * buf_idx,
662  stride, rsrc_desc.numRecords);
663  oobMask.set(lane);
664  continue;
665  }
666  }
667 
668  if (stride != 0 && rsrc_desc.swizzleEn) {
669  if (buf_idx >= rsrc_desc.numRecords ||
670  buf_off >= stride) {
671  DPRINTF(GCN3, "mubuf out-of-bounds condition 2: "
672  "lane = %d, offset = %llx, "
673  "index = %llx, "
674  "const_num_records = %llx\n",
675  lane, buf_off, buf_idx,
676  rsrc_desc.numRecords);
677  oobMask.set(lane);
678  continue;
679  }
680  }
681 
682  if (rsrc_desc.swizzleEn) {
683  Addr idx_stride = 8 << rsrc_desc.idxStride;
684  Addr elem_size = 2 << rsrc_desc.elemSize;
685  Addr idx_msb = buf_idx / idx_stride;
686  Addr idx_lsb = buf_idx % idx_stride;
687  Addr off_msb = buf_off / elem_size;
688  Addr off_lsb = buf_off % elem_size;
689  DPRINTF(GCN3, "mubuf swizzled lane %d: "
690  "idx_stride = %llx, elem_size = %llx, "
691  "idx_msb = %llx, idx_lsb = %llx, "
692  "off_msb = %llx, off_lsb = %llx\n",
693  lane, idx_stride, elem_size, idx_msb, idx_lsb,
694  off_msb, off_lsb);
695 
696  vaddr += ((idx_msb * stride + off_msb * elem_size)
697  * idx_stride + idx_lsb * elem_size + off_lsb);
698  } else {
699  vaddr += buf_off + stride * buf_idx;
700  }
701 
702  DPRINTF(GCN3, "Calculating mubuf address for lane %d: "
703  "vaddr = %llx, base_addr = %llx, "
704  "stride = %llx, buf_idx = %llx, buf_off = %llx\n",
705  lane, vaddr, base_addr, stride,
706  buf_idx, buf_off);
707  gpuDynInst->addr.at(lane) = vaddr;
708  }
709  }
710  }
711 
712  // first instruction DWORD
714  // second instruction DWORD
716  // Mask of lanes with out-of-bounds accesses. Needs to be tracked
717  // seperately from the exec_mask so that we remember to write zero
718  // to the registers associated with out of bounds lanes.
720  }; // Inst_MUBUF
721 
723  {
724  public:
725  Inst_MTBUF(InFmt_MTBUF*, const std::string &opcode);
726  ~Inst_MTBUF();
727 
728  int instSize() const override;
729 
730  protected:
731  // first instruction DWORD
733  // second instruction DWORD
735 
736  private:
737  bool hasSecondDword(InFmt_MTBUF *);
738  }; // Inst_MTBUF
739 
741  {
742  public:
743  Inst_MIMG(InFmt_MIMG*, const std::string &opcode);
744  ~Inst_MIMG();
745 
746  int instSize() const override;
747 
748  protected:
749  // first instruction DWORD
751  // second instruction DWORD
753  }; // Inst_MIMG
754 
756  {
757  public:
758  Inst_EXP(InFmt_EXP*, const std::string &opcode);
759  ~Inst_EXP();
760 
761  int instSize() const override;
762 
763  protected:
764  // first instruction DWORD
766  // second instruction DWORD
768  }; // Inst_EXP
769 
771  {
772  public:
773  Inst_FLAT(InFmt_FLAT*, const std::string &opcode);
774  ~Inst_FLAT();
775 
776  int instSize() const override;
777  void generateDisassembly() override;
778 
779  bool isScalarRegister(int opIdx) override;
780  bool isVectorRegister(int opIdx) override;
781  int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
782 
783  protected:
784  template<typename T>
785  void
787  {
788  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::ReadReq);
789  }
790 
791  template<int N>
792  void
794  {
795  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::ReadReq);
796  }
797 
798  template<typename T>
799  void
801  {
802  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::WriteReq);
803  }
804 
805  template<int N>
806  void
808  {
809  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::WriteReq);
810  }
811 
812  template<typename T>
813  void
815  {
816  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::SwapReq, true);
817  }
818 
819  void
821  {
822  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
823  if (gpuDynInst->exec_mask[lane]) {
824  gpuDynInst->addr.at(lane) = addr[lane];
825  }
826  }
827  gpuDynInst->resolveFlatSegment(gpuDynInst->exec_mask);
828  }
829 
830  // first instruction DWORD
832  // second instruction DWORD
834  }; // Inst_FLAT
835 } // namespace Gcn3ISA
836 
837 #endif // __ARCH_GCN3_INSTS_OP_ENCODINGS_HH__
Gcn3ISA::Inst_SMEM::Inst_SMEM
Inst_SMEM(InFmt_SMEM *, const std::string &opcode)
Definition: op_encodings.cc:600
Gcn3ISA::Inst_SMEM::isScalarRegister
bool isScalarRegister(int opIdx) override
Definition: op_encodings.cc:662
Gcn3ISA::Inst_VOP3_SDST_ENC::Inst_VOP3_SDST_ENC
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Definition: op_encodings.cc:1522
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Definition: op_encodings.hh:265
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Definition: op_encodings.hh:311
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For normal s_load_dword/s_store_dword instruction addresses.
Definition: op_encodings.hh:227
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Definition: op_encodings.cc:2117
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Definition: op_encodings.cc:964
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Definition: op_encodings.cc:1099
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Definition: op_encodings.cc:1195
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Definition: op_encodings.hh:312
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Definition: op_encodings.hh:58
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Definition: op_encodings.cc:1812
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Definition: op_encodings.cc:616
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Definition: lds_state.hh:89
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Definition: op_encodings.cc:2160
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Definition: gpu_decoder.hh:1373
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Definition: op_encodings.hh:333
Gcn3ISA::Inst_SMEM::getRegisterIndex
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Definition: gpu_decoder.hh:1520
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Definition: op_encodings.hh:800
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Definition: op_encodings.cc:1998
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Definition: gpu_decoder.hh:1468
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Definition: op_encodings.cc:1088
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Definition: op_encodings.hh:555
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Definition: op_encodings.hh:91
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Definition: op_encodings.cc:750
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Definition: op_encodings.cc:344
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bool isScalarRegister(int opIdx) override
Definition: op_encodings.cc:1588
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@ ReadReq
Definition: packet.hh:82
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Definition: op_encodings.cc:1533
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Definition: op_encodings.hh:287
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int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: op_encodings.cc:906
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Definition: gpu_decoder.hh:1425
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int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: op_encodings.cc:1049
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Definition: op_encodings.cc:492
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int instSize() const override
Definition: op_encodings.cc:1230
Gcn3ISA::BufferRsrcDescriptor::atc
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Definition: op_encodings.hh:65
RequestPtr
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Definition: request.hh:82
Gcn3ISA::Inst_VOP1::Inst_VOP1
Inst_VOP1(InFmt_VOP1 *, const std::string &opcode)
Definition: op_encodings.cc:944
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InFmt_FLAT_1 extData
Definition: op_encodings.hh:833
Gcn3ISA::BufferRsrcDescriptor::cacheSwizzle
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Definition: op_encodings.hh:53
Gcn3ISA::BufferRsrcDescriptor::dataFmt
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Definition: op_encodings.hh:61
Gcn3ISA::Inst_VOP3_SDST_ENC
Definition: op_encodings.hh:389
Gcn3ISA::Inst_MTBUF::hasSecondDword
bool hasSecondDword(InFmt_MTBUF *)
Gcn3ISA::Inst_MUBUF::Inst_MUBUF
Inst_MUBUF(InFmt_MUBUF *, const std::string &opcode)
Definition: op_encodings.cc:1911
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Gcn3ISA::Inst_SOP2::hasSecondDword
bool hasSecondDword(InFmt_SOP2 *)
Definition: op_encodings.cc:68
Gcn3ISA::Inst_DS::getRegisterIndex
int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: op_encodings.cc:1876
Gcn3ISA::Inst_VOP2::hasSecondDword
bool hasSecondDword(InFmt_VOP2 *)
Definition: op_encodings.cc:756
Gcn3ISA::Inst_MTBUF::instSize
int instSize() const override
Definition: op_encodings.cc:2043
Gcn3ISA::Inst_SOPK::instSize
int instSize() const override
Definition: op_encodings.cc:178
Gcn3ISA::Inst_MUBUF::oobMask
VectorMask oobMask
Definition: op_encodings.hh:719
Gcn3ISA::Inst_SOPK::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:201
Gcn3ISA::Inst_SOPP::getRegisterIndex
int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: op_encodings.cc:588
Gcn3ISA::Inst_VOP2::isScalarRegister
bool isScalarRegister(int opIdx) override
Definition: op_encodings.cc:820
Gcn3ISA::Inst_SOPK::varSize
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Definition: op_encodings.hh:115
Gcn3ISA::Inst_VOP3_SDST_ENC::instData
InFmt_VOP3_SDST_ENC instData
Definition: op_encodings.hh:404
Gcn3ISA::Inst_SMEM::initMemRead
void initMemRead(GPUDynInstPtr gpuDynInst)
initiate a memory read access for N dwords
Definition: op_encodings.hh:206
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Definition: op_encodings.cc:1202
Gcn3ISA::BufferRsrcDescriptor::numRecords
uint32_t numRecords
Definition: op_encodings.hh:55
Gcn3ISA::Inst_SOPP::isScalarRegister
bool isScalarRegister(int opIdx) override
Definition: op_encodings.cc:566
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const std::string & opcode() const
Definition: gpu_static_inst.hh:257
Gcn3ISA::Inst_MUBUF::calcAddr
void calcAddr(GPUDynInstPtr gpuDynInst, VOFF v_off, VIDX v_idx, SRSRC s_rsrc_desc, SOFF s_offset, int inst_offset)
MUBUF insructions calculate their addresses as follows:
Definition: op_encodings.hh:616
Gcn3ISA::InFmt_MTBUF_1
Definition: gpu_decoder.hh:1445
Gcn3ISA::InFmt_FLAT
Definition: gpu_decoder.hh:1390
Gcn3ISA::Inst_DS::initMemWrite
void initMemWrite(GPUDynInstPtr gpuDynInst, Addr offset)
Definition: op_encodings.hh:463
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Definition: gpu_decoder.hh:1542
Gcn3ISA::BufferRsrcDescriptor::dstSelW
uint32_t dstSelW
Definition: op_encodings.hh:59
MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:85
Gcn3ISA::InFmt_DS
Definition: gpu_decoder.hh:1357
Gcn3ISA::Inst_DS::initMemRead
void initMemRead(GPUDynInstPtr gpuDynInst, Addr offset)
Definition: op_encodings.hh:428
Gcn3ISA::Inst_SOP1::hasSecondDword
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Definition: op_encodings.cc:296
Gcn3ISA::Inst_SOP1::varSize
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Definition: op_encodings.hh:139
Gcn3ISA::Inst_FLAT::initMemRead
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Definition: op_encodings.hh:786
Wavefront::ldsChunk
LdsChunk * ldsChunk
Definition: wavefront.hh:215
Gcn3ISA::Inst_MIMG::extData
InFmt_MIMG_1 extData
Definition: op_encodings.hh:752
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Definition: op_encodings.hh:355
Gcn3ISA::Inst_SOPC::isVectorRegister
bool isVectorRegister(int opIdx) override
Definition: op_encodings.cc:462
Gcn3ISA::InFmt_SOP2
Definition: gpu_decoder.hh:1498
Gcn3ISA::Inst_VOP3_SDST_ENC::isVectorRegister
bool isVectorRegister(int opIdx) override
Definition: op_encodings.cc:1662
Gcn3ISA::Inst_SOPC::extData
InstFormat extData
Definition: op_encodings.hh:162
Gcn3ISA::Inst_VOP1::isVectorRegister
bool isVectorRegister(int opIdx) override
Definition: op_encodings.cc:1031
Gcn3ISA::Inst_VINTRP::instSize
int instSize() const override
Definition: op_encodings.cc:1207
Gcn3ISA::Inst_FLAT::instData
InFmt_FLAT instData
Definition: op_encodings.hh:831
Gcn3ISA::BufferRsrcDescriptor::numFmt
uint32_t numFmt
Definition: op_encodings.hh:60
Gcn3ISA::Inst_VOP2::instData
InFmt_VOP2 instData
Definition: op_encodings.hh:285
MemCmd::SwapReq
@ SwapReq
Definition: packet.hh:111
Gcn3ISA::Inst_SOP1::instData
InFmt_SOP1 instData
Definition: op_encodings.hh:136
Gcn3ISA::Inst_VOP2::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:781
Gcn3ISA::Inst_FLAT::instSize
int instSize() const override
Definition: op_encodings.cc:2122
Gcn3ISA::BufferRsrcDescriptor::stride
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Definition: op_encodings.hh:52
Gcn3ISA::Inst_EXP::~Inst_EXP
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Definition: op_encodings.cc:2088
Gcn3ISA::Inst_SOP2
Definition: op_encodings.hh:74
Gcn3ISA::Inst_SOP2::getRegisterIndex
int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: op_encodings.cc:133
Gcn3ISA::Inst_VOP2::isVectorRegister
bool isVectorRegister(int opIdx) override
Definition: op_encodings.cc:863
Gcn3ISA::Inst_VOP3_SDST_ENC::getRegisterIndex
int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: op_encodings.cc:1736
Gcn3ISA::Inst_SOPC::Inst_SOPC
Inst_SOPC(InFmt_SOPC *, const std::string &opcode)
Definition: op_encodings.cc:380
Gcn3ISA::Inst_SOPK::getRegisterIndex
int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: op_encodings.cc:249
Gcn3ISA::InFmt_VOPC
Definition: gpu_decoder.hh:1575
Gcn3ISA::InFmt_SMEM_1
Definition: gpu_decoder.hh:1487
Gcn3ISA::Inst_SOP1::extData
InstFormat extData
Definition: op_encodings.hh:138
Gcn3ISA::Inst_MUBUF::instData
InFmt_MUBUF instData
Definition: op_encodings.hh:713
Gcn3ISA
classes that represnt vector/scalar operands in GCN3 ISA.
Definition: decoder.cc:44
Gcn3ISA::Inst_VOP3::getRegisterIndex
int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: op_encodings.cc:1442
Gcn3ISA::InFmt_FLAT_1
Definition: gpu_decoder.hh:1399
Gcn3ISA::VecOperand
Definition: operand.hh:102
Gcn3ISA::Inst_DS::initDualMemWrite
void initDualMemWrite(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
Definition: op_encodings.hh:478
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
Gcn3ISA::InFmt_MTBUF
Definition: gpu_decoder.hh:1434
Gcn3ISA::BufferRsrcDescriptor::mType
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Definition: op_encodings.hh:68
Gcn3ISA::Inst_SOP2::Inst_SOP2
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Definition: op_encodings.cc:44
Gcn3ISA::Inst_VOP3_SDST_ENC::hasSecondDword
bool hasSecondDword(InFmt_VOP3_SDST_ENC *)
Gcn3ISA::Inst_VOP1::instSize
int instSize() const override
Definition: op_encodings.cc:969
Gcn3ISA::InFmt_SOPC
Definition: gpu_decoder.hh:1506
Gcn3ISA::Inst_SOPC
Definition: op_encodings.hh:145
Gcn3ISA::Inst_SMEM::extData
InFmt_SMEM_1 extData
Definition: op_encodings.hh:267
Gcn3ISA::Inst_SOPC::instData
InFmt_SOPC instData
Definition: op_encodings.hh:160
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Definition: pra_constants.hh:275
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Definition: op_encodings.hh:342
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Definition: gpu_decoder.hh:1455
Gcn3ISA::Inst_VOP3::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1236
Gcn3ISA::Inst_SMEM::instSize
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Definition: op_encodings.cc:621
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Definition: op_encodings.cc:2038
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InFmt_EXP_1 extData
Definition: op_encodings.hh:767
Gcn3ISA::BufferRsrcDescriptor::dstSelX
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Definition: op_encodings.hh:56
Gcn3ISA::BufferRsrcDescriptor::hashEn
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Definition: op_encodings.hh:66
Gcn3ISA::Inst_VOPC::getRegisterIndex
int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: op_encodings.cc:1172
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Definition: gpu_decoder.hh:1513
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Definition: op_encodings.cc:285
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Definition: gpu_decoder.hh:1526
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bool isScalarRegister(int opIdx) override
Definition: op_encodings.cc:1130
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InFmt_VOP3_1 extData
Definition: op_encodings.hh:372
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Definition: op_encodings.cc:268
Gcn3ISA::Inst_SOPC::instSize
int instSize() const override
Definition: op_encodings.cc:402
Gcn3ISA::Inst_SOPP::instData
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Definition: op_encodings.hh:184
Gcn3ISA::Inst_SOPC::hasSecondDword
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Definition: op_encodings.cc:408
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Definition: op_encodings.cc:2100
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Definition: op_encodings.hh:187
Gcn3ISA::Inst_SOPK::isVectorRegister
bool isVectorRegister(int opIdx) override
Definition: op_encodings.cc:239
Gcn3ISA::Inst_SOP1::isScalarRegister
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Definition: op_encodings.cc:322
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Definition: op_encodings.hh:169
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Definition: op_encodings.cc:2050
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bool isScalarRegister(int opIdx) override
Definition: op_encodings.cc:222
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Definition: gpu_decoder.hh:1535
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uint32_t varSize
Definition: op_encodings.hh:336
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Definition: op_encodings.hh:51
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Definition: op_encodings.cc:1927
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Definition: op_encodings.cc:156
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bool isScalarRegister(int opIdx) override
Definition: op_encodings.cc:104
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Definition: gpu_decoder.hh:1550
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Definition: gpu_decoder.hh:1366
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Definition: op_encodings.hh:270
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Definition: gpu_decoder.hh:1491
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Definition: gpu_decoder.hh:1559
Addr
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Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
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Definition: op_encodings.cc:1856
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InstFormat extData
Definition: op_encodings.hh:335
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Definition: op_encodings.cc:1013
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Definition: op_encodings.hh:121
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Definition: op_encodings.cc:305
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Definition: op_encodings.cc:2093
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Definition: op_encodings.hh:318
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Definition: op_encodings.cc:1538
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Definition: op_encodings.hh:69
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Definition: op_encodings.cc:80
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Definition: op_encodings.hh:163
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Definition: op_encodings.hh:62
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Definition: op_encodings.cc:2078
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Definition: op_encodings.cc:420
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Definition: op_encodings.cc:975
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Definition: op_encodings.hh:444
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Definition: op_encodings.hh:88
Gcn3ISA::Inst_MUBUF::isVectorRegister
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Definition: op_encodings.cc:1977
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Definition: op_encodings.cc:1800
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Definition: gpu_decoder.hh:1477
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Definition: op_encodings.hh:406
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Definition: op_encodings.cc:173
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InstFormat extData
Definition: op_encodings.hh:114
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Definition: op_encodings.hh:97
Gcn3ISA::Inst_VOPC::instSize
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Definition: op_encodings.cc:1093
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Definition: op_encodings.hh:770
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InstFormat extData
Definition: op_encodings.hh:90
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Gcn3ISA::Inst_VOP3_SDST_ENC::generateDisassembly
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Definition: op_encodings.cc:1544
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Definition: lds_state.hh:70
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Definition: wavefront.hh:57
Gcn3ISA::Inst_SMEM::initMemWrite
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initiate a memory write access for N dwords
Definition: op_encodings.hh:217
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Definition: operand.hh:98
Gcn3ISA::Inst_DS::extData
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Definition: op_encodings.hh:509
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Definition: op_encodings.hh:309
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Definition: wavefront.cc:1398
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Definition: op_encodings.hh:734
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Definition: op_encodings.cc:184
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Definition: inet.hh:423
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Definition: op_encodings.cc:506
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Definition: op_encodings.cc:725
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Definition: misc.hh:48
Gcn3ISA::Inst_VOP3::sgprDst
const bool sgprDst
the v_cmp and readlane instructions in the VOP3 encoding are unique because they are the only instruc...
Definition: op_encodings.hh:386
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Definition: gpu_decoder.hh:1383
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Bitfield< 21, 20 > stride
Definition: miscregs_types.hh:441
Gcn3ISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: registers.hh:154
Gcn3ISA::Inst_MUBUF::injectGlobalMemFence
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Definition: op_encodings.hh:580
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Definition: op_encodings.hh:294
Gcn3ISA::Inst_EXP
Definition: op_encodings.hh:755
Gcn3ISA::Inst_VOPC::isVectorRegister
bool isVectorRegister(int opIdx) override
Definition: op_encodings.cc:1151
Gcn3ISA::Inst_SOP2::instSize
int instSize() const override
Definition: op_encodings.cc:62
Gcn3ISA::Inst_VOP1::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:994
gpu_decoder.hh
Gcn3ISA::InstFormat
Definition: gpu_decoder.hh:1612
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Definition: op_encodings.hh:765
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Definition: op_encodings.hh:49
Gcn3ISA::Inst_VOP3::Inst_VOP3
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Definition: op_encodings.cc:1214
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void calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU32 &addr)
Definition: op_encodings.hh:495
Gcn3ISA::Inst_MUBUF::instSize
int instSize() const override
Definition: op_encodings.cc:1932
Gcn3ISA::Inst_FLAT::getRegisterIndex
int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: op_encodings.cc:2175
Gcn3ISA::Inst_VOPC::Inst_VOPC
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Definition: op_encodings.cc:1068
Gcn3ISA::Inst_MUBUF::extData
InFmt_MUBUF_1 extData
Definition: op_encodings.hh:715
VectorMask
std::bitset< std::numeric_limits< unsigned long long >::digits > VectorMask
Definition: misc.hh:44
Gcn3ISA::Inst_FLAT::calcAddr
void calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &addr)
Definition: op_encodings.hh:820
Gcn3ISA::Inst_SOPK::instData
InFmt_SOPK instData
Definition: op_encodings.hh:112
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bool isVectorRegister(int opIdx) override
Definition: op_encodings.cc:577
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Definition: gpu_decoder.hh:1411
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bool isScalarRegister(int opIdx) override
Definition: op_encodings.cc:1294
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Definition: gpu_decoder.hh:1567
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Definition: op_encodings.hh:528
Gcn3ISA::Inst_SOP1::getRegisterIndex
int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: op_encodings.cc:354
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void generateDisassembly() override
Definition: op_encodings.cc:2128
Gcn3ISA::Inst_FLAT::initAtomicAccess
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Definition: op_encodings.hh:814
Gcn3ISA::Inst_SOPC::getRegisterIndex
int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: op_encodings.cc:472
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Definition: op_encodings.hh:732
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void generateDisassembly() override
Definition: op_encodings.cc:627
Gcn3ISA::Inst_MIMG::instSize
int instSize() const override
Definition: op_encodings.cc:2071
Gcn3ISA::Inst_SOPC::isScalarRegister
bool isScalarRegister(int opIdx) override
Definition: op_encodings.cc:443
Gcn3ISA::Inst_SOPP::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:512
Gcn3ISA::BufferRsrcDescriptor::swizzleEn
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Definition: op_encodings.hh:54
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Definition: op_encodings.hh:722
Gcn3ISA::BufferRsrcDescriptor::idxStride
uint32_t idxStride
Definition: op_encodings.hh:63
Gcn3ISA::Inst_MIMG::instData
InFmt_MIMG instData
Definition: op_encodings.hh:750
Gcn3ISA::Inst_DS::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1823
Gcn3ISA::Inst_SOPC::~Inst_SOPC
~Inst_SOPC()
Definition: op_encodings.cc:397
Gcn3ISA::Inst_SMEM::isVectorRegister
bool isVectorRegister(int opIdx) override
Definition: op_encodings.cc:686
Gcn3ISA::Inst_MUBUF::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1938
Gcn3ISA::Inst_VOP3::instData
InFmt_VOP3 instData
Definition: op_encodings.hh:370
Gcn3ISA::BufferRsrcDescriptor::heap
uint32_t heap
Definition: op_encodings.hh:67
Gcn3ISA::Inst_MIMG
Definition: op_encodings.hh:740
Gcn3ISA::Inst_SMEM::calcAddr
void calcAddr(GPUDynInstPtr gpu_dyn_inst, ConstScalarOperandU128 &s_rsrc_desc, ScalarRegU32 offset)
For s_buffer_load_dword/s_buffer_store_dword instruction addresses.
Definition: op_encodings.hh:240
Gcn3ISA::Inst_MUBUF
Definition: op_encodings.hh:512
Gcn3ISA::Inst_MUBUF::isScalarRegister
bool isScalarRegister(int opIdx) override
Definition: op_encodings.cc:1956
Gcn3ISA::Inst_DS
Definition: op_encodings.hh:412
Gcn3ISA::Inst_VOPC::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1118
Gcn3ISA::Inst_VINTRP::instData
InFmt_VINTRP instData
Definition: op_encodings.hh:352
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Bitfield< 23, 0 > offset
Definition: types.hh:153
Gcn3ISA::Inst_DS::isVectorRegister
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Definition: op_encodings.cc:1866
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Definition: gpu_static_inst.hh:48

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