gem5  v21.0.0.0
•All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
isa.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010-2021 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #include "arch/arm/isa.hh"
39 
40 #include "arch/arm/faults.hh"
41 #include "arch/arm/htm.hh"
42 #include "arch/arm/interrupts.hh"
43 #include "arch/arm/mmu.hh"
44 #include "arch/arm/pmu.hh"
45 #include "arch/arm/self_debug.hh"
46 #include "arch/arm/system.hh"
47 #include "arch/arm/tlbi_op.hh"
48 #include "cpu/base.hh"
49 #include "cpu/checker/cpu.hh"
50 #include "debug/Arm.hh"
51 #include "debug/MiscRegs.hh"
52 #include "dev/arm/generic_timer.hh"
53 #include "dev/arm/gic_v3.hh"
54 #include "dev/arm/gic_v3_cpu_interface.hh"
55 #include "params/ArmISA.hh"
56 #include "sim/faults.hh"
57 #include "sim/stat_control.hh"
58 #include "sim/system.hh"
59 
60 namespace ArmISA
61 {
62 
63 ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
64  _decoderFlavor(p.decoderFlavor), _vecRegRenameMode(Enums::Full),
65  pmu(p.pmu), impdefAsNop(p.impdef_nop),
66  afterStartup(false)
67 {
68  miscRegs[MISCREG_SCTLR_RST] = 0;
69 
70  // Hook up a dummy device if we haven't been configured with a
71  // real PMU. By using a dummy device, we don't need to check that
72  // the PMU exist every time we try to access a PMU register.
73  if (!pmu)
74  pmu = &dummyDevice;
75 
76  // Give all ISA devices a pointer to this ISA
77  pmu->setISA(this);
78 
79  system = dynamic_cast<ArmSystem *>(p.system);
80 
81  // Cache system-level properties
82  if (FullSystem && system) {
83  highestELIs64 = system->highestELIs64();
84  haveSecurity = system->haveSecurity();
85  haveLPAE = system->haveLPAE();
86  haveCrypto = system->haveCrypto();
87  haveVirtualization = system->haveVirtualization();
88  haveLargeAsid64 = system->haveLargeAsid64();
89  physAddrRange = system->physAddrRange();
90  haveSVE = system->haveSVE();
91  haveVHE = system->haveVHE();
92  havePAN = system->havePAN();
93  haveSecEL2 = system->haveSecEL2();
94  sveVL = system->sveVL();
95  haveLSE = system->haveLSE();
96  haveTME = system->haveTME();
97  } else {
98  highestELIs64 = true; // ArmSystem::highestELIs64 does the same
99  haveSecurity = haveLPAE = haveVirtualization = false;
100  haveCrypto = true;
101  haveLargeAsid64 = false;
102  physAddrRange = 32; // dummy value
103  haveSVE = true;
104  haveVHE = false;
105  havePAN = false;
106  haveSecEL2 = true;
107  sveVL = p.sve_vl_se;
108  haveLSE = true;
109  haveTME = true;
110  }
111 
112  // Initial rename mode depends on highestEL
113  const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
114  highestELIs64 ? Enums::Full : Enums::Elem;
115 
116  selfDebug = new SelfDebug();
117  initializeMiscRegMetadata();
118  preUnflattenMiscReg();
119 
120  clear();
121 }
122 
123 std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
124 
125 void
126 ISA::clear()
127 {
128  const Params &p(params());
129 
130  // Invalidate cached copies of miscregs in the TLBs
131  if (tc) {
132  getMMUPtr(tc)->invalidateMiscReg();
133  }
134 
135  SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
136  memset(miscRegs, 0, sizeof(miscRegs));
137 
138  initID32(p);
139 
140  // We always initialize AArch64 ID registers even
141  // if we are in AArch32. This is done since if we
142  // are in SE mode we don't know if our ArmProcess is
143  // AArch32 or AArch64
144  initID64(p);
145 
146  // Start with an event in the mailbox
147  miscRegs[MISCREG_SEV_MAILBOX] = 1;
148 
149  // Separate Instruction and Data TLBs
150  miscRegs[MISCREG_TLBTR] = 1;
151 
152  MVFR0 mvfr0 = 0;
153  mvfr0.advSimdRegisters = 2;
154  mvfr0.singlePrecision = 2;
155  mvfr0.doublePrecision = 2;
156  mvfr0.vfpExceptionTrapping = 0;
157  mvfr0.divide = 1;
158  mvfr0.squareRoot = 1;
159  mvfr0.shortVectors = 1;
160  mvfr0.roundingModes = 1;
161  miscRegs[MISCREG_MVFR0] = mvfr0;
162 
163  MVFR1 mvfr1 = 0;
164  mvfr1.flushToZero = 1;
165  mvfr1.defaultNaN = 1;
166  mvfr1.advSimdLoadStore = 1;
167  mvfr1.advSimdInteger = 1;
168  mvfr1.advSimdSinglePrecision = 1;
169  mvfr1.advSimdHalfPrecision = 1;
170  mvfr1.vfpHalfPrecision = 1;
171  miscRegs[MISCREG_MVFR1] = mvfr1;
172 
173  // Reset values of PRRR and NMRR are implementation dependent
174 
175  // @todo: PRRR and NMRR in secure state?
176  miscRegs[MISCREG_PRRR_NS] =
177  (1 << 19) | // 19
178  (0 << 18) | // 18
179  (0 << 17) | // 17
180  (1 << 16) | // 16
181  (2 << 14) | // 15:14
182  (0 << 12) | // 13:12
183  (2 << 10) | // 11:10
184  (2 << 8) | // 9:8
185  (2 << 6) | // 7:6
186  (2 << 4) | // 5:4
187  (1 << 2) | // 3:2
188  0; // 1:0
189 
190  miscRegs[MISCREG_NMRR_NS] =
191  (1 << 30) | // 31:30
192  (0 << 26) | // 27:26
193  (0 << 24) | // 25:24
194  (3 << 22) | // 23:22
195  (2 << 20) | // 21:20
196  (0 << 18) | // 19:18
197  (0 << 16) | // 17:16
198  (1 << 14) | // 15:14
199  (0 << 12) | // 13:12
200  (2 << 10) | // 11:10
201  (0 << 8) | // 9:8
202  (3 << 6) | // 7:6
203  (2 << 4) | // 5:4
204  (0 << 2) | // 3:2
205  0; // 1:0
206 
207  if (FullSystem && system->highestELIs64()) {
208  // Initialize AArch64 state
209  clear64(p);
210  return;
211  }
212 
213  // Initialize AArch32 state...
214  clear32(p, sctlr_rst);
215 }
216 
217 void
218 ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
219 {
220  CPSR cpsr = 0;
221  cpsr.mode = MODE_USER;
222 
223  if (FullSystem) {
224  miscRegs[MISCREG_MVBAR] = system->resetAddr();
225  }
226 
227  miscRegs[MISCREG_CPSR] = cpsr;
228  updateRegMap(cpsr);
229 
230  SCTLR sctlr = 0;
231  sctlr.te = (bool) sctlr_rst.te;
232  sctlr.nmfi = (bool) sctlr_rst.nmfi;
233  sctlr.v = (bool) sctlr_rst.v;
234  sctlr.u = 1;
235  sctlr.xp = 1;
236  sctlr.rao2 = 1;
237  sctlr.rao3 = 1;
238  sctlr.rao4 = 0xf; // SCTLR[6:3]
239  sctlr.uci = 1;
240  sctlr.dze = 1;
241  miscRegs[MISCREG_SCTLR_NS] = sctlr;
242  miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
243  miscRegs[MISCREG_HCPTR] = 0;
244 
245  miscRegs[MISCREG_CPACR] = 0;
246 
247  miscRegs[MISCREG_FPSID] = p.fpsid;
248 
249  if (haveLPAE) {
250  TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
251  ttbcr.eae = 0;
252  miscRegs[MISCREG_TTBCR_NS] = ttbcr;
253  // Enforce consistency with system-level settings
254  miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
255  }
256 
257  if (haveSecurity) {
258  miscRegs[MISCREG_SCTLR_S] = sctlr;
259  miscRegs[MISCREG_SCR] = 0;
260  miscRegs[MISCREG_VBAR_S] = 0;
261  } else {
262  // we're always non-secure
263  miscRegs[MISCREG_SCR] = 1;
264  }
265 
266  //XXX We need to initialize the rest of the state.
267 }
268 
269 void
270 ISA::clear64(const ArmISAParams &p)
271 {
272  CPSR cpsr = 0;
273  Addr rvbar = system->resetAddr();
274  switch (system->highestEL()) {
275  // Set initial EL to highest implemented EL using associated stack
276  // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
277  // value
278  case EL3:
279  cpsr.mode = MODE_EL3H;
280  miscRegs[MISCREG_RVBAR_EL3] = rvbar;
281  break;
282  case EL2:
283  cpsr.mode = MODE_EL2H;
284  miscRegs[MISCREG_RVBAR_EL2] = rvbar;
285  break;
286  case EL1:
287  cpsr.mode = MODE_EL1H;
288  miscRegs[MISCREG_RVBAR_EL1] = rvbar;
289  break;
290  default:
291  panic("Invalid highest implemented exception level");
292  break;
293  }
294 
295  // Initialize rest of CPSR
296  cpsr.daif = 0xf; // Mask all interrupts
297  cpsr.ss = 0;
298  cpsr.il = 0;
299  miscRegs[MISCREG_CPSR] = cpsr;
300  updateRegMap(cpsr);
301 
302  // Initialize other control registers
303  miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
304  if (haveSecurity) {
305  miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
306  miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
307  } else if (haveVirtualization) {
308  // also MISCREG_SCTLR_EL2 (by mapping)
309  miscRegs[MISCREG_HSCTLR] = 0x30c50830;
310  } else {
311  // also MISCREG_SCTLR_EL1 (by mapping)
312  miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
313  // Always non-secure
314  miscRegs[MISCREG_SCR_EL3] = 1;
315  }
316 }
317 
318 void
319 ISA::initID32(const ArmISAParams &p)
320 {
321  // Initialize configurable default values
322 
323  uint32_t midr;
324  if (p.midr != 0x0)
325  midr = p.midr;
326  else if (highestELIs64)
327  // Cortex-A57 TRM r0p0 MIDR
328  midr = 0x410fd070;
329  else
330  // Cortex-A15 TRM r0p0 MIDR
331  midr = 0x410fc0f0;
332 
333  miscRegs[MISCREG_MIDR] = midr;
334  miscRegs[MISCREG_MIDR_EL1] = midr;
335  miscRegs[MISCREG_VPIDR] = midr;
336 
337  miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
338  miscRegs[MISCREG_ID_ISAR1] = p.id_isar1;
339  miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
340  miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
341  miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
342  miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
343  miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;
344 
345  miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
346  miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
347  miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2;
348  miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
349  miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;
350 
351  miscRegs[MISCREG_ID_ISAR5] = insertBits(
352  miscRegs[MISCREG_ID_ISAR5], 19, 4,
353  haveCrypto ? 0x1112 : 0x0);
354 }
355 
356 void
357 ISA::initID64(const ArmISAParams &p)
358 {
359  // Initialize configurable id registers
360  miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1;
361  miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1;
362  miscRegs[MISCREG_ID_AA64DFR0_EL1] =
363  (p.id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
364  (p.pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
365 
366  miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1;
367  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p.id_aa64isar0_el1;
368  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p.id_aa64isar1_el1;
369  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p.id_aa64mmfr0_el1;
370  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p.id_aa64mmfr1_el1;
371  miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p.id_aa64mmfr2_el1;
372 
373  miscRegs[MISCREG_ID_DFR0_EL1] =
374  (p.pmu ? 0x03000000ULL : 0); // Enable PMUv3
375 
376  miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
377 
378  // SVE
379  miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0
380  if (haveSecurity) {
381  miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
382  } else if (haveVirtualization) {
383  miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
384  } else {
385  miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
386  }
387 
388  // Enforce consistency with system-level settings...
389 
390  // EL3
391  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
392  miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
393  haveSecurity ? 0x2 : 0x0);
394  // EL2
395  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
396  miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
397  haveVirtualization ? 0x2 : 0x0);
398  // SVE
399  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
400  miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
401  haveSVE ? 0x1 : 0x0);
402  // SecEL2
403  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
404  miscRegs[MISCREG_ID_AA64PFR0_EL1], 39, 36,
405  haveSecEL2 ? 0x1 : 0x0);
406  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
407  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 39, 36,
408  haveSecEL2 ? 0x1 : 0x0);
409  // Large ASID support
410  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
411  miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
412  haveLargeAsid64 ? 0x2 : 0x0);
413  // Physical address size
414  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
415  miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
416  encodePhysAddrRange64(physAddrRange));
417  // Crypto
418  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
419  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
420  haveCrypto ? 0x1112 : 0x0);
421  // LSE
422  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
423  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
424  haveLSE ? 0x2 : 0x0);
425  // VHE
426  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
427  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
428  haveVHE ? 0x1 : 0x0);
429  // PAN
430  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
431  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
432  havePAN ? 0x1 : 0x0);
433  // TME
434  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
435  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 27, 24,
436  haveTME ? 0x1 : 0x0);
437 }
438 
439 void
440 ISA::startup()
441 {
442  BaseISA::startup();
443 
444  if (tc) {
445  setupThreadContext();
446 
447  if (haveTME) {
448  std::unique_ptr<BaseHTMCheckpoint> cpt(new HTMCheckpoint());
449  tc->setHtmCheckpointPtr(std::move(cpt));
450  }
451  }
452 
453  afterStartup = true;
454 }
455 
456 void
457 ISA::setupThreadContext()
458 {
459  pmu->setThreadContext(tc);
460 
461  if (!system)
462  return;
463 
464  selfDebug->init(tc);
465 
466  Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
467  if (!gicv3)
468  return;
469 
470  if (!gicv3CpuInterface)
471  gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
472 
473  gicv3CpuInterface->setISA(this);
474  gicv3CpuInterface->setThreadContext(tc);
475 }
476 
477 void
478 ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
479 {
480  tc = new_tc;
481  setupThreadContext();
482 }
483 
484 RegVal
485 ISA::readMiscRegNoEffect(int misc_reg) const
486 {
487  assert(misc_reg < NumMiscRegs);
488 
489  const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
490  const auto &map = getMiscIndices(misc_reg);
491  int lower = map.first, upper = map.second;
492  // NB!: apply architectural masks according to desired register,
493  // despite possibly getting value from different (mapped) register.
494  auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
495  |(miscRegs[upper] << 32));
496  if (val & reg.res0()) {
497  DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
498  miscRegName[misc_reg], val & reg.res0());
499  }
500  if ((val & reg.res1()) != reg.res1()) {
501  DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
502  miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
503  }
504  return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
505 }
506 
507 
508 RegVal
509 ISA::readMiscReg(int misc_reg)
510 {
511  CPSR cpsr = 0;
512  PCState pc = 0;
513  SCR scr = 0;
514 
515  if (misc_reg == MISCREG_CPSR) {
516  cpsr = miscRegs[misc_reg];
517  pc = tc->pcState();
518  cpsr.j = pc.jazelle() ? 1 : 0;
519  cpsr.t = pc.thumb() ? 1 : 0;
520  return cpsr;
521  }
522 
523 #ifndef NDEBUG
524  if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
525  if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
526  warn("Unimplemented system register %s read.\n",
527  miscRegName[misc_reg]);
528  else
529  panic("Unimplemented system register %s read.\n",
530  miscRegName[misc_reg]);
531  }
532 #endif
533  misc_reg = redirectRegVHE(tc, misc_reg);
534 
535  switch (unflattenMiscReg(misc_reg)) {
536  case MISCREG_HCR:
537  case MISCREG_HCR2:
538  if (!haveVirtualization)
539  return 0;
540  break;
541  case MISCREG_CPACR:
542  {
543  const uint32_t ones = (uint32_t)(-1);
544  CPACR cpacrMask = 0;
545  // Only cp10, cp11, and ase are implemented, nothing else should
546  // be readable? (straight copy from the write code)
547  cpacrMask.cp10 = ones;
548  cpacrMask.cp11 = ones;
549  cpacrMask.asedis = ones;
550 
551  // Security Extensions may limit the readability of CPACR
552  if (haveSecurity) {
553  scr = readMiscRegNoEffect(MISCREG_SCR);
554  cpsr = readMiscRegNoEffect(MISCREG_CPSR);
555  if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
556  NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
557  // NB: Skipping the full loop, here
558  if (!nsacr.cp10) cpacrMask.cp10 = 0;
559  if (!nsacr.cp11) cpacrMask.cp11 = 0;
560  }
561  }
562  RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
563  val &= cpacrMask;
564  DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
565  miscRegName[misc_reg], val);
566  return val;
567  }
568  case MISCREG_MPIDR:
569  case MISCREG_MPIDR_EL1:
570  return readMPIDR(system, tc);
571  case MISCREG_VMPIDR:
572  case MISCREG_VMPIDR_EL2:
573  // top bit defined as RES1
574  return readMiscRegNoEffect(misc_reg) | 0x80000000;
575  case MISCREG_ID_AFR0: // not implemented, so alias MIDR
576  case MISCREG_REVIDR: // not implemented, so alias MIDR
577  case MISCREG_MIDR:
578  cpsr = readMiscRegNoEffect(MISCREG_CPSR);
579  scr = readMiscRegNoEffect(MISCREG_SCR);
580  if ((cpsr.mode == MODE_HYP) || isSecure(tc)) {
581  return readMiscRegNoEffect(misc_reg);
582  } else {
583  return readMiscRegNoEffect(MISCREG_VPIDR);
584  }
585  break;
586  case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
587  case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
588  case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
589  case MISCREG_AIDR: // AUX ID set to 0
590  case MISCREG_TCMTR: // No TCM's
591  return 0;
592 
593  case MISCREG_CLIDR:
594  warn_once("The clidr register always reports 0 caches.\n");
595  warn_once("clidr LoUIS field of 0b001 to match current "
596  "ARM implementations.\n");
597  return 0x00200000;
598  case MISCREG_CCSIDR:
599  warn_once("The ccsidr register isn't implemented and "
600  "always reads as 0.\n");
601  break;
602  case MISCREG_CTR: // AArch32, ARMv7, top bit set
603  case MISCREG_CTR_EL0: // AArch64
604  {
605  //all caches have the same line size in gem5
606  //4 byte words in ARM
607  unsigned lineSizeWords =
608  tc->getSystemPtr()->cacheLineSize() / 4;
609  unsigned log2LineSizeWords = 0;
610 
611  while (lineSizeWords >>= 1) {
612  ++log2LineSizeWords;
613  }
614 
615  CTR ctr = 0;
616  //log2 of minimun i-cache line size (words)
617  ctr.iCacheLineSize = log2LineSizeWords;
618  //b11 - gem5 uses pipt
619  ctr.l1IndexPolicy = 0x3;
620  //log2 of minimum d-cache line size (words)
621  ctr.dCacheLineSize = log2LineSizeWords;
622  //log2 of max reservation size (words)
623  ctr.erg = log2LineSizeWords;
624  //log2 of max writeback size (words)
625  ctr.cwg = log2LineSizeWords;
626  //b100 - gem5 format is ARMv7
627  ctr.format = 0x4;
628 
629  return ctr;
630  }
631  case MISCREG_ACTLR:
632  warn("Not doing anything for miscreg ACTLR\n");
633  break;
634 
635  case MISCREG_PMXEVTYPER_PMCCFILTR:
636  case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
637  case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
638  case MISCREG_PMCR ... MISCREG_PMOVSSET:
639  return pmu->readMiscReg(misc_reg);
640 
641  case MISCREG_CPSR_Q:
642  panic("shouldn't be reading this register seperately\n");
643  case MISCREG_FPSCR_QC:
644  return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
645  case MISCREG_FPSCR_EXC:
646  return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
647  case MISCREG_FPSR:
648  {
649  const uint32_t ones = (uint32_t)(-1);
650  FPSCR fpscrMask = 0;
651  fpscrMask.ioc = ones;
652  fpscrMask.dzc = ones;
653  fpscrMask.ofc = ones;
654  fpscrMask.ufc = ones;
655  fpscrMask.ixc = ones;
656  fpscrMask.idc = ones;
657  fpscrMask.qc = ones;
658  fpscrMask.v = ones;
659  fpscrMask.c = ones;
660  fpscrMask.z = ones;
661  fpscrMask.n = ones;
662  return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
663  }
664  case MISCREG_FPCR:
665  {
666  const uint32_t ones = (uint32_t)(-1);
667  FPSCR fpscrMask = 0;
668  fpscrMask.len = ones;
669  fpscrMask.fz16 = ones;
670  fpscrMask.stride = ones;
671  fpscrMask.rMode = ones;
672  fpscrMask.fz = ones;
673  fpscrMask.dn = ones;
674  fpscrMask.ahp = ones;
675  return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
676  }
677  case MISCREG_NZCV:
678  {
679  CPSR cpsr = 0;
680  cpsr.nz = tc->readCCReg(CCREG_NZ);
681  cpsr.c = tc->readCCReg(CCREG_C);
682  cpsr.v = tc->readCCReg(CCREG_V);
683  return cpsr;
684  }
685  case MISCREG_DAIF:
686  {
687  CPSR cpsr = 0;
688  cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
689  return cpsr;
690  }
691  case MISCREG_SP_EL0:
692  {
693  return tc->readIntReg(INTREG_SP0);
694  }
695  case MISCREG_SP_EL1:
696  {
697  return tc->readIntReg(INTREG_SP1);
698  }
699  case MISCREG_SP_EL2:
700  {
701  return tc->readIntReg(INTREG_SP2);
702  }
703  case MISCREG_SPSEL:
704  {
705  return miscRegs[MISCREG_CPSR] & 0x1;
706  }
707  case MISCREG_CURRENTEL:
708  {
709  return miscRegs[MISCREG_CPSR] & 0xc;
710  }
711  case MISCREG_PAN:
712  {
713  return miscRegs[MISCREG_CPSR] & 0x400000;
714  }
715  case MISCREG_L2CTLR:
716  {
717  // mostly unimplemented, just set NumCPUs field from sim and return
718  L2CTLR l2ctlr = 0;
719  // b00:1CPU to b11:4CPUs
720  l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
721  return l2ctlr;
722  }
723  case MISCREG_DBGDIDR:
724  /* For now just implement the version number.
725  * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
726  */
727  return 0x5 << 16;
728  case MISCREG_DBGDSCRint:
729  return readMiscRegNoEffect(MISCREG_DBGDSCRint);
730  case MISCREG_ISR:
731  {
732  auto ic = dynamic_cast<ArmISA::Interrupts *>(
733  tc->getCpuPtr()->getInterruptController(tc->threadId()));
734  return ic->getISR(
735  readMiscRegNoEffect(MISCREG_HCR),
736  readMiscRegNoEffect(MISCREG_CPSR),
737  readMiscRegNoEffect(MISCREG_SCR));
738  }
739  case MISCREG_ISR_EL1:
740  {
741  auto ic = dynamic_cast<ArmISA::Interrupts *>(
742  tc->getCpuPtr()->getInterruptController(tc->threadId()));
743  return ic->getISR(
744  readMiscRegNoEffect(MISCREG_HCR_EL2),
745  readMiscRegNoEffect(MISCREG_CPSR),
746  readMiscRegNoEffect(MISCREG_SCR_EL3));
747  }
748  case MISCREG_DCZID_EL0:
749  return 0x04; // DC ZVA clear 64-byte chunks
750  case MISCREG_HCPTR:
751  {
752  RegVal val = readMiscRegNoEffect(misc_reg);
753  // The trap bit associated with CP14 is defined as RAZ
754  val &= ~(1 << 14);
755  // If a CP bit in NSACR is 0 then the corresponding bit in
756  // HCPTR is RAO/WI
757  bool secure_lookup = haveSecurity && isSecure(tc);
758  if (!secure_lookup) {
759  RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
760  val |= (mask ^ 0x7FFF) & 0xBFFF;
761  }
762  // Set the bits for unimplemented coprocessors to RAO/WI
763  val |= 0x33FF;
764  return (val);
765  }
766  case MISCREG_HDFAR: // alias for secure DFAR
767  return readMiscRegNoEffect(MISCREG_DFAR_S);
768  case MISCREG_HIFAR: // alias for secure IFAR
769  return readMiscRegNoEffect(MISCREG_IFAR_S);
770 
771  case MISCREG_ID_PFR0:
772  // !ThumbEE | !Jazelle | Thumb | ARM
773  return 0x00000031;
774  case MISCREG_ID_PFR1:
775  { // Timer | Virti | !M Profile | TrustZone | ARMv4
776  bool haveTimer = (system->getGenericTimer() != NULL);
777  return 0x00000001
778  | (haveSecurity ? 0x00000010 : 0x0)
779  | (haveVirtualization ? 0x00001000 : 0x0)
780  | (haveTimer ? 0x00010000 : 0x0);
781  }
782  case MISCREG_ID_AA64PFR0_EL1:
783  return 0x0000000000000002 | // AArch{64,32} supported at EL0
784  0x0000000000000020 | // EL1
785  (haveVirtualization ? 0x0000000000000200 : 0) | // EL2
786  (haveSecurity ? 0x0000000000002000 : 0) | // EL3
787  (haveSVE ? 0x0000000100000000 : 0) | // SVE
788  (haveSecEL2 ? 0x0000001000000000 : 0) | // SecEL2
789  (gicv3CpuInterface ? 0x0000000001000000 : 0);
790  case MISCREG_ID_AA64PFR1_EL1:
791  return 0; // bits [63:0] RES0 (reserved for future use)
792 
793  // Generic Timer registers
794  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
795  case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
796  return getGenericTimer().readMiscReg(misc_reg);
797 
798  case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
799  case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
800  case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
801  return getGICv3CPUInterface().readMiscReg(misc_reg);
802 
803  default:
804  break;
805 
806  }
807  return readMiscRegNoEffect(misc_reg);
808 }
809 
810 void
811 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
812 {
813  assert(misc_reg < NumMiscRegs);
814 
815  const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
816  const auto &map = getMiscIndices(misc_reg);
817  int lower = map.first, upper = map.second;
818 
819  auto v = (val & ~reg.wi()) | reg.rao();
820  if (upper > 0) {
821  miscRegs[lower] = bits(v, 31, 0);
822  miscRegs[upper] = bits(v, 63, 32);
823  DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
824  miscRegName[misc_reg], misc_reg, lower, upper, v);
825  } else {
826  miscRegs[lower] = v;
827  DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
828  miscRegName[misc_reg], misc_reg, lower, v);
829  }
830 }
831 
832 void
833 ISA::setMiscReg(int misc_reg, RegVal val)
834 {
835 
836  RegVal newVal = val;
837  bool secure_lookup;
838  SCR scr;
839 
840  if (misc_reg == MISCREG_CPSR) {
841  updateRegMap(val);
842 
843 
844  CPSR old_cpsr = miscRegs[MISCREG_CPSR];
845  int old_mode = old_cpsr.mode;
846  CPSR cpsr = val;
847  if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
848  getMMUPtr(tc)->invalidateMiscReg();
849  }
850 
851  if (cpsr.pan != old_cpsr.pan) {
852  getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
853  }
854 
855  DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
856  miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
857  PCState pc = tc->pcState();
858  pc.nextThumb(cpsr.t);
859  pc.nextJazelle(cpsr.j);
860  pc.illegalExec(cpsr.il == 1);
861  selfDebug->setDebugMask(cpsr.d == 1);
862 
863  tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
864 
865  // Follow slightly different semantics if a CheckerCPU object
866  // is connected
867  CheckerCPU *checker = tc->getCheckerCpuPtr();
868  if (checker) {
869  tc->pcStateNoRecord(pc);
870  } else {
871  tc->pcState(pc);
872  }
873  } else {
874 #ifndef NDEBUG
875  if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
876  if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
877  warn("Unimplemented system register %s write with %#x.\n",
878  miscRegName[misc_reg], val);
879  else
880  panic("Unimplemented system register %s write with %#x.\n",
881  miscRegName[misc_reg], val);
882  }
883 #endif
884  misc_reg = redirectRegVHE(tc, misc_reg);
885 
886  switch (unflattenMiscReg(misc_reg)) {
887  case MISCREG_CPACR:
888  {
889 
890  const uint32_t ones = (uint32_t)(-1);
891  CPACR cpacrMask = 0;
892  // Only cp10, cp11, and ase are implemented, nothing else should
893  // be writable
894  cpacrMask.cp10 = ones;
895  cpacrMask.cp11 = ones;
896  cpacrMask.asedis = ones;
897 
898  // Security Extensions may limit the writability of CPACR
899  if (haveSecurity) {
900  scr = readMiscRegNoEffect(MISCREG_SCR);
901  CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
902  if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
903  NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
904  // NB: Skipping the full loop, here
905  if (!nsacr.cp10) cpacrMask.cp10 = 0;
906  if (!nsacr.cp11) cpacrMask.cp11 = 0;
907  }
908  }
909 
910  RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);
911  newVal &= cpacrMask;
912  newVal |= old_val & ~cpacrMask;
913  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
914  miscRegName[misc_reg], newVal);
915  }
916  break;
917  case MISCREG_CPACR_EL1:
918  {
919  const uint32_t ones = (uint32_t)(-1);
920  CPACR cpacrMask = 0;
921  cpacrMask.tta = ones;
922  cpacrMask.fpen = ones;
923  if (haveSVE) {
924  cpacrMask.zen = ones;
925  }
926  newVal &= cpacrMask;
927  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
928  miscRegName[misc_reg], newVal);
929  }
930  break;
931  case MISCREG_CPTR_EL2:
932  {
933  const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
934  const uint32_t ones = (uint32_t)(-1);
935  CPTR cptrMask = 0;
936  cptrMask.tcpac = ones;
937  cptrMask.tta = ones;
938  cptrMask.tfp = ones;
939  if (haveSVE) {
940  cptrMask.tz = ones;
941  cptrMask.zen = hcr.e2h ? ones : 0;
942  }
943  cptrMask.fpen = hcr.e2h ? ones : 0;
944  newVal &= cptrMask;
945  cptrMask = 0;
946  cptrMask.res1_13_12_el2 = ones;
947  cptrMask.res1_7_0_el2 = ones;
948  if (!haveSVE) {
949  cptrMask.res1_8_el2 = ones;
950  }
951  cptrMask.res1_9_el2 = ones;
952  newVal |= cptrMask;
953  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
954  miscRegName[misc_reg], newVal);
955  }
956  break;
957  case MISCREG_CPTR_EL3:
958  {
959  const uint32_t ones = (uint32_t)(-1);
960  CPTR cptrMask = 0;
961  cptrMask.tcpac = ones;
962  cptrMask.tta = ones;
963  cptrMask.tfp = ones;
964  if (haveSVE) {
965  cptrMask.ez = ones;
966  }
967  newVal &= cptrMask;
968  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
969  miscRegName[misc_reg], newVal);
970  }
971  break;
972  case MISCREG_CSSELR:
973  warn_once("The csselr register isn't implemented.\n");
974  return;
975 
976  case MISCREG_DC_ZVA_Xt:
977  warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
978  return;
979 
980  case MISCREG_FPSCR:
981  {
982  const uint32_t ones = (uint32_t)(-1);
983  FPSCR fpscrMask = 0;
984  fpscrMask.ioc = ones;
985  fpscrMask.dzc = ones;
986  fpscrMask.ofc = ones;
987  fpscrMask.ufc = ones;
988  fpscrMask.ixc = ones;
989  fpscrMask.idc = ones;
990  fpscrMask.ioe = ones;
991  fpscrMask.dze = ones;
992  fpscrMask.ofe = ones;
993  fpscrMask.ufe = ones;
994  fpscrMask.ixe = ones;
995  fpscrMask.ide = ones;
996  fpscrMask.len = ones;
997  fpscrMask.fz16 = ones;
998  fpscrMask.stride = ones;
999  fpscrMask.rMode = ones;
1000  fpscrMask.fz = ones;
1001  fpscrMask.dn = ones;
1002  fpscrMask.ahp = ones;
1003  fpscrMask.qc = ones;
1004  fpscrMask.v = ones;
1005  fpscrMask.c = ones;
1006  fpscrMask.z = ones;
1007  fpscrMask.n = ones;
1008  newVal = (newVal & (uint32_t)fpscrMask) |
1009  (readMiscRegNoEffect(MISCREG_FPSCR) &
1010  ~(uint32_t)fpscrMask);
1011  tc->getDecoderPtr()->setContext(newVal);
1012  }
1013  break;
1014  case MISCREG_FPSR:
1015  {
1016  const uint32_t ones = (uint32_t)(-1);
1017  FPSCR fpscrMask = 0;
1018  fpscrMask.ioc = ones;
1019  fpscrMask.dzc = ones;
1020  fpscrMask.ofc = ones;
1021  fpscrMask.ufc = ones;
1022  fpscrMask.ixc = ones;
1023  fpscrMask.idc = ones;
1024  fpscrMask.qc = ones;
1025  fpscrMask.v = ones;
1026  fpscrMask.c = ones;
1027  fpscrMask.z = ones;
1028  fpscrMask.n = ones;
1029  newVal = (newVal & (uint32_t)fpscrMask) |
1030  (readMiscRegNoEffect(MISCREG_FPSCR) &
1031  ~(uint32_t)fpscrMask);
1032  misc_reg = MISCREG_FPSCR;
1033  }
1034  break;
1035  case MISCREG_FPCR:
1036  {
1037  const uint32_t ones = (uint32_t)(-1);
1038  FPSCR fpscrMask = 0;
1039  fpscrMask.len = ones;
1040  fpscrMask.fz16 = ones;
1041  fpscrMask.stride = ones;
1042  fpscrMask.rMode = ones;
1043  fpscrMask.fz = ones;
1044  fpscrMask.dn = ones;
1045  fpscrMask.ahp = ones;
1046  newVal = (newVal & (uint32_t)fpscrMask) |
1047  (readMiscRegNoEffect(MISCREG_FPSCR) &
1048  ~(uint32_t)fpscrMask);
1049  misc_reg = MISCREG_FPSCR;
1050  }
1051  break;
1052  case MISCREG_CPSR_Q:
1053  {
1054  assert(!(newVal & ~CpsrMaskQ));
1055  newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1056  misc_reg = MISCREG_CPSR;
1057  }
1058  break;
1059  case MISCREG_FPSCR_QC:
1060  {
1061  newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1062  (newVal & FpscrQcMask);
1063  misc_reg = MISCREG_FPSCR;
1064  }
1065  break;
1066  case MISCREG_FPSCR_EXC:
1067  {
1068  newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1069  (newVal & FpscrExcMask);
1070  misc_reg = MISCREG_FPSCR;
1071  }
1072  break;
1073  case MISCREG_FPEXC:
1074  {
1075  // vfpv3 architecture, section B.6.1 of DDI04068
1076  // bit 29 - valid only if fpexc[31] is 0
1077  const uint32_t fpexcMask = 0x60000000;
1078  newVal = (newVal & fpexcMask) |
1079  (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1080  }
1081  break;
1082  case MISCREG_HCR2:
1083  if (!haveVirtualization)
1084  return;
1085  break;
1086  case MISCREG_HCR:
1087  {
1088  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1089  selfDebug->setenableTDETGE((HCR)val, mdcr);
1090  if (!haveVirtualization)
1091  return;
1092  }
1093  break;
1094 
1095  case MISCREG_HDCR:
1096  {
1097  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1098  selfDebug->setenableTDETGE(hcr, (HDCR)val);
1099  }
1100  break;
1101  case MISCREG_DBGOSLAR:
1102  {
1103  OSL r = tc->readMiscReg(MISCREG_DBGOSLSR);
1104  const uint32_t temp = (val == 0xC5ACCE55)? 0x1 : 0x0;
1105  selfDebug->updateOSLock((RegVal) temp);
1106  r.oslk = bits(temp,0);
1107  tc->setMiscReg(MISCREG_DBGOSLSR, r);
1108  }
1109  break;
1110  case MISCREG_DBGBCR0:
1111  selfDebug->updateDBGBCR(0, val);
1112  break;
1113  case MISCREG_DBGBCR1:
1114  selfDebug->updateDBGBCR(1, val);
1115  break;
1116  case MISCREG_DBGBCR2:
1117  selfDebug->updateDBGBCR(2, val);
1118  break;
1119  case MISCREG_DBGBCR3:
1120  selfDebug->updateDBGBCR(3, val);
1121  break;
1122  case MISCREG_DBGBCR4:
1123  selfDebug->updateDBGBCR(4, val);
1124  break;
1125  case MISCREG_DBGBCR5:
1126  selfDebug->updateDBGBCR(5, val);
1127  break;
1128  case MISCREG_DBGBCR6:
1129  selfDebug->updateDBGBCR(6, val);
1130  break;
1131  case MISCREG_DBGBCR7:
1132  selfDebug->updateDBGBCR(7, val);
1133  break;
1134  case MISCREG_DBGBCR8:
1135  selfDebug->updateDBGBCR(8, val);
1136  break;
1137  case MISCREG_DBGBCR9:
1138  selfDebug->updateDBGBCR(9, val);
1139  break;
1140  case MISCREG_DBGBCR10:
1141  selfDebug->updateDBGBCR(10, val);
1142  break;
1143  case MISCREG_DBGBCR11:
1144  selfDebug->updateDBGBCR(11, val);
1145  break;
1146  case MISCREG_DBGBCR12:
1147  selfDebug->updateDBGBCR(12, val);
1148  break;
1149  case MISCREG_DBGBCR13:
1150  selfDebug->updateDBGBCR(13, val);
1151  break;
1152  case MISCREG_DBGBCR14:
1153  selfDebug->updateDBGBCR(14, val);
1154  break;
1155  case MISCREG_DBGBCR15:
1156  selfDebug->updateDBGBCR(15, val);
1157  break;
1158  case MISCREG_DBGWCR0:
1159  selfDebug->updateDBGWCR(0, val);
1160  break;
1161  case MISCREG_DBGWCR1:
1162  selfDebug->updateDBGWCR(1, val);
1163  break;
1164  case MISCREG_DBGWCR2:
1165  selfDebug->updateDBGWCR(2, val);
1166  break;
1167  case MISCREG_DBGWCR3:
1168  selfDebug->updateDBGWCR(3, val);
1169  break;
1170  case MISCREG_DBGWCR4:
1171  selfDebug->updateDBGWCR(4, val);
1172  break;
1173  case MISCREG_DBGWCR5:
1174  selfDebug->updateDBGWCR(5, val);
1175  break;
1176  case MISCREG_DBGWCR6:
1177  selfDebug->updateDBGWCR(6, val);
1178  break;
1179  case MISCREG_DBGWCR7:
1180  selfDebug->updateDBGWCR(7, val);
1181  break;
1182  case MISCREG_DBGWCR8:
1183  selfDebug->updateDBGWCR(8, val);
1184  break;
1185  case MISCREG_DBGWCR9:
1186  selfDebug->updateDBGWCR(9, val);
1187  break;
1188  case MISCREG_DBGWCR10:
1189  selfDebug->updateDBGWCR(10, val);
1190  break;
1191  case MISCREG_DBGWCR11:
1192  selfDebug->updateDBGWCR(11, val);
1193  break;
1194  case MISCREG_DBGWCR12:
1195  selfDebug->updateDBGWCR(12, val);
1196  break;
1197  case MISCREG_DBGWCR13:
1198  selfDebug->updateDBGWCR(13, val);
1199  break;
1200  case MISCREG_DBGWCR14:
1201  selfDebug->updateDBGWCR(14, val);
1202  break;
1203  case MISCREG_DBGWCR15:
1204  selfDebug->updateDBGWCR(15, val);
1205  break;
1206 
1207  case MISCREG_MDCR_EL2:
1208  {
1209  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1210  selfDebug->setenableTDETGE(hcr, (HDCR)val);
1211  }
1212  break;
1213  case MISCREG_SDCR:
1214  case MISCREG_MDCR_EL3:
1215  {
1216  selfDebug->setbSDD(val);
1217  }
1218  break;
1219  case MISCREG_DBGDSCRext:
1220  {
1221  selfDebug->setMDBGen(val);
1222  DBGDS32 r = tc->readMiscReg(MISCREG_DBGDSCRint);
1223  DBGDS32 v = val;
1224  r.moe = v.moe;
1225  r.udccdis = v.udccdis;
1226  r.mdbgen = v.mdbgen;
1227  tc->setMiscReg(MISCREG_DBGDSCRint, r);
1228  r = tc->readMiscReg(MISCREG_DBGDSCRint);
1229  }
1230 
1231  break;
1232  case MISCREG_MDSCR_EL1:
1233  {
1234  selfDebug->setMDSCRvals(val);
1235  }
1236  break;
1237 
1238  case MISCREG_OSLAR_EL1:
1239  {
1240  selfDebug->updateOSLock(val);
1241  OSL r = tc->readMiscReg(MISCREG_OSLSR_EL1);
1242  r.oslk = bits(val, 0);
1243  r.oslm_3 = 1;
1244  tc->setMiscReg(MISCREG_OSLSR_EL1, r);
1245  }
1246  break;
1247 
1248  case MISCREG_DBGBCR0_EL1:
1249  selfDebug->updateDBGBCR(0, val);
1250  break;
1251  case MISCREG_DBGBCR1_EL1:
1252  selfDebug->updateDBGBCR(1, val);
1253  break;
1254  case MISCREG_DBGBCR2_EL1:
1255  selfDebug->updateDBGBCR(2, val);
1256  break;
1257  case MISCREG_DBGBCR3_EL1:
1258  selfDebug->updateDBGBCR(3, val);
1259  break;
1260  case MISCREG_DBGBCR4_EL1:
1261  selfDebug->updateDBGBCR(4, val);
1262  break;
1263  case MISCREG_DBGBCR5_EL1:
1264  selfDebug->updateDBGBCR(5, val);
1265  break;
1266  case MISCREG_DBGBCR6_EL1:
1267  selfDebug->updateDBGBCR(6, val);
1268  break;
1269  case MISCREG_DBGBCR7_EL1:
1270  selfDebug->updateDBGBCR(7, val);
1271  break;
1272  case MISCREG_DBGBCR8_EL1:
1273  selfDebug->updateDBGBCR(8, val);
1274  break;
1275  case MISCREG_DBGBCR9_EL1:
1276  selfDebug->updateDBGBCR(9, val);
1277  break;
1278  case MISCREG_DBGBCR10_EL1:
1279  selfDebug->updateDBGBCR(10, val);
1280  break;
1281  case MISCREG_DBGBCR11_EL1:
1282  selfDebug->updateDBGBCR(11, val);
1283  break;
1284  case MISCREG_DBGBCR12_EL1:
1285  selfDebug->updateDBGBCR(12, val);
1286  break;
1287  case MISCREG_DBGBCR13_EL1:
1288  selfDebug->updateDBGBCR(13, val);
1289  break;
1290  case MISCREG_DBGBCR14_EL1:
1291  selfDebug->updateDBGBCR(14, val);
1292  break;
1293  case MISCREG_DBGBCR15_EL1:
1294  selfDebug->updateDBGBCR(15, val);
1295  break;
1296  case MISCREG_DBGWCR0_EL1:
1297  selfDebug->updateDBGWCR(0, val);
1298  break;
1299  case MISCREG_DBGWCR1_EL1:
1300  selfDebug->updateDBGWCR(1, val);
1301  break;
1302  case MISCREG_DBGWCR2_EL1:
1303  selfDebug->updateDBGWCR(2, val);
1304  break;
1305  case MISCREG_DBGWCR3_EL1:
1306  selfDebug->updateDBGWCR(3, val);
1307  break;
1308  case MISCREG_DBGWCR4_EL1:
1309  selfDebug->updateDBGWCR(4, val);
1310  break;
1311  case MISCREG_DBGWCR5_EL1:
1312  selfDebug->updateDBGWCR(5, val);
1313  break;
1314  case MISCREG_DBGWCR6_EL1:
1315  selfDebug->updateDBGWCR(6, val);
1316  break;
1317  case MISCREG_DBGWCR7_EL1:
1318  selfDebug->updateDBGWCR(7, val);
1319  break;
1320  case MISCREG_DBGWCR8_EL1:
1321  selfDebug->updateDBGWCR(8, val);
1322  break;
1323  case MISCREG_DBGWCR9_EL1:
1324  selfDebug->updateDBGWCR(9, val);
1325  break;
1326  case MISCREG_DBGWCR10_EL1:
1327  selfDebug->updateDBGWCR(10, val);
1328  break;
1329  case MISCREG_DBGWCR11_EL1:
1330  selfDebug->updateDBGWCR(11, val);
1331  break;
1332  case MISCREG_DBGWCR12_EL1:
1333  selfDebug->updateDBGWCR(12, val);
1334  break;
1335  case MISCREG_DBGWCR13_EL1:
1336  selfDebug->updateDBGWCR(13, val);
1337  break;
1338  case MISCREG_DBGWCR14_EL1:
1339  selfDebug->updateDBGWCR(14, val);
1340  break;
1341  case MISCREG_DBGWCR15_EL1:
1342  selfDebug->updateDBGWCR(15, val);
1343  break;
1344  case MISCREG_IFSR:
1345  {
1346  // ARM ARM (ARM DDI 0406C.b) B4.1.96
1347  const uint32_t ifsrMask =
1348  mask(31, 13) | mask(11, 11) | mask(8, 6);
1349  newVal = newVal & ~ifsrMask;
1350  }
1351  break;
1352  case MISCREG_DFSR:
1353  {
1354  // ARM ARM (ARM DDI 0406C.b) B4.1.52
1355  const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1356  newVal = newVal & ~dfsrMask;
1357  }
1358  break;
1359  case MISCREG_AMAIR0:
1360  case MISCREG_AMAIR1:
1361  {
1362  // ARM ARM (ARM DDI 0406C.b) B4.1.5
1363  // Valid only with LPAE
1364  if (!haveLPAE)
1365  return;
1366  DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1367  }
1368  break;
1369  case MISCREG_SCR:
1370  getMMUPtr(tc)->invalidateMiscReg();
1371  break;
1372  case MISCREG_SCTLR:
1373  {
1374  DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1375  scr = readMiscRegNoEffect(MISCREG_SCR);
1376 
1377  MiscRegIndex sctlr_idx;
1378  if (haveSecurity && !highestELIs64 && !scr.ns) {
1379  sctlr_idx = MISCREG_SCTLR_S;
1380  } else {
1381  sctlr_idx = MISCREG_SCTLR_NS;
1382  }
1383 
1384  SCTLR sctlr = miscRegs[sctlr_idx];
1385  SCTLR new_sctlr = newVal;
1386  new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1387  miscRegs[sctlr_idx] = (RegVal)new_sctlr;
1388  getMMUPtr(tc)->invalidateMiscReg();
1389  }
1390  case MISCREG_MIDR:
1391  case MISCREG_ID_PFR0:
1392  case MISCREG_ID_PFR1:
1393  case MISCREG_ID_DFR0:
1394  case MISCREG_ID_MMFR0:
1395  case MISCREG_ID_MMFR1:
1396  case MISCREG_ID_MMFR2:
1397  case MISCREG_ID_MMFR3:
1398  case MISCREG_ID_MMFR4:
1399  case MISCREG_ID_ISAR0:
1400  case MISCREG_ID_ISAR1:
1401  case MISCREG_ID_ISAR2:
1402  case MISCREG_ID_ISAR3:
1403  case MISCREG_ID_ISAR4:
1404  case MISCREG_ID_ISAR5:
1405 
1406  case MISCREG_MPIDR:
1407  case MISCREG_FPSID:
1408  case MISCREG_TLBTR:
1409  case MISCREG_MVFR0:
1410  case MISCREG_MVFR1:
1411 
1412  case MISCREG_ID_AA64AFR0_EL1:
1413  case MISCREG_ID_AA64AFR1_EL1:
1414  case MISCREG_ID_AA64DFR0_EL1:
1415  case MISCREG_ID_AA64DFR1_EL1:
1416  case MISCREG_ID_AA64ISAR0_EL1:
1417  case MISCREG_ID_AA64ISAR1_EL1:
1418  case MISCREG_ID_AA64MMFR0_EL1:
1419  case MISCREG_ID_AA64MMFR1_EL1:
1420  case MISCREG_ID_AA64MMFR2_EL1:
1421  case MISCREG_ID_AA64PFR0_EL1:
1422  case MISCREG_ID_AA64PFR1_EL1:
1423  // ID registers are constants.
1424  return;
1425 
1426  // TLB Invalidate All
1427  case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1428  {
1429  assert32();
1430  scr = readMiscReg(MISCREG_SCR);
1431 
1432  TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1433  tlbiOp(tc);
1434  return;
1435  }
1436  // TLB Invalidate All, Inner Shareable
1437  case MISCREG_TLBIALLIS:
1438  {
1439  assert32();
1440  scr = readMiscReg(MISCREG_SCR);
1441 
1442  TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1443  tlbiOp.broadcast(tc);
1444  return;
1445  }
1446  // Instruction TLB Invalidate All
1447  case MISCREG_ITLBIALL:
1448  {
1449  assert32();
1450  scr = readMiscReg(MISCREG_SCR);
1451 
1452  ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1453  tlbiOp(tc);
1454  return;
1455  }
1456  // Data TLB Invalidate All
1457  case MISCREG_DTLBIALL:
1458  {
1459  assert32();
1460  scr = readMiscReg(MISCREG_SCR);
1461 
1462  DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1463  tlbiOp(tc);
1464  return;
1465  }
1466  // TLB Invalidate by VA
1467  // mcr tlbimval(is) is invalidating all matching entries
1468  // regardless of the level of lookup, since in gem5 we cache
1469  // in the tlb the last level of lookup only.
1470  case MISCREG_TLBIMVA:
1471  case MISCREG_TLBIMVAL:
1472  {
1473  assert32();
1474  scr = readMiscReg(MISCREG_SCR);
1475 
1476  TLBIMVA tlbiOp(EL1,
1477  haveSecurity && !scr.ns,
1478  mbits(newVal, 31, 12),
1479  bits(newVal, 7,0));
1480 
1481  tlbiOp(tc);
1482  return;
1483  }
1484  // TLB Invalidate by VA, Inner Shareable
1485  case MISCREG_TLBIMVAIS:
1486  case MISCREG_TLBIMVALIS:
1487  {
1488  assert32();
1489  scr = readMiscReg(MISCREG_SCR);
1490 
1491  TLBIMVA tlbiOp(EL1,
1492  haveSecurity && !scr.ns,
1493  mbits(newVal, 31, 12),
1494  bits(newVal, 7,0));
1495 
1496  tlbiOp.broadcast(tc);
1497  return;
1498  }
1499  // TLB Invalidate by ASID match
1500  case MISCREG_TLBIASID:
1501  {
1502  assert32();
1503  scr = readMiscReg(MISCREG_SCR);
1504 
1505  TLBIASID tlbiOp(EL1,
1506  haveSecurity && !scr.ns,
1507  bits(newVal, 7,0));
1508 
1509  tlbiOp(tc);
1510  return;
1511  }
1512  // TLB Invalidate by ASID match, Inner Shareable
1513  case MISCREG_TLBIASIDIS:
1514  {
1515  assert32();
1516  scr = readMiscReg(MISCREG_SCR);
1517 
1518  TLBIASID tlbiOp(EL1,
1519  haveSecurity && !scr.ns,
1520  bits(newVal, 7,0));
1521 
1522  tlbiOp.broadcast(tc);
1523  return;
1524  }
1525  // mcr tlbimvaal(is) is invalidating all matching entries
1526  // regardless of the level of lookup, since in gem5 we cache
1527  // in the tlb the last level of lookup only.
1528  // TLB Invalidate by VA, All ASID
1529  case MISCREG_TLBIMVAA:
1530  case MISCREG_TLBIMVAAL:
1531  {
1532  assert32();
1533  scr = readMiscReg(MISCREG_SCR);
1534 
1535  TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1536  mbits(newVal, 31,12));
1537 
1538  tlbiOp(tc);
1539  return;
1540  }
1541  // TLB Invalidate by VA, All ASID, Inner Shareable
1542  case MISCREG_TLBIMVAAIS:
1543  case MISCREG_TLBIMVAALIS:
1544  {
1545  assert32();
1546  scr = readMiscReg(MISCREG_SCR);
1547 
1548  TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1549  mbits(newVal, 31,12));
1550 
1551  tlbiOp.broadcast(tc);
1552  return;
1553  }
1554  // mcr tlbimvalh(is) is invalidating all matching entries
1555  // regardless of the level of lookup, since in gem5 we cache
1556  // in the tlb the last level of lookup only.
1557  // TLB Invalidate by VA, Hyp mode
1558  case MISCREG_TLBIMVAH:
1559  case MISCREG_TLBIMVALH:
1560  {
1561  assert32();
1562  scr = readMiscReg(MISCREG_SCR);
1563 
1564  TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1565  mbits(newVal, 31,12));
1566 
1567  tlbiOp(tc);
1568  return;
1569  }
1570  // TLB Invalidate by VA, Hyp mode, Inner Shareable
1571  case MISCREG_TLBIMVAHIS:
1572  case MISCREG_TLBIMVALHIS:
1573  {
1574  assert32();
1575  scr = readMiscReg(MISCREG_SCR);
1576 
1577  TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1578  mbits(newVal, 31,12));
1579 
1580  tlbiOp.broadcast(tc);
1581  return;
1582  }
1583  // mcr tlbiipas2l(is) is invalidating all matching entries
1584  // regardless of the level of lookup, since in gem5 we cache
1585  // in the tlb the last level of lookup only.
1586  // TLB Invalidate by Intermediate Physical Address, Stage 2
1587  case MISCREG_TLBIIPAS2:
1588  case MISCREG_TLBIIPAS2L:
1589  {
1590  assert32();
1591  scr = readMiscReg(MISCREG_SCR);
1592 
1593  TLBIIPA tlbiOp(EL1,
1594  haveSecurity && !scr.ns,
1595  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1596 
1597  tlbiOp(tc);
1598  return;
1599  }
1600  // TLB Invalidate by Intermediate Physical Address, Stage 2,
1601  // Inner Shareable
1602  case MISCREG_TLBIIPAS2IS:
1603  case MISCREG_TLBIIPAS2LIS:
1604  {
1605  assert32();
1606  scr = readMiscReg(MISCREG_SCR);
1607 
1608  TLBIIPA tlbiOp(EL1,
1609  haveSecurity && !scr.ns,
1610  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1611 
1612  tlbiOp.broadcast(tc);
1613  return;
1614  }
1615  // Instruction TLB Invalidate by VA
1616  case MISCREG_ITLBIMVA:
1617  {
1618  assert32();
1619  scr = readMiscReg(MISCREG_SCR);
1620 
1621  ITLBIMVA tlbiOp(EL1,
1622  haveSecurity && !scr.ns,
1623  mbits(newVal, 31, 12),
1624  bits(newVal, 7,0));
1625 
1626  tlbiOp(tc);
1627  return;
1628  }
1629  // Data TLB Invalidate by VA
1630  case MISCREG_DTLBIMVA:
1631  {
1632  assert32();
1633  scr = readMiscReg(MISCREG_SCR);
1634 
1635  DTLBIMVA tlbiOp(EL1,
1636  haveSecurity && !scr.ns,
1637  mbits(newVal, 31, 12),
1638  bits(newVal, 7,0));
1639 
1640  tlbiOp(tc);
1641  return;
1642  }
1643  // Instruction TLB Invalidate by ASID match
1644  case MISCREG_ITLBIASID:
1645  {
1646  assert32();
1647  scr = readMiscReg(MISCREG_SCR);
1648 
1649  ITLBIASID tlbiOp(EL1,
1650  haveSecurity && !scr.ns,
1651  bits(newVal, 7,0));
1652 
1653  tlbiOp(tc);
1654  return;
1655  }
1656  // Data TLB Invalidate by ASID match
1657  case MISCREG_DTLBIASID:
1658  {
1659  assert32();
1660  scr = readMiscReg(MISCREG_SCR);
1661 
1662  DTLBIASID tlbiOp(EL1,
1663  haveSecurity && !scr.ns,
1664  bits(newVal, 7,0));
1665 
1666  tlbiOp(tc);
1667  return;
1668  }
1669  // TLB Invalidate All, Non-Secure Non-Hyp
1670  case MISCREG_TLBIALLNSNH:
1671  {
1672  assert32();
1673 
1674  TLBIALLN tlbiOp(EL1);
1675  tlbiOp(tc);
1676  return;
1677  }
1678  // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1679  case MISCREG_TLBIALLNSNHIS:
1680  {
1681  assert32();
1682 
1683  TLBIALLN tlbiOp(EL1);
1684  tlbiOp.broadcast(tc);
1685  return;
1686  }
1687  // TLB Invalidate All, Hyp mode
1688  case MISCREG_TLBIALLH:
1689  {
1690  assert32();
1691 
1692  TLBIALLN tlbiOp(EL2);
1693  tlbiOp(tc);
1694  return;
1695  }
1696  // TLB Invalidate All, Hyp mode, Inner Shareable
1697  case MISCREG_TLBIALLHIS:
1698  {
1699  assert32();
1700 
1701  TLBIALLN tlbiOp(EL2);
1702  tlbiOp.broadcast(tc);
1703  return;
1704  }
1705  // AArch64 TLB Invalidate All, EL3
1706  case MISCREG_TLBI_ALLE3:
1707  {
1708  assert64();
1709 
1710  TLBIALLEL tlbiOp(EL3, true);
1711  tlbiOp(tc);
1712  return;
1713  }
1714  // AArch64 TLB Invalidate All, EL3, Inner Shareable
1715  case MISCREG_TLBI_ALLE3IS:
1716  {
1717  assert64();
1718 
1719  TLBIALLEL tlbiOp(EL3, true);
1720  tlbiOp.broadcast(tc);
1721  return;
1722  }
1723  // AArch64 TLB Invalidate All, EL2
1724  case MISCREG_TLBI_ALLE2:
1725  {
1726  assert64();
1727  scr = readMiscReg(MISCREG_SCR);
1728 
1729  TLBIALLEL tlbiOp(EL2, haveSecurity && !scr.ns);
1730  tlbiOp(tc);
1731  return;
1732  }
1733  // AArch64 TLB Invalidate All, EL2, Inner Shareable
1734  case MISCREG_TLBI_ALLE2IS:
1735  {
1736  assert64();
1737  scr = readMiscReg(MISCREG_SCR);
1738 
1739  TLBIALLEL tlbiOp(EL2, haveSecurity && !scr.ns);
1740  tlbiOp.broadcast(tc);
1741  return;
1742  }
1743  // AArch64 TLB Invalidate All, EL1
1744  case MISCREG_TLBI_ALLE1:
1745  {
1746  assert64();
1747  scr = readMiscReg(MISCREG_SCR);
1748 
1749  TLBIALLEL tlbiOp(EL1, haveSecurity && !scr.ns);
1750  tlbiOp(tc);
1751  return;
1752  }
1753  // AArch64 TLB Invalidate All, EL1, Inner Shareable
1754  case MISCREG_TLBI_ALLE1IS:
1755  {
1756  assert64();
1757  scr = readMiscReg(MISCREG_SCR);
1758 
1759  TLBIALLEL tlbiOp(EL1, haveSecurity && !scr.ns);
1760  tlbiOp.broadcast(tc);
1761  return;
1762  }
1763  case MISCREG_TLBI_VMALLS12E1:
1764  {
1765  assert64();
1766  scr = readMiscReg(MISCREG_SCR);
1767 
1768  TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
1769  tlbiOp(tc);
1770  return;
1771  }
1772  case MISCREG_TLBI_VMALLE1:
1773  {
1774  assert64();
1775  scr = readMiscReg(MISCREG_SCR);
1776 
1777  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1778  bool is_host = (hcr.tge && hcr.e2h);
1779  ExceptionLevel target_el = is_host ? EL2 : EL1;
1780  TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns, false);
1781  tlbiOp(tc);
1782  return;
1783  }
1784  case MISCREG_TLBI_VMALLS12E1IS:
1785  {
1786  assert64();
1787  scr = readMiscReg(MISCREG_SCR);
1788 
1789  TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
1790  tlbiOp.broadcast(tc);
1791  return;
1792  }
1793  case MISCREG_TLBI_VMALLE1IS:
1794  {
1795  assert64();
1796  scr = readMiscReg(MISCREG_SCR);
1797 
1798  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1799  bool is_host = (hcr.tge && hcr.e2h);
1800  ExceptionLevel target_el = is_host ? EL2 : EL1;
1801  TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns, false);
1802  tlbiOp.broadcast(tc);
1803  return;
1804  }
1805  // VAEx(IS) and VALEx(IS) are the same because TLBs
1806  // only store entries
1807  // from the last level of translation table walks
1808  // AArch64 TLB Invalidate by VA, EL3
1809  case MISCREG_TLBI_VAE3_Xt:
1810  case MISCREG_TLBI_VALE3_Xt:
1811  {
1812  assert64();
1813 
1814  TLBIMVA tlbiOp(EL3, true,
1815  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1816  0xbeef);
1817  tlbiOp(tc);
1818  return;
1819  }
1820  // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1821  case MISCREG_TLBI_VAE3IS_Xt:
1822  case MISCREG_TLBI_VALE3IS_Xt:
1823  {
1824  assert64();
1825 
1826  TLBIMVA tlbiOp(EL3, true,
1827  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1828  0xbeef);
1829 
1830  tlbiOp.broadcast(tc);
1831  return;
1832  }
1833  // AArch64 TLB Invalidate by VA, EL2
1834  case MISCREG_TLBI_VAE2_Xt:
1835  case MISCREG_TLBI_VALE2_Xt:
1836  {
1837  assert64();
1838  scr = readMiscReg(MISCREG_SCR);
1839 
1840  TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1841  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1842  0xbeef);
1843  tlbiOp(tc);
1844  return;
1845  }
1846  // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1847  case MISCREG_TLBI_VAE2IS_Xt:
1848  case MISCREG_TLBI_VALE2IS_Xt:
1849  {
1850  assert64();
1851  scr = readMiscReg(MISCREG_SCR);
1852 
1853  TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1854  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1855  0xbeef);
1856 
1857  tlbiOp.broadcast(tc);
1858  return;
1859  }
1860  // AArch64 TLB Invalidate by VA, EL1
1861  case MISCREG_TLBI_VAE1_Xt:
1862  case MISCREG_TLBI_VALE1_Xt:
1863  {
1864  assert64();
1865  scr = readMiscReg(MISCREG_SCR);
1866  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1867  bits(newVal, 55, 48);
1868 
1869  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1870  bool is_host = (hcr.tge && hcr.e2h);
1871  ExceptionLevel target_el = is_host ? EL2 : EL1;
1872  TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
1873  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1874  asid);
1875 
1876  tlbiOp(tc);
1877  return;
1878  }
1879  // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1880  case MISCREG_TLBI_VAE1IS_Xt:
1881  case MISCREG_TLBI_VALE1IS_Xt:
1882  {
1883  assert64();
1884  scr = readMiscReg(MISCREG_SCR);
1885  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1886  bits(newVal, 55, 48);
1887 
1888  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1889  bool is_host = (hcr.tge && hcr.e2h);
1890  ExceptionLevel target_el = is_host ? EL2 : EL1;
1891  TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
1892  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1893  asid);
1894 
1895  tlbiOp.broadcast(tc);
1896  return;
1897  }
1898  // AArch64 TLB Invalidate by ASID, EL1
1899  case MISCREG_TLBI_ASIDE1_Xt:
1900  {
1901  assert64();
1902  scr = readMiscReg(MISCREG_SCR);
1903  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1904  bits(newVal, 55, 48);
1905 
1906  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1907  bool is_host = (hcr.tge && hcr.e2h);
1908  ExceptionLevel target_el = is_host ? EL2 : EL1;
1909  TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
1910  tlbiOp(tc);
1911  return;
1912  }
1913  // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1914  case MISCREG_TLBI_ASIDE1IS_Xt:
1915  {
1916  assert64();
1917  scr = readMiscReg(MISCREG_SCR);
1918  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1919  bits(newVal, 55, 48);
1920 
1921  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1922  bool is_host = (hcr.tge && hcr.e2h);
1923  ExceptionLevel target_el = is_host ? EL2 : EL1;
1924  TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
1925  tlbiOp.broadcast(tc);
1926  return;
1927  }
1928  // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1929  // entries from the last level of translation table walks
1930  // AArch64 TLB Invalidate by VA, All ASID, EL1
1931  case MISCREG_TLBI_VAAE1_Xt:
1932  case MISCREG_TLBI_VAALE1_Xt:
1933  {
1934  assert64();
1935  scr = readMiscReg(MISCREG_SCR);
1936 
1937  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1938  bool is_host = (hcr.tge && hcr.e2h);
1939  ExceptionLevel target_el = is_host ? EL2 : EL1;
1940  TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
1941  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1942 
1943  tlbiOp(tc);
1944  return;
1945  }
1946  // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1947  case MISCREG_TLBI_VAAE1IS_Xt:
1948  case MISCREG_TLBI_VAALE1IS_Xt:
1949  {
1950  assert64();
1951  scr = readMiscReg(MISCREG_SCR);
1952 
1953  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1954  bool is_host = (hcr.tge && hcr.e2h);
1955  ExceptionLevel target_el = is_host ? EL2 : EL1;
1956  TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
1957  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1958 
1959  tlbiOp.broadcast(tc);
1960  return;
1961  }
1962  // AArch64 TLB Invalidate by Intermediate Physical Address,
1963  // Stage 2, EL1
1964  case MISCREG_TLBI_IPAS2E1_Xt:
1965  case MISCREG_TLBI_IPAS2LE1_Xt:
1966  {
1967  assert64();
1968  scr = readMiscReg(MISCREG_SCR);
1969 
1970  TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1971  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1972 
1973  tlbiOp(tc);
1974  return;
1975  }
1976  // AArch64 TLB Invalidate by Intermediate Physical Address,
1977  // Stage 2, EL1, Inner Shareable
1978  case MISCREG_TLBI_IPAS2E1IS_Xt:
1979  case MISCREG_TLBI_IPAS2LE1IS_Xt:
1980  {
1981  assert64();
1982  scr = readMiscReg(MISCREG_SCR);
1983 
1984  TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1985  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1986 
1987  tlbiOp.broadcast(tc);
1988  return;
1989  }
1990  case MISCREG_ACTLR:
1991  warn("Not doing anything for write of miscreg ACTLR\n");
1992  break;
1993 
1994  case MISCREG_PMXEVTYPER_PMCCFILTR:
1995  case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1996  case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1997  case MISCREG_PMCR ... MISCREG_PMOVSSET:
1998  pmu->setMiscReg(misc_reg, newVal);
1999  break;
2000 
2001 
2002  case MISCREG_HSTR: // TJDBX, now redifined to be RES0
2003  {
2004  HSTR hstrMask = 0;
2005  hstrMask.tjdbx = 1;
2006  newVal &= ~((uint32_t) hstrMask);
2007  break;
2008  }
2009  case MISCREG_HCPTR:
2010  {
2011  // If a CP bit in NSACR is 0 then the corresponding bit in
2012  // HCPTR is RAO/WI. Same applies to NSASEDIS
2013  secure_lookup = haveSecurity && isSecure(tc);
2014  if (!secure_lookup) {
2015  RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
2016  RegVal mask =
2017  (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
2018  newVal = (newVal & ~mask) | (oldValue & mask);
2019  }
2020  break;
2021  }
2022  case MISCREG_HDFAR: // alias for secure DFAR
2023  misc_reg = MISCREG_DFAR_S;
2024  break;
2025  case MISCREG_HIFAR: // alias for secure IFAR
2026  misc_reg = MISCREG_IFAR_S;
2027  break;
2028  case MISCREG_ATS1CPR:
2029  addressTranslation(TLB::S1CTran, BaseTLB::Read, 0, val);
2030  return;
2031  case MISCREG_ATS1CPW:
2032  addressTranslation(TLB::S1CTran, BaseTLB::Write, 0, val);
2033  return;
2034  case MISCREG_ATS1CUR:
2035  addressTranslation(TLB::S1CTran, BaseTLB::Read,
2036  TLB::UserMode, val);
2037  return;
2038  case MISCREG_ATS1CUW:
2039  addressTranslation(TLB::S1CTran, BaseTLB::Write,
2040  TLB::UserMode, val);
2041  return;
2042  case MISCREG_ATS12NSOPR:
2043  if (!haveSecurity)
2044  panic("Security Extensions required for ATS12NSOPR");
2045  addressTranslation(TLB::S1S2NsTran, BaseTLB::Read, 0, val);
2046  return;
2047  case MISCREG_ATS12NSOPW:
2048  if (!haveSecurity)
2049  panic("Security Extensions required for ATS12NSOPW");
2050  addressTranslation(TLB::S1S2NsTran, BaseTLB::Write, 0, val);
2051  return;
2052  case MISCREG_ATS12NSOUR:
2053  if (!haveSecurity)
2054  panic("Security Extensions required for ATS12NSOUR");
2055  addressTranslation(TLB::S1S2NsTran, BaseTLB::Read,
2056  TLB::UserMode, val);
2057  return;
2058  case MISCREG_ATS12NSOUW:
2059  if (!haveSecurity)
2060  panic("Security Extensions required for ATS12NSOUW");
2061  addressTranslation(TLB::S1S2NsTran, BaseTLB::Write,
2062  TLB::UserMode, val);
2063  return;
2064  case MISCREG_ATS1HR:
2065  addressTranslation(TLB::HypMode, BaseTLB::Read, 0, val);
2066  return;
2067  case MISCREG_ATS1HW:
2068  addressTranslation(TLB::HypMode, BaseTLB::Write, 0, val);
2069  return;
2070  case MISCREG_TTBCR:
2071  {
2072  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2073  const uint32_t ones = (uint32_t)(-1);
2074  TTBCR ttbcrMask = 0;
2075  TTBCR ttbcrNew = newVal;
2076 
2077  // ARM DDI 0406C.b, ARMv7-32
2078  ttbcrMask.n = ones; // T0SZ
2079  if (haveSecurity) {
2080  ttbcrMask.pd0 = ones;
2081  ttbcrMask.pd1 = ones;
2082  }
2083  ttbcrMask.epd0 = ones;
2084  ttbcrMask.irgn0 = ones;
2085  ttbcrMask.orgn0 = ones;
2086  ttbcrMask.sh0 = ones;
2087  ttbcrMask.ps = ones; // T1SZ
2088  ttbcrMask.a1 = ones;
2089  ttbcrMask.epd1 = ones;
2090  ttbcrMask.irgn1 = ones;
2091  ttbcrMask.orgn1 = ones;
2092  ttbcrMask.sh1 = ones;
2093  if (haveLPAE)
2094  ttbcrMask.eae = ones;
2095 
2096  if (haveLPAE && ttbcrNew.eae) {
2097  newVal = newVal & ttbcrMask;
2098  } else {
2099  newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
2100  }
2101  // Invalidate TLB MiscReg
2102  getMMUPtr(tc)->invalidateMiscReg();
2103  break;
2104  }
2105  case MISCREG_TTBR0:
2106  case MISCREG_TTBR1:
2107  {
2108  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2109  if (haveLPAE) {
2110  if (ttbcr.eae) {
2111  // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
2112  // ARMv8 AArch32 bit 63-56 only
2113  uint64_t ttbrMask = mask(63,56) | mask(47,40);
2114  newVal = (newVal & (~ttbrMask));
2115  }
2116  }
2117  // Invalidate TLB MiscReg
2118  getMMUPtr(tc)->invalidateMiscReg();
2119  break;
2120  }
2121  case MISCREG_SCTLR_EL1:
2122  case MISCREG_CONTEXTIDR:
2123  case MISCREG_PRRR:
2124  case MISCREG_NMRR:
2125  case MISCREG_MAIR0:
2126  case MISCREG_MAIR1:
2127  case MISCREG_DACR:
2128  case MISCREG_VTTBR:
2129  case MISCREG_SCR_EL3:
2130  case MISCREG_TCR_EL1:
2131  case MISCREG_TCR_EL2:
2132  case MISCREG_TCR_EL3:
2133  case MISCREG_SCTLR_EL2:
2134  case MISCREG_SCTLR_EL3:
2135  case MISCREG_HSCTLR:
2136  case MISCREG_TTBR0_EL1:
2137  case MISCREG_TTBR1_EL1:
2138  case MISCREG_TTBR0_EL2:
2139  case MISCREG_TTBR1_EL2:
2140  case MISCREG_TTBR0_EL3:
2141  getMMUPtr(tc)->invalidateMiscReg();
2142  break;
2143  case MISCREG_HCR_EL2:
2144  {
2145  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
2146  selfDebug->setenableTDETGE((HCR)val, mdcr);
2147  getMMUPtr(tc)->invalidateMiscReg();
2148  }
2149  break;
2150  case MISCREG_NZCV:
2151  {
2152  CPSR cpsr = val;
2153 
2154  tc->setCCReg(CCREG_NZ, cpsr.nz);
2155  tc->setCCReg(CCREG_C, cpsr.c);
2156  tc->setCCReg(CCREG_V, cpsr.v);
2157  }
2158  break;
2159  case MISCREG_DAIF:
2160  {
2161  CPSR cpsr = miscRegs[MISCREG_CPSR];
2162  cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
2163  newVal = cpsr;
2164  misc_reg = MISCREG_CPSR;
2165  }
2166  break;
2167  case MISCREG_SP_EL0:
2168  tc->setIntReg(INTREG_SP0, newVal);
2169  break;
2170  case MISCREG_SP_EL1:
2171  tc->setIntReg(INTREG_SP1, newVal);
2172  break;
2173  case MISCREG_SP_EL2:
2174  tc->setIntReg(INTREG_SP2, newVal);
2175  break;
2176  case MISCREG_SPSEL:
2177  {
2178  CPSR cpsr = miscRegs[MISCREG_CPSR];
2179  cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
2180  newVal = cpsr;
2181  misc_reg = MISCREG_CPSR;
2182  }
2183  break;
2184  case MISCREG_CURRENTEL:
2185  {
2186  CPSR cpsr = miscRegs[MISCREG_CPSR];
2187  cpsr.el = (uint8_t) ((CPSR) newVal).el;
2188  newVal = cpsr;
2189  misc_reg = MISCREG_CPSR;
2190  }
2191  break;
2192  case MISCREG_PAN:
2193  {
2194  // PAN is affecting data accesses
2195  getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
2196 
2197  CPSR cpsr = miscRegs[MISCREG_CPSR];
2198  cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
2199  newVal = cpsr;
2200  misc_reg = MISCREG_CPSR;
2201  }
2202  break;
2203  case MISCREG_AT_S1E1R_Xt:
2204  addressTranslation64(TLB::S1E1Tran, BaseTLB::Read, 0, val);
2205  return;
2206  case MISCREG_AT_S1E1W_Xt:
2207  addressTranslation64(TLB::S1E1Tran, BaseTLB::Write, 0, val);
2208  return;
2209  case MISCREG_AT_S1E0R_Xt:
2210  addressTranslation64(TLB::S1E0Tran, BaseTLB::Read,
2211  TLB::UserMode, val);
2212  return;
2213  case MISCREG_AT_S1E0W_Xt:
2214  addressTranslation64(TLB::S1E0Tran, BaseTLB::Write,
2215  TLB::UserMode, val);
2216  return;
2217  case MISCREG_AT_S1E2R_Xt:
2218  addressTranslation64(TLB::S1E2Tran, BaseTLB::Read, 0, val);
2219  return;
2220  case MISCREG_AT_S1E2W_Xt:
2221  addressTranslation64(TLB::S1E2Tran, BaseTLB::Write, 0, val);
2222  return;
2223  case MISCREG_AT_S12E1R_Xt:
2224  addressTranslation64(TLB::S12E1Tran, BaseTLB::Read, 0, val);
2225  return;
2226  case MISCREG_AT_S12E1W_Xt:
2227  addressTranslation64(TLB::S12E1Tran, BaseTLB::Write, 0, val);
2228  return;
2229  case MISCREG_AT_S12E0R_Xt:
2230  addressTranslation64(TLB::S12E0Tran, BaseTLB::Read,
2231  TLB::UserMode, val);
2232  return;
2233  case MISCREG_AT_S12E0W_Xt:
2234  addressTranslation64(TLB::S12E0Tran, BaseTLB::Write,
2235  TLB::UserMode, val);
2236  return;
2237  case MISCREG_AT_S1E3R_Xt:
2238  addressTranslation64(TLB::S1E3Tran, BaseTLB::Read, 0, val);
2239  return;
2240  case MISCREG_AT_S1E3W_Xt:
2241  addressTranslation64(TLB::S1E3Tran, BaseTLB::Write, 0, val);
2242  return;
2243  case MISCREG_SPSR_EL3:
2244  case MISCREG_SPSR_EL2:
2245  case MISCREG_SPSR_EL1:
2246  {
2247  RegVal spsr_mask = havePAN ?
2248  ~(0x2 << 22) : ~(0x3 << 22);
2249 
2250  newVal = val & spsr_mask;
2251  break;
2252  }
2253  case MISCREG_L2CTLR:
2254  warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
2255  miscRegName[misc_reg], uint32_t(val));
2256  break;
2257 
2258  // Generic Timer registers
2259  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
2260  case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
2261  getGenericTimer().setMiscReg(misc_reg, newVal);
2262  break;
2263  case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
2264  case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
2265  case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
2266  getGICv3CPUInterface().setMiscReg(misc_reg, newVal);
2267  return;
2268  case MISCREG_ZCR_EL3:
2269  case MISCREG_ZCR_EL2:
2270  case MISCREG_ZCR_EL1:
2271  tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
2272  break;
2273  }
2274  }
2275  setMiscRegNoEffect(misc_reg, newVal);
2276 }
2277 
2278 BaseISADevice &
2279 ISA::getGenericTimer()
2280 {
2281  // We only need to create an ISA interface the first time we try
2282  // to access the timer.
2283  if (timer)
2284  return *timer.get();
2285 
2286  assert(system);
2287  GenericTimer *generic_timer(system->getGenericTimer());
2288  if (!generic_timer) {
2289  panic("Trying to get a generic timer from a system that hasn't "
2290  "been configured to use a generic timer.\n");
2291  }
2292 
2293  timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2294  timer->setThreadContext(tc);
2295 
2296  return *timer.get();
2297 }
2298 
2299 BaseISADevice &
2300 ISA::getGICv3CPUInterface()
2301 {
2302  panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
2303  return *gicv3CpuInterface.get();
2304 }
2305 
2306 unsigned
2307 ISA::getCurSveVecLenInBits() const
2308 {
2309  if (!FullSystem) {
2310  return sveVL * 128;
2311  }
2312 
2313  panic_if(!tc,
2314  "A ThreadContext is needed to determine the SVE vector length "
2315  "in full-system mode");
2316 
2317  CPSR cpsr = miscRegs[MISCREG_CPSR];
2318  ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
2319 
2320  unsigned len = 0;
2321 
2322  if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
2323  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len;
2324  }
2325 
2326  if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
2327  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
2328  } else if (haveVirtualization && !isSecure(tc) &&
2329  (el == EL0 || el == EL1)) {
2330  len = std::min(
2331  len,
2332  static_cast<unsigned>(
2333  static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len));
2334  }
2335 
2336  if (el == EL3) {
2337  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
2338  } else if (haveSecurity) {
2339  len = std::min(
2340  len,
2341  static_cast<unsigned>(
2342  static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len));
2343  }
2344 
2345  len = std::min(len, sveVL - 1);
2346 
2347  return (len + 1) * 128;
2348 }
2349 
2350 void
2351 ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
2352 {
2353  auto vv = vc.as<uint64_t>();
2354  for (int i = 2; i < eCount; ++i) {
2355  vv[i] = 0;
2356  }
2357 }
2358 
2359 void
2360 ISA::serialize(CheckpointOut &cp) const
2361 {
2362  DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
2363  SERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
2364 }
2365 
2366 void
2367 ISA::unserialize(CheckpointIn &cp)
2368 {
2369  DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
2370  UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
2371  CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
2372  updateRegMap(tmp_cpsr);
2373 }
2374 
2375 void
2376 ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
2377  BaseTLB::Mode mode, Request::Flags flags, RegVal val)
2378 {
2379  // If we're in timing mode then doing the translation in
2380  // functional mode then we're slightly distorting performance
2381  // results obtained from simulations. The translation should be
2382  // done in the same mode the core is running in. NOTE: This
2383  // can't be an atomic translation because that causes problems
2384  // with unexpected atomic snoop requests.
2385  warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2386 
2387  auto req = std::make_shared<Request>(
2388  val, 0, flags, Request::funcRequestorId,
2389  tc->pcState().pc(), tc->contextId());
2390 
2391  Fault fault = getMMUPtr(tc)->translateFunctional(
2392  req, tc, mode, tran_type);
2393 
2394  PAR par = 0;
2395  if (fault == NoFault) {
2396  Addr paddr = req->getPaddr();
2397  uint64_t attr = getMMUPtr(tc)->getAttr();
2398  uint64_t attr1 = attr >> 56;
2399  if (!attr1 || attr1 ==0x44) {
2400  attr |= 0x100;
2401  attr &= ~ uint64_t(0x80);
2402  }
2403  par = (paddr & mask(47, 12)) | attr;
2404  DPRINTF(MiscRegs,
2405  "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2406  val, par);
2407  } else {
2408  ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2409  arm_fault->update(tc);
2410  // Set fault bit and FSR
2411  FSR fsr = arm_fault->getFsr(tc);
2412 
2413  par.f = 1; // F bit
2414  par.fst = fsr.status; // FST
2415  par.ptw = (arm_fault->iss() >> 7) & 0x1; // S1PTW
2416  par.s = arm_fault->isStage2() ? 1 : 0; // S
2417 
2418  DPRINTF(MiscRegs,
2419  "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2420  val, fsr, par);
2421  }
2422  setMiscRegNoEffect(MISCREG_PAR_EL1, par);
2423  return;
2424 }
2425 
2426 void
2427 ISA::addressTranslation(TLB::ArmTranslationType tran_type,
2428  BaseTLB::Mode mode, Request::Flags flags, RegVal val)
2429 {
2430  // If we're in timing mode then doing the translation in
2431  // functional mode then we're slightly distorting performance
2432  // results obtained from simulations. The translation should be
2433  // done in the same mode the core is running in. NOTE: This
2434  // can't be an atomic translation because that causes problems
2435  // with unexpected atomic snoop requests.
2436  warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2437 
2438  auto req = std::make_shared<Request>(
2439  val, 0, flags, Request::funcRequestorId,
2440  tc->pcState().pc(), tc->contextId());
2441 
2442  Fault fault = getMMUPtr(tc)->translateFunctional(
2443  req, tc, mode, tran_type);
2444 
2445  PAR par = 0;
2446  if (fault == NoFault) {
2447  Addr paddr = req->getPaddr();
2448  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2449  HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
2450 
2451  uint8_t max_paddr_bit = 0;
2452  if (haveLPAE && (ttbcr.eae || tran_type & TLB::HypMode ||
2453  ((tran_type & TLB::S1S2NsTran) && hcr.vm) )) {
2454 
2455  max_paddr_bit = 39;
2456  } else {
2457  max_paddr_bit = 31;
2458  }
2459 
2460  par = (paddr & mask(max_paddr_bit, 12)) |
2461  (getMMUPtr(tc)->getAttr());
2462 
2463  DPRINTF(MiscRegs,
2464  "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
2465  val, par);
2466  } else {
2467  ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2468  arm_fault->update(tc);
2469  // Set fault bit and FSR
2470  FSR fsr = arm_fault->getFsr(tc);
2471 
2472  par.f = 0x1; // F bit
2473  par.lpae = fsr.lpae;
2474  par.ptw = (arm_fault->iss() >> 7) & 0x1;
2475  par.s = arm_fault->isStage2() ? 1 : 0;
2476 
2477  if (par.lpae) {
2478  // LPAE - rearange fault status
2479  par.fst = fsr.status;
2480  } else {
2481  // VMSA - rearange fault status
2482  par.fs4_0 = fsr.fsLow | (fsr.fsHigh << 5);
2483  par.fs5 = fsr.ext;
2484  }
2485  DPRINTF(MiscRegs,
2486  "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
2487  val, fsr, par);
2488  }
2489  setMiscRegNoEffect(MISCREG_PAR, par);
2490  return;
2491 }
2492 
2493 ISA::MiscRegLUTEntryInitializer::chain
2494 ISA::MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
2495 {
2496  switch (FullSystem ? sys->highestEL() : EL1) {
2497  case EL0:
2498  case EL1: priv(); break;
2499  case EL2: hyp(); break;
2500  case EL3: mon(); break;
2501  }
2502  return *this;
2503 }
2504 
2505 } // namespace ArmISA
ArmISA::ISA::setupThreadContext
void setupThreadContext()
Definition: isa.cc:457
ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: miscregs.hh:317
ArmISA::SelfDebug
Definition: self_debug.hh:273
ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition: miscregs.hh:672
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gic_v3_cpu_interface.hh
ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: miscregs.hh:473
ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition: miscregs.hh:92
ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: miscregs.hh:183
ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: miscregs.hh:818
ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:337
GenericTimerISA
Definition: generic_timer.hh:388
ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition: miscregs.hh:878
ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: miscregs.hh:686
ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: miscregs.hh:562
ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition: miscregs.hh:304
ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1351
ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition: miscregs.hh:673
ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition: miscregs.hh:127
ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition: miscregs.hh:389
ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition: miscregs.hh:315
ArmISA::ISA::getMiscIndices
std::pair< int, int > getMiscIndices(int misc_reg) const
Definition: isa.hh:830
ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:642
ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: miscregs.hh:320
ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: miscregs.hh:472
insertBits
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:143
ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: miscregs.cc:3397
warn
#define warn(...)
Definition: logging.hh:239
ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: miscregs.hh:564
SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:162
ArmISA::MISCREG_IMPLEMENTED
@ MISCREG_IMPLEMENTED
Definition: miscregs.hh:1096
ArmISA::SelfDebug::init
void init(ThreadContext *tc)
Definition: self_debug.cc:329
ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: miscregs.hh:506
ArmISA::EL2
@ EL2
Definition: types.hh:624
ArmISA::ISA::clear
void clear()
Definition: isa.cc:126
ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: miscregs.hh:1052
ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: miscregs.hh:509
ArmISA::TLB::UserMode
@ UserMode
Definition: tlb.hh:124
ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: miscregs.hh:247
system.hh
ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: miscregs.hh:250
ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition: miscregs.hh:132
ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: miscregs.hh:571
ArmISA::CCREG_NZ
@ CCREG_NZ
Definition: ccregs.hh:45
BaseTLB::Read
@ Read
Definition: tlb.hh:57
ArmISA::ISA::haveVHE
bool haveVHE
Definition: isa.hh:98
ArmISA::daif
Bitfield< 9, 6 > daif
Definition: miscregs_types.hh:66
ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition: miscregs.hh:338
ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: miscregs.hh:786
ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: miscregs.hh:150
ArmSystem::haveCrypto
bool haveCrypto() const
Returns true if this system implements the Crypto Extension.
Definition: system.hh:173
ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: miscregs.hh:524
ArmSystem::physAddrRange
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:252
ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: miscregs.hh:511
ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: miscregs.hh:502
ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: miscregs.hh:679
ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:58
ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: miscregs.hh:225
ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition: miscregs.cc:1346
ArmISA::TLB::ArmTranslationType
ArmTranslationType
Definition: tlb.hh:127
ArmISA::ArmFault::iss
virtual uint32_t iss() const =0
ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:202
ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition: miscregs.hh:651
ArmISA::ISA::miscRegs
RegVal miscRegs[NumMiscRegs]
Definition: isa.hh:457
ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:217
ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: miscregs.hh:513
warn_once
#define warn_once(...)
Definition: logging.hh:243
ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition: miscregs.hh:1050
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: miscregs.hh:563
ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: miscregs.hh:574
ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: miscregs.hh:749
ArmISA::ISA::haveLPAE
bool haveLPAE
Definition: isa.hh:91
Loader::Arm
@ Arm
Definition: object_file.hh:52
ArmISA::EL0
@ EL0
Definition: types.hh:622
ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: miscregs.hh:333
ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: miscregs.hh:516
ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: miscregs.hh:257
ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: miscregs.hh:677
ArmISA::MODE_EL3H
@ MODE_EL3H
Definition: types.hh:635
ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: miscregs.hh:324
Flags< FlagsType >
ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: miscregs.hh:485
ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: miscregs.hh:504
ArmISA::SelfDebug::setMDBGen
void setMDBGen(RegVal val)
Definition: self_debug.hh:387
ArmISA::ISA::gicv3CpuInterface
std::unique_ptr< BaseISADevice > gicv3CpuInterface
Definition: isa.hh:86
ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: miscregs.hh:211
ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: miscregs.hh:198
ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: miscregs.hh:517
ArmISA::BaseISADevice::setThreadContext
virtual void setThreadContext(ThreadContext *tc)
Definition: isa_device.hh:65
ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition: miscregs.hh:614
ArmISA::ISA::clear32
void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
Definition: isa.cc:218
ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition: miscregs.hh:300
ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: miscregs.hh:618
ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: miscregs.hh:195
ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: miscregs.hh:593
ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition: miscregs.hh:881
ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition: miscregs.hh:215
ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: miscregs.hh:616
ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: miscregs.hh:330
ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: miscregs.hh:213
ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition: miscregs.hh:572
ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: miscregs.hh:318
ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: miscregs.hh:680
BaseTLB::Mode
Mode
Definition: tlb.hh:57
ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: miscregs.hh:224
ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: miscregs.hh:206
ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: miscregs.hh:475
ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: miscregs.hh:699
ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition: miscregs.hh:702
ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition: miscregs.hh:833
ArmISA::SelfDebug::updateDBGWCR
void updateDBGWCR(int index, DBGWCR val)
Definition: self_debug.hh:411
ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: miscregs.hh:721
ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: miscregs.hh:237
ArmISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:833
ArmISA::TLB::HypMode
@ HypMode
Definition: tlb.hh:130
ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition: miscregs.hh:372
ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition: miscregs.hh:703
ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition: miscregs.hh:69
ArmISA::TLBIMVA
TLB Invalidate by VA.
Definition: tlbi_op.hh:241
ArmISA::HTMCheckpoint
Definition: htm.hh:54
ArmISA::CCREG_V
@ CCREG_V
Definition: ccregs.hh:47
ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: miscregs.hh:592
ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: miscregs.hh:676
ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition: miscregs.hh:77
ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: miscregs.hh:99
ArmSystem::haveSVE
bool haveSVE() const
Returns true if SVE is implemented (ARMv8)
Definition: system.hh:229
ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: miscregs.hh:687
CheckerCPU
CheckerCPU class.
Definition: cpu.hh:85
ArmISA::DTLBIALL
Data TLB Invalidate All.
Definition: tlbi_op.hh:113
ArmISA::TLBIVMALL
Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions.
Definition: tlbi_op.hh:145
ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: miscregs.hh:658
ArmISA::MISCREG_FPSCR_EXC
@ MISCREG_FPSCR_EXC
Definition: miscregs.hh:76
ArmISA::ArmFault::isStage2
virtual bool isStage2() const
Definition: faults.hh:249
ArmISA::getMMUPtr
MMU * getMMUPtr(T *tc)
Definition: mmu.hh:113
ArmISA::TLBIOp::broadcast
void broadcast(ThreadContext *tc)
Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
Definition: tlbi_op.hh:69
std::vector
STL vector class.
Definition: stl.hh:37
ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: miscregs.hh:514
ArmISA::ISA::redirectRegVHE
int redirectRegVHE(ThreadContext *tc, int misc_reg)
Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at ...
Definition: isa.hh:753
GenericTimer
Definition: generic_timer.hh:286
ArmISA::EL3
@ EL3
Definition: types.hh:625
ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition: miscregs.hh:126
ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: miscregs.hh:735
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:204
ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: miscregs.hh:332
ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: miscregs.hh:219
ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition: miscregs.hh:392
ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: miscregs.hh:600
ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: miscregs.hh:212
ArmISA::TLB::S1S2NsTran
@ S1S2NsTran
Definition: tlb.hh:133
SERIALIZE_MAPPING
#define SERIALIZE_MAPPING(member, names, size)
Definition: serialize.hh:707
ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: miscregs.hh:223
ArmSystem::getGIC
BaseGic * getGIC() const
Get a pointer to the system's GIC.
Definition: system.hh:195
ArmSystem::getGenericTimer
GenericTimer * getGenericTimer() const
Get a pointer to the system's generic timer model.
Definition: system.hh:192
ArmISA::Interrupts
Definition: interrupts.hh:69
system.hh
ThreadContext::setHtmCheckpointPtr
virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0
ArmISA::TLBIASID
TLB Invalidate by ASID match.
Definition: tlbi_op.hh:167
ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition: miscregs.hh:1047
ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: miscregs.cc:1362
ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: miscregs.hh:1054
ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: miscregs.hh:515
ArmISA::miscRegName
const char *const miscRegName[]
Definition: miscregs.hh:1167
ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: miscregs.hh:656
faults.hh
ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: miscregs.hh:286
ArmISA::ISA::sveVL
unsigned sveVL
SVE vector length in quadwords.
Definition: isa.hh:104
ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: miscregs.hh:88
ArmISA
Definition: ccregs.hh:41
ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition: miscregs.hh:129
ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: miscregs.hh:691
ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: miscregs.hh:606
ArmISA::ISA::haveSecEL2
bool haveSecEL2
Definition: isa.hh:100
ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: miscregs.hh:671
ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition: miscregs.hh:205
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:88
ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:168
ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: miscregs.hh:322
ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition: miscregs.hh:130
ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition: miscregs.hh:302
ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition: miscregs.hh:164
ArmISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:485
ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition: miscregs.hh:336
ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: miscregs.hh:230
ArmISA::ISA::zeroSveVecRegUpperPart
static void zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
Definition: isa.cc:2351
ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: miscregs.hh:409
ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: miscregs.hh:484
ArmISA::ISA::takeOverFrom
void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override
Definition: isa.cc:478
ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: miscregs.hh:565
ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: miscregs.hh:507
ArmISA::ISA::assert32
void assert32()
Definition: isa.hh:502
ThreadContext::threadId
virtual int threadId() const =0
ArmISA::ISA::system
ArmSystem * system
Definition: isa.hh:70
ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: miscregs.hh:329
ArmISA::ISA::addressTranslation
void addressTranslation(TLB::ArmTranslationType tran_type, BaseTLB::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2427
ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: miscregs.hh:561
iGbReg::TxdOp::ic
bool ic(TxDesc *d)
Definition: i8254xGBe_defs.hh:250
ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition: miscregs.hh:131
ArmISA::ISA::timer
std::unique_ptr< BaseISADevice > timer
Definition: isa.hh:83
ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition: miscregs.hh:241
VecRegContainer::as
VecRegT< VecElem, NumElems, true > as() const
View interposers.
Definition: vec_reg.hh:386
ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition: miscregs.hh:339
ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: miscregs.hh:560
ArmISA::ISA::_vecRegRenameMode
const Enums::VecRegRenameMode _vecRegRenameMode
Definition: isa.hh:74
ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: miscregs.hh:668
ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition: miscregs.hh:366
SimObject::startup
virtual void startup()
startup() is the final initialization call before simulation.
Definition: sim_object.cc:93
ArmISA::ISA::haveLargeAsid64
bool haveLargeAsid64
Definition: isa.hh:94
ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: miscregs.hh:471
ArmISA::ISA::haveLSE
bool haveLSE
Definition: isa.hh:97
ArmISA::MISCREG_AMAIR0
@ MISCREG_AMAIR0
Definition: miscregs.hh:377
ArmISA::CCREG_C
@ CCREG_C
Definition: ccregs.hh:46
ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition: miscregs.hh:346
ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: miscregs.hh:470
mmu.hh
X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition: miscregs.hh:133
ArmISA::SelfDebug::setDebugMask
void setDebugMask(bool mask)
Definition: self_debug.hh:417
ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition: miscregs.hh:281
ArmISA::TLB::S1CTran
@ S1CTran
Definition: tlb.hh:129
ArmISA::ISA::assert64
void assert64()
Definition: isa.hh:503
htm.hh
ArmISA::ISA::haveTME
bool haveTME
Definition: isa.hh:101
ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition: miscregs.hh:155
ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition: miscregs.hh:525
ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: miscregs.hh:214
ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: miscregs.hh:661
ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition: miscregs.hh:701
ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:328
ArmISA::MISCREG_PAR
@ MISCREG_PAR
Definition: miscregs.hh:290
ArmISA::TLB::S12E0Tran
@ S12E0Tran
Definition: tlb.hh:142
ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: miscregs.hh:395
cp
Definition: cprintf.cc:37
ArmISA::BaseISADevice::setMiscReg
virtual void setMiscReg(int misc_reg, RegVal val)=0
Write to a system register belonging to this device.
ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: miscregs.hh:207
ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: miscregs.hh:390
ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition: miscregs.hh:955
ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: miscregs.hh:202
ArmISA::SelfDebug::setbSDD
void setbSDD(RegVal val)
Definition: self_debug.hh:373
ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: miscregs.hh:557
ArmISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:2360
interrupts.hh
ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition: miscregs.hh:284
ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: miscregs.hh:327
ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:159
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
ArmISA::MISCREG_SCTLR_RST
@ MISCREG_SCTLR_RST
Definition: miscregs.hh:87
ArmISA::ISA::haveSVE
bool haveSVE
Definition: isa.hh:96
ArmISA::MODE_EL1H
@ MODE_EL1H
Definition: types.hh:631
ArmISA::ISA::dummyDevice
DummyISADevice dummyDevice
Dummy device for to handle non-existing ISA devices.
Definition: isa.hh:77
ArmSystem::haveLPAE
bool haveLPAE() const
Returns true if this system implements the Large Physical Address Extension.
Definition: system.hh:163
ArmISA::MISCREG_AMAIR1
@ MISCREG_AMAIR1
Definition: miscregs.hh:380
ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: miscregs.hh:505
ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition: miscregs.hh:341
ArmSystem::haveLSE
bool haveLSE() const
Returns true if LSE is implemented (ARMv8.1)
Definition: system.hh:235
ArmISA::ArmFault
Definition: faults.hh:60
ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition: miscregs.hh:156
ArmISA::TLB::S1E2Tran
@ S1E2Tran
Definition: tlb.hh:140
ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: miscregs.hh:451
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:237
ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: miscregs.hh:244
ThreadContext::pcStateNoRecord
virtual void pcStateNoRecord(const TheISA::PCState &val)=0
ArmSystem::havePAN
bool havePAN() const
Returns true if Priviledge Access Never is implemented.
Definition: system.hh:241
ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition: miscregs.hh:303
ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: miscregs.hh:675
ArmISA::ISA::haveCrypto
bool haveCrypto
Definition: isa.hh:93
BaseISA::tc
ThreadContext * tc
Definition: isa.hh:52
ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:621
ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: miscregs.hh:362
ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: miscregs.hh:204
ArmISA::SelfDebug::setMDSCRvals
void setMDSCRvals(RegVal val)
Definition: self_debug.hh:379
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:246
ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition: miscregs.hh:162
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: miscregs.hh:670
ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: miscregs.hh:540
ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: miscregs.hh:566
isa.hh
ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: miscregs.hh:667
ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: miscregs.hh:657
MipsISA::r
r
Definition: pra_constants.hh:95
cpu.hh
ArmISA::FpscrExcMask
static const uint32_t FpscrExcMask
Definition: miscregs.hh:2208
ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition: miscregs.hh:612
ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: miscregs.hh:217
ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: miscregs.hh:597
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: miscregs.hh:220
ArmISA::el
Bitfield< 3, 2 > el
Definition: miscregs_types.hh:69
ArmISA::ISA::getGICv3CPUInterface
BaseISADevice & getGICv3CPUInterface()
Definition: isa.cc:2300
ArmISA::TLB::S1E0Tran
@ S1E0Tran
Definition: tlb.hh:138
ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition: miscregs.hh:734
ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition: miscregs.hh:363
ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition: miscregs.hh:337
ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: miscregs.hh:256
ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: miscregs.hh:264
ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: miscregs.hh:559
ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition: miscregs.hh:152
ArmISA::attr
attr
Definition: miscregs_types.hh:649
ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: miscregs.hh:479
ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: miscregs.hh:692
ArmSystem::sveVL
unsigned sveVL() const
Returns the SVE vector length at reset, in quadwords.
Definition: system.hh:232
ArmSystem::haveSecEL2
bool haveSecEL2() const
Returns true if Priviledge Access Never is implemented.
Definition: system.hh:244
tlbi_op.hh
System::Threads::size
int size() const
Definition: system.hh:204
ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition: miscregs.hh:233
ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition: miscregs.hh:120
ThreadContext::contextId
virtual ContextID contextId() const =0
ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: miscregs.hh:334
ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: miscregs.hh:683
ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: miscregs.hh:234
ArmISA::ISA::selfDebug
SelfDebug * selfDebug
Definition: isa.hh:114
ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: miscregs.hh:599
ArmISA::INTREG_SP0
@ INTREG_SP0
Definition: intregs.hh:118
mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:100
ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: miscregs.hh:674
ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition: miscregs.hh:344
Gicv3
Definition: gic_v3.hh:53
ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: miscregs.hh:784
ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition: miscregs.hh:307
ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: miscregs.hh:261
ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition: miscregs.hh:232
ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: miscregs.hh:696
ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: miscregs.hh:508
ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition: miscregs.hh:306
ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: miscregs.hh:481
ArmISA::TLBIMVAA
TLB Invalidate by VA, All ASID.
Definition: tlbi_op.hh:226
ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition: miscregs.hh:159
ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition: miscregs.hh:605
ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: miscregs.hh:512
faults.hh
ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: miscregs.hh:323
generic_timer.hh
ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: miscregs.hh:319
ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition: miscregs.hh:245
ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition: miscregs.hh:160
ArmISA::ISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition: isa.cc:2494
ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: miscregs.hh:582
ArmISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:811
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition: miscregs.hh:700
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:251
ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: miscregs.hh:595
ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition: miscregs.hh:91
ArmISA::sp
Bitfield< 0 > sp
Definition: miscregs_types.hh:71
ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition: miscregs.hh:630
ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: miscregs.hh:267
ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: miscregs.hh:328
ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition: miscregs.hh:71
ArmISA::EL1
@ EL1
Definition: types.hh:623
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:148
ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition: miscregs.hh:739
ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition: miscregs.hh:305
ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition: miscregs.hh:342
ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition: miscregs.hh:1099
ArmISA::ISA::clear64
void clear64(const ArmISAParams &p)
Definition: isa.cc:270
ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: miscregs.hh:242
ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:174
ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: miscregs.hh:331
ArmISA::SelfDebug::updateOSLock
void updateOSLock(RegVal val)
Definition: self_debug.hh:399
ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition: miscregs.hh:153
ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: miscregs.hh:203
Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:252
ArmISA::ISA::afterStartup
bool afterStartup
Definition: isa.hh:112
ArmISA::ISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition: isa.hh:323
ArmISA::ISA::updateRegMap
void updateRegMap(CPSR cpsr)
Definition: isa.hh:461
ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: miscregs.hh:655
ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: miscregs.hh:68
ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: miscregs.hh:483
ArmISA::TLBIALL
TLB Invalidate All.
Definition: tlbi_op.hh:80
ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: miscregs.hh:1051
ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: miscregs.hh:371
ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition: miscregs.hh:125
ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition: miscregs.hh:705
ArmISA::ISA::initID32
void initID32(const ArmISAParams &p)
Definition: isa.cc:319
ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: miscregs.hh:623
ArmISA::ISA::getGenericTimer
BaseISADevice & getGenericTimer()
Definition: isa.cc:2279
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
ArmISA::CpsrMaskQ
static const uint32_t CpsrMaskQ
Definition: miscregs.hh:2187
ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: miscregs.hh:253
ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: miscregs.hh:1089
ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: miscregs.hh:698
ArmISA::asid
asid
Definition: miscregs_types.hh:611
ArmISA::ISA::haveVirtualization
bool haveVirtualization
Definition: isa.hh:92
ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
ArmISA::MMU::getAttr
uint64_t getAttr() const
Definition: mmu.hh:105
BaseTLB::Write
@ Write
Definition: tlb.hh:57
ArmISA::ISA::MiscRegLUTEntryInitializer::chain
const typedef MiscRegLUTEntryInitializer & chain
Definition: isa.hh:144
ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: miscregs.hh:365
ArmISA::DTLBIMVA
Data TLB Invalidate by VA.
Definition: tlbi_op.hh:272
ArmSystem
Definition: system.hh:59
ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: miscregs.hh:477
ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: miscregs.hh:681
ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition: miscregs.hh:345
ArmISA::ITLBIALL
Instruction TLB Invalidate All.
Definition: tlbi_op.hh:100
ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: miscregs.hh:589
ArmISA::ISA::haveSecurity
bool haveSecurity
Definition: isa.hh:90
ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: miscregs.hh:209
ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: miscregs.hh:584
stat_control.hh
ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition: miscregs.hh:163
ArmISA::MMU::D_TLBS
@ D_TLBS
Definition: mmu.hh:67
ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: miscregs.hh:613
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
System::threads
Threads threads
Definition: system.hh:304
ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: miscregs.hh:374
ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition: miscregs.hh:238
ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: miscregs.hh:184
ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: miscregs.hh:57
ArmISA::TLB::S1E1Tran
@ S1E1Tran
Definition: tlb.hh:139
ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: miscregs.hh:678
ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition: miscregs.hh:222
ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: miscregs.hh:474
ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: miscregs.hh:617
ArmISA::ISA::physAddrRange
uint8_t physAddrRange
Definition: isa.hh:95
ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: miscregs.hh:666
ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition: miscregs.hh:128
ThreadContext::setCCReg
virtual void setCCReg(RegIndex reg_idx, RegVal val)=0
base.hh
ArmISA::ArmFault::update
void update(ThreadContext *tc)
Definition: faults.cc:436
ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition: miscregs.hh:165
ArmISA::ISA::pmu
BaseISADevice * pmu
Definition: isa.hh:80
ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: miscregs.hh:688
ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: miscregs.hh:690
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: miscregs.hh:583
ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: miscregs.hh:210
ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition: miscregs.hh:704
Gicv3::getCPUInterface
Gicv3CPUInterface * getCPUInterface(int cpu_id) const
Definition: gic_v3.hh:132
ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition: miscregs.hh:343
ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: miscregs.hh:321
ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:206
ArmISA::pan
Bitfield< 22 > pan
Definition: miscregs_types.hh:55
ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition: miscregs.hh:123
ArmISA::ArmFault::getFsr
virtual FSR getFsr(ThreadContext *tc) const
Definition: faults.hh:250
ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: miscregs.hh:1092
ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: miscregs.hh:218
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: miscregs.hh:86
ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition: miscregs.hh:910
ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: miscregs.hh:685
ArmISA::len
Bitfield< 18, 16 > len
Definition: miscregs_types.hh:439
ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
ArmISA::MiscRegIndex
MiscRegIndex
Definition: miscregs.hh:56
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: miscregs.hh:248
ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition: miscregs.hh:535
ArmISA::ISA::initID64
void initID64(const ArmISAParams &p)
Definition: isa.cc:357
ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition: miscregs.hh:229
ArmISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:2367
ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition: miscregs.hh:154
ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: miscregs.hh:216
ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: miscregs.hh:536
ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: miscregs.hh:326
ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: miscregs.hh:325
ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: miscregs.hh:510
ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: miscregs.hh:476
ArmISA::TLBIALLEL
Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions.
Definition: tlbi_op.hh:126
ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: miscregs.hh:208
ArmISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:63
ArmISA::TLBIIPA
TLB Invalidate by Intermediate Physical Address.
Definition: tlbi_op.hh:286
pmu.hh
ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition: miscregs.hh:67
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:64
ThreadContext::getDecoderPtr
virtual TheISA::Decoder * getDecoderPtr()=0
bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:73
ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition: miscregs.hh:737
ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: miscregs.hh:693
ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: miscregs.hh:368
ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:640
ArmISA::FpscrQcMask
static const uint32_t FpscrQcMask
Definition: miscregs.hh:2204
ArmISA::ISA::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: isa.cc:440
ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition: miscregs.hh:161
ArmISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:509
ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: miscregs.hh:285
ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition: miscregs.hh:121
ArmISA::SelfDebug::updateDBGBCR
void updateDBGBCR(int index, DBGBCR val)
Definition: self_debug.hh:405
ArmISA::ISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition: isa.hh:361
ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition: miscregs.hh:124
ArmISA::ISA::addressTranslation64
void addressTranslation64(TLB::ArmTranslationType tran_type, BaseTLB::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2376
ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: miscregs.hh:816
ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: miscregs.hh:231
ArmISA::ISA::getCurSveVecLenInBits
unsigned getCurSveVecLenInBits() const
Definition: isa.cc:2307
SimObject::params
const Params & params() const
Definition: sim_object.hh:168
ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: miscregs.hh:669
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
self_debug.hh
ArmISA::TLB::S1E3Tran
@ S1E3Tran
Definition: tlb.hh:141
ArmISA::NUM_PHYS_MISCREGS
@ NUM_PHYS_MISCREGS
Definition: miscregs.hh:1061
ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: miscregs.hh:697
ArmISA::DTLBIASID
Data TLB Invalidate by ASID match.
Definition: tlbi_op.hh:196
ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition: miscregs.hh:615
ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: miscregs.hh:578
ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition: miscregs.hh:122
ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: miscregs.hh:482
System::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: system.hh:302
ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:636
ArmISA::ITLBIASID
Instruction TLB Invalidate by ASID match.
Definition: tlbi_op.hh:183
ArmISA::ISA::MiscRegLUTEntryInitializer::priv
chain priv(bool v=true) const
Definition: isa.hh:247
ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition: miscregs.hh:797
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition: miscregs.hh:201
ArmISA::INTREG_SP1
@ INTREG_SP1
Definition: intregs.hh:119
ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: miscregs.hh:628
ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: miscregs.hh:587
ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition: miscregs.hh:157
ArmISA::MMU::translateFunctional
bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr)
Definition: mmu.cc:44
ArmSystem::haveTME
bool haveTME() const
Returns true if this system implements the transactional memory extension (ARMv9)
Definition: system.hh:226
CheckpointIn
Definition: serialize.hh:68
ArmISA::ISA::havePAN
bool havePAN
Definition: isa.hh:99
ArmISA::SelfDebug::setenableTDETGE
void setenableTDETGE(HCR hcr, HDCR mdcr)
Definition: self_debug.hh:393
ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition: miscregs.hh:151
ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: miscregs.hh:695
ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: miscregs.hh:197
ArmISA::BaseISADevice::setISA
virtual void setISA(ISA *isa)
Definition: isa_device.cc:51
ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition: miscregs.hh:335
ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: miscregs.hh:694
ArmISA::NumMiscRegs
const int NumMiscRegs
Definition: registers.hh:77
ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: miscregs.hh:239
ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: miscregs.hh:246
ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: miscregs.hh:478
UNSERIALIZE_MAPPING
#define UNSERIALIZE_MAPPING(member, names, size)
Definition: serialize.hh:713
ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: miscregs.hh:684
ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: miscregs.hh:480
ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: miscregs.hh:429
ArmISA::TLB::S12E1Tran
@ S12E1Tran
Definition: tlb.hh:143
ArmISA::MODE_EL2H
@ MODE_EL2H
Definition: types.hh:633
BaseISA
Definition: isa.hh:47
ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: miscregs.hh:591
ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: miscregs.hh:621
ArmISA::miscRegInfo
std::bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: miscregs.cc:3394
BaseCPU::getInterruptController
BaseInterrupts * getInterruptController(ThreadID tid)
Definition: base.hh:236
ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: miscregs.hh:580
ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: miscregs.hh:558
ArmSystem::haveVHE
bool haveVHE() const
Returns true if Virtualization Host Extensions is implemented.
Definition: system.hh:238
ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition: miscregs.hh:340
gic_v3.hh
ArmISA::ISA::highestELIs64
bool highestELIs64
Definition: isa.hh:89
ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: miscregs.hh:503
ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition: miscregs.hh:444
ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition: miscregs.hh:316
ArmISA::ITLBIMVA
Instruction TLB Invalidate by VA.
Definition: tlbi_op.hh:258
ArmISA::v
Bitfield< 28 > v
Definition: miscregs_types.hh:51
ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition: miscregs.hh:118
ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition: miscregs.hh:75
ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition: miscregs.hh:119
ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: miscregs.hh:226
ULL
#define ULL(N)
uint64_t constant
Definition: types.hh:46
ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: miscregs.hh:689
RegVal
uint64_t RegVal
Definition: types.hh:174
ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: miscregs.hh:347
ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: miscregs.hh:221
VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:156
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: miscregs.hh:575
ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:112
ArmISA::ISA::lookUpMiscReg
static std::vector< struct MiscRegLUTEntry > lookUpMiscReg
Metadata table accessible via the value of the register.
Definition: isa.hh:139
ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition: miscregs.hh:158
ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
ArmSystem::haveLargeAsid64
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:221
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
ArmISA::TLBIALLN
TLB Invalidate All, Non-Secure.
Definition: tlbi_op.hh:209
ArmISA::MMU::invalidateMiscReg
void invalidateMiscReg(TLBType type=ALL_TLBS)
Definition: mmu.cc:60
ArmISA::BaseISADevice::readMiscReg
virtual RegVal readMiscReg(int misc_reg)=0
Read a system register belonging to this device.
ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: miscregs.hh:682
ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: miscregs.hh:706
ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition: miscregs.hh:70
ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition: miscregs.hh:301
ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: miscregs.hh:608
ArmISA::INTREG_SP2
@ INTREG_SP2
Definition: intregs.hh:120
Generated on Tue Mar 23 2021 19:41:18 for gem5 by doxygen 1.8.17