gem5
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arch
arm
fastmodel
iris
mmu.hh
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/*
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* Copyright (c) 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ARM_FASTMODEL_IRIS_MMU_HH__
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#define __ARCH_ARM_FASTMODEL_IRIS_MMU_HH__
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#include "
arch/arm/page_size.hh
"
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#include "
arch/generic/mmu.hh
"
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#include "params/IrisMMU.hh"
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namespace
gem5
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{
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namespace
Iris
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{
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class
MMU
:
public
BaseMMU
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{
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public
:
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MMU
(
const
Params
&
p
) :
BaseMMU
(
p
) {}
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TranslationGenPtr
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translateFunctional
(
Addr
start,
Addr
size,
ThreadContext
*tc,
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Mode
mode
,
Request::Flags
flags
)
override
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{
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return
TranslationGenPtr
(
new
MMUTranslationGen
(
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ArmISA::PageBytes
, start, size, tc,
this
,
mode
,
flags
));
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}
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};
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}
// namespace Iris
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}
// namespace gem5
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#endif
// __ARCH_ARM_FASTMODEL_IRIS_MMU_HH__
page_size.hh
gem5::BaseMMU::MMUTranslationGen
Definition
mmu.hh:127
gem5::BaseMMU
Definition
mmu.hh:54
gem5::BaseMMU::Params
BaseMMUParams Params
Definition
mmu.hh:88
gem5::BaseMMU::Mode
Mode
Definition
mmu.hh:56
gem5::Flags< FlagsType >
gem5::Iris::MMU
Definition
mmu.hh:53
gem5::Iris::MMU::translateFunctional
TranslationGenPtr translateFunctional(Addr start, Addr size, ThreadContext *tc, Mode mode, Request::Flags flags) override
Definition
mmu.hh:58
gem5::Iris::MMU::MMU
MMU(const Params &p)
Definition
mmu.hh:55
gem5::Iris::ThreadContext
Definition
thread_context.hh:55
mmu.hh
flags
uint8_t flags
Definition
helpers.cc:87
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition
misc_types.hh:74
gem5::ArmISA::PageBytes
const Addr PageBytes
Definition
page_size.hh:53
gem5::MipsISA::p
Bitfield< 0 > p
Definition
pra_constants.hh:326
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition
types.hh:147
gem5::TranslationGenPtr
std::unique_ptr< TranslationGen > TranslationGenPtr
Definition
translation_gen.hh:131
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