gem5  v22.0.0.2
cpu.cc
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27 
29 
31 #include "scx/scx.h"
32 #include "sim/serialize.hh"
33 
34 namespace gem5
35 {
36 
37 namespace Iris
38 {
39 
40 BaseCPU::BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs) :
41  gem5::BaseCPU::BaseCPU(params), evs(_evs),
42  evs_base_cpu(dynamic_cast<Iris::BaseCpuEvs *>(_evs))
43 {
44  panic_if(!evs_base_cpu, "EVS should be of type BaseCpuEvs");
45 
46  // Make sure fast model knows we're using debugging mechanisms to control
47  // the simulation, and it shouldn't shut down if simulation time stops
48  // for some reason. Despite the misleading name, this doesn't start a CADI
49  // server because it's first parameter is false.
50  scx::scx_start_cadi_server(false, false, true);
51 }
52 
54 {
55  for (auto &tc: threadContexts)
56  delete tc;
57  threadContexts.clear();
58 }
59 
60 Counter
62 {
63  Counter count = 0;
64  for (auto *tc: threadContexts)
65  count += tc->getCurrentInstCount();
66  return count;
67 }
68 
69 void
71 {
72  gem5::serialize(*threadContexts[tid], cp);
73 }
74 
75 } // namespace Iris
76 } // namespace gem5
gem5::Iris::BaseCPU::~BaseCPU
virtual ~BaseCPU()
Definition: cpu.cc:53
serialize.hh
sc_core::sc_module
Definition: sc_module.hh:101
gem5::Iris::BaseCPU
Definition: cpu.hh:61
gem5::Iris::BaseCpuEvs
Definition: cpu.hh:47
cpu.hh
gem5::Iris::BaseCPU::evs_base_cpu
Iris::BaseCpuEvs * evs_base_cpu
Definition: cpu.hh:99
gem5::Iris::BaseCPU::BaseCPU
BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs)
Definition: cpu.cc:40
gem5::X86ISA::count
count
Definition: misc.hh:703
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:215
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
thread_context.hh
gem5::Iris::BaseCPU::totalInsts
Counter totalInsts() const override
Definition: cpu.cc:61
gem5::Iris::BaseCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Definition: cpu.cc:70
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235

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