gem5  v22.1.0.0
branch.hh
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40 
41 #ifndef __ARCH_ARM_INSTS_BRANCH_HH__
42 #define __ARCH_ARM_INSTS_BRANCH_HH__
43 
45 
46 namespace gem5
47 {
48 
49 namespace ArmISA
50 {
51 // Branch to a target computed with an immediate
52 class BranchImm : public PredOp
53 {
54  protected:
55  int32_t imm;
56 
57  public:
58  BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
59  int32_t _imm) :
60  PredOp(mnem, _machInst, __opClass), imm(_imm)
61  {}
62 
63  std::string generateDisassembly(
64  Addr pc, const loader::SymbolTable *symtab) const override;
65 };
66 
67 // Conditionally Branch to a target computed with an immediate
68 class BranchImmCond : public BranchImm
69 {
70  public:
71  BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
72  int32_t _imm, ConditionCode _condCode) :
73  BranchImm(mnem, _machInst, __opClass, _imm)
74  {
75  // Only update if this isn't part of an IT block
76  if (!machInst.itstateMask)
77  condCode = _condCode;
78  }
79 };
80 
81 // Branch to a target computed with a register
82 class BranchReg : public PredOp
83 {
84  protected:
86 
87  public:
88  BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
89  RegIndex _op1) :
90  PredOp(mnem, _machInst, __opClass), op1(_op1)
91  {}
92 
93  std::string generateDisassembly(
94  Addr pc, const loader::SymbolTable *symtab) const override;
95 };
96 
97 // Conditionally Branch to a target computed with a register
98 class BranchRegCond : public BranchReg
99 {
100  public:
101  BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
102  RegIndex _op1, ConditionCode _condCode) :
103  BranchReg(mnem, _machInst, __opClass, _op1)
104  {
105  // Only update if this isn't part of an IT block
106  if (!machInst.itstateMask)
107  condCode = _condCode;
108  }
109 };
110 
111 // Branch to a target computed with two registers
112 class BranchRegReg : public PredOp
113 {
114  protected:
117 
118  public:
119  BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
120  RegIndex _op1, RegIndex _op2) :
121  PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2)
122  {}
123 
124  std::string generateDisassembly(
125  Addr pc, const loader::SymbolTable *symtab) const override;
126 };
127 
128 // Branch to a target computed with an immediate and a register
129 class BranchImmReg : public PredOp
130 {
131  protected:
132  int32_t imm;
134 
135  public:
136  BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
137  int32_t _imm, RegIndex _op1) :
138  PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
139  {}
140 };
141 
142 } // namespace ArmISA
143 } // namespace gem5
144 
145 #endif //__ARCH_ARM_INSTS_BRANCH_HH__
BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int32_t _imm, ConditionCode _condCode)
Definition: branch.hh:71
BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int32_t _imm, RegIndex _op1)
Definition: branch.hh:136
BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int32_t _imm)
Definition: branch.hh:58
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:58
BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _op1, ConditionCode _condCode)
Definition: branch.hh:101
BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _op1, RegIndex _op2)
Definition: branch.hh:119
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:68
BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _op1)
Definition: branch.hh:88
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:48
Base class for predicated integer operations.
Definition: pred_inst.hh:217
ConditionCode condCode
Definition: pred_inst.hh:220
ConditionCode
Definition: cc.hh:92
Bitfield< 4 > pc
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint16_t RegIndex
Definition: types.hh:176
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147

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