branch.hh

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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
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 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2007-2008 The Florida State University
 * All rights reserved.
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#ifndef __ARCH_ARM_INSTS_BRANCH_HH__
#define __ARCH_ARM_INSTS_BRANCH_HH__
 
#include "arch/arm/insts/pred_inst.hh"
 
namespace gem5
{
 
namespace ArmISA
{
// Branch to a target computed with an immediate
class BranchImm : public PredOp
{
  protected:
    int32_t imm;
 
  public:
    BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
              int32_t _imm) :
        PredOp(mnem, _machInst, __opClass), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
// Conditionally Branch to a target computed with an immediate
class BranchImmCond : public BranchImm
{
  public:
    BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                  int32_t _imm, ConditionCode _condCode) :
        BranchImm(mnem, _machInst, __opClass, _imm)
    {
        // Only update if this isn't part of an IT block
        if (!machInst.itstateMask)
            condCode = _condCode;
    }
};
 
// Branch to a target computed with a register
class BranchReg : public PredOp
{
  protected:
    RegIndex op1;
 
  public:
    BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
              RegIndex _op1) :
        PredOp(mnem, _machInst, __opClass), op1(_op1)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
// Conditionally Branch to a target computed with a register
class BranchRegCond : public BranchReg
{
  public:
    BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                  RegIndex _op1, ConditionCode _condCode) :
        BranchReg(mnem, _machInst, __opClass, _op1)
    {
        // Only update if this isn't part of an IT block
        if (!machInst.itstateMask)
            condCode = _condCode;
    }
};
 
// Branch to a target computed with two registers
class BranchRegReg : public PredOp
{
  protected:
    RegIndex op1;
    RegIndex op2;
 
  public:
    BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                 RegIndex _op1, RegIndex _op2) :
        PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
// Branch to a target computed with an immediate and a register
class BranchImmReg : public PredOp
{
  protected:
    int32_t imm;
    RegIndex op1;
 
  public:
    BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                 int32_t _imm, RegIndex _op1) :
        PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
    {}
};
 
} // namespace ArmISA
} // namespace gem5
 
#endif //__ARCH_ARM_INSTS_BRANCH_HH__