gem5  v21.1.0.2
branch.hh
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40 
41 #ifndef __ARCH_ARM_INSTS_BRANCH_HH__
42 #define __ARCH_ARM_INSTS_BRANCH_HH__
43 
45 
46 namespace gem5
47 {
48 
49 namespace ArmISA
50 {
51 // Branch to a target computed with an immediate
52 class BranchImm : public PredOp
53 {
54  protected:
55  int32_t imm;
56 
57  public:
58  BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
59  int32_t _imm) :
60  PredOp(mnem, _machInst, __opClass), imm(_imm)
61  {}
62 
63  std::string generateDisassembly(
64  Addr pc, const loader::SymbolTable *symtab) const override;
65 };
66 
67 // Conditionally Branch to a target computed with an immediate
68 class BranchImmCond : public BranchImm
69 {
70  public:
71  BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
72  int32_t _imm, ConditionCode _condCode) :
73  BranchImm(mnem, _machInst, __opClass, _imm)
74  {
75  // Only update if this isn't part of an IT block
76  if (!machInst.itstateMask)
77  condCode = _condCode;
78  }
79 };
80 
81 // Branch to a target computed with a register
82 class BranchReg : public PredOp
83 {
84  protected:
85  IntRegIndex op1;
86 
87  public:
88  BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
89  IntRegIndex _op1) :
90  PredOp(mnem, _machInst, __opClass), op1(_op1)
91  {}
92 
93  std::string generateDisassembly(
94  Addr pc, const loader::SymbolTable *symtab) const override;
95 };
96 
97 // Conditionally Branch to a target computed with a register
98 class BranchRegCond : public BranchReg
99 {
100  public:
101  BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
102  IntRegIndex _op1, ConditionCode _condCode) :
103  BranchReg(mnem, _machInst, __opClass, _op1)
104  {
105  // Only update if this isn't part of an IT block
106  if (!machInst.itstateMask)
107  condCode = _condCode;
108  }
109 };
110 
111 // Branch to a target computed with two registers
112 class BranchRegReg : public PredOp
113 {
114  protected:
115  IntRegIndex op1;
116  IntRegIndex op2;
117 
118  public:
119  BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
120  IntRegIndex _op1, IntRegIndex _op2) :
121  PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2)
122  {}
123 
124  std::string generateDisassembly(
125  Addr pc, const loader::SymbolTable *symtab) const override;
126 };
127 
128 // Branch to a target computed with an immediate and a register
129 class BranchImmReg : public PredOp
130 {
131  protected:
132  int32_t imm;
133  IntRegIndex op1;
134 
135  public:
136  BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
137  int32_t _imm, IntRegIndex _op1) :
138  PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
139  {}
140 };
141 
142 } // namespace ArmISA
143 } // namespace gem5
144 
145 #endif //__ARCH_ARM_INSTS_BRANCH_HH__
gem5::ArmISA::BranchRegReg::op2
IntRegIndex op2
Definition: branch.hh:116
gem5::ArmISA::BranchRegReg
Definition: branch.hh:112
gem5::ArmISA::BranchRegReg::BranchRegReg
BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2)
Definition: branch.hh:119
gem5::ArmISA::BranchRegReg::op1
IntRegIndex op1
Definition: branch.hh:115
gem5::ArmISA::PredOp::condCode
ConditionCode condCode
Definition: pred_inst.hh:218
gem5::ArmISA::BranchReg::op1
IntRegIndex op1
Definition: branch.hh:85
gem5::ArmISA::BranchImmReg::imm
int32_t imm
Definition: branch.hh:132
gem5::ArmISA::BranchReg
Definition: branch.hh:82
gem5::ArmISA::BranchImmReg::op1
IntRegIndex op1
Definition: branch.hh:133
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::BranchImmReg::BranchImmReg
BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int32_t _imm, IntRegIndex _op1)
Definition: branch.hh:136
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:149
gem5::ArmISA::BranchImm
Definition: branch.hh:52
gem5::ArmISA::BranchImmCond::BranchImmCond
BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int32_t _imm, ConditionCode _condCode)
Definition: branch.hh:71
gem5::ArmISA::BranchRegCond
Definition: branch.hh:98
gem5::ArmISA::BranchImmReg
Definition: branch.hh:129
gem5::ArmISA::BranchRegCond::BranchRegCond
BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1, ConditionCode _condCode)
Definition: branch.hh:101
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
pred_inst.hh
gem5::ArmISA::BranchReg::BranchReg
BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1)
Definition: branch.hh:88
gem5::ArmISA::BranchRegReg::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:68
gem5::ArmISA::BranchImm::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:58
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::BranchImmCond
Definition: branch.hh:68
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:67
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::BranchImm::imm
int32_t imm
Definition: branch.hh:55
gem5::ArmISA::PredOp
Base class for predicated integer operations.
Definition: pred_inst.hh:214
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::BranchImm::BranchImm
BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int32_t _imm)
Definition: branch.hh:58
gem5::ArmISA::BranchReg::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:48

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