gem5  v21.1.0.2
pseudo.hh
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40 
41 #ifndef __ARCH_ARM_INSTS_PSEUDO_HH__
42 #define __ARCH_ARM_INSTS_PSEUDO_HH__
43 
45 
46 namespace gem5
47 {
48 
50 {
51  protected:
53 
54  const char *faultName() const;
55 
56  public:
58 
60  Trace::InstRecord *traceData) const override;
61 
62  std::string generateDisassembly(
63  Addr pc, const loader::SymbolTable *symtab) const override;
64 };
65 
74 {
75  private:
78  std::string fullMnemonic;
79 
80  public:
81  FailUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst);
82  FailUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst,
83  const std::string& _fullMnemonic);
84 
86  Trace::InstRecord *traceData) const override;
87 
88  std::string generateDisassembly(
89  Addr pc, const loader::SymbolTable *symtab) const override;
90 };
91 
102 {
103  private:
105  mutable bool warned;
108  std::string fullMnemonic;
109 
110  public:
111  WarnUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst);
112  WarnUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst,
113  const std::string& _fullMnemonic);
114 
116  Trace::InstRecord *traceData) const override;
117 
118  std::string generateDisassembly(
119  Addr pc, const loader::SymbolTable *symtab) const override;
120 };
121 
130 {
131  public:
133 
135  Trace::InstRecord *traceData) const override;
136 };
137 
139 {
140  public:
141  DebugStep(ArmISA::ExtMachInst _machInst);
142 
144  Trace::InstRecord *traceData) const override;
145 };
146 
147 } // namespace gem5
148 
149 #endif
gem5::DebugStep
Definition: pseudo.hh:138
gem5::WarnUnimplemented::WarnUnimplemented
WarnUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst)
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::FailUnimplemented::fullMnemonic
std::string fullMnemonic
Full mnemonic for MRC and MCR instructions including the coproc.
Definition: pseudo.hh:78
gem5::WarnUnimplemented::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pseudo.cc:182
gem5::IllegalExecInst::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:194
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::FailUnimplemented::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pseudo.cc:140
gem5::DecoderFaultInst::faultId
ArmISA::DecoderFault faultId
Definition: pseudo.hh:52
gem5::FailUnimplemented::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:134
gem5::WarnUnimplemented::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:170
gem5::DebugStep::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:204
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:43
gem5::DecoderFaultInst::faultName
const char * faultName() const
Definition: pseudo.cc:88
gem5::DecoderFaultInst::DecoderFaultInst
DecoderFaultInst(ArmISA::ExtMachInst _machInst)
Definition: pseudo.cc:50
gem5::DecoderFaultInst
Definition: pseudo.hh:49
gem5::WarnUnimplemented::warned
bool warned
Have we warned on this instruction yet?
Definition: pseudo.hh:105
gem5::FailUnimplemented
Static instruction class for unimplemented instructions that cause simulator termination.
Definition: pseudo.hh:73
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::DecoderFault
DecoderFault
Instruction decoder fault codes in ExtMachInst.
Definition: types.hh:349
gem5::WarnUnimplemented
Base class for unimplemented instructions that cause a warning to be printed (but do not terminate si...
Definition: pseudo.hh:101
gem5::WarnUnimplemented::fullMnemonic
std::string fullMnemonic
Full mnemonic for MRC and MCR instructions including the coproc.
Definition: pseudo.hh:108
gem5::FailUnimplemented::FailUnimplemented
FailUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst)
gem5::DecoderFaultInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pseudo.cc:105
gem5::DecoderFaultInst::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:61
gem5::IllegalExecInst::IllegalExecInst
IllegalExecInst(ArmISA::ExtMachInst _machInst)
Definition: pseudo.cc:189
static_inst.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::IllegalExecInst
This class is modelling instructions which are not going to be executed since they are flagged as Ill...
Definition: pseudo.hh:129
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::DebugStep::DebugStep
DebugStep(ArmISA::ExtMachInst _machInst)
Definition: pseudo.cc:199

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