gem5 v24.0.0.0
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pseudo.cc
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1/*
2 * Copyright (c) 2014,2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
42
43#include "cpu/exec_context.hh"
44
45namespace gem5
46{
47
48using namespace ArmISA;
49
51 : ArmStaticInst("gem5decoderFault", _machInst, No_OpClass),
52 faultId(static_cast<DecoderFault>(
53 static_cast<uint8_t>(_machInst.decoderFault)))
54{
55 // Don't call execute() if we're on a speculative path and the
56 // fault is an internal panic fault.
57 flags[IsNonSpeculative] = (faultId == DecoderFault::PANIC);
58}
59
62{
63 const Addr pc = xc->pcState().instAddr();
64
65 switch (faultId) {
66 case DecoderFault::UNALIGNED:
67 if (machInst.aarch64) {
68 return std::make_shared<PCAlignmentFault>(pc);
69 } else {
70 // TODO: We should check if we the receiving end is in
71 // aarch64 mode and raise a PCAlignment fault instead.
72 return std::make_shared<PrefetchAbort>(
74 }
75
76 case DecoderFault::PANIC:
77 panic("Internal error in instruction decoder\n");
78
79 case DecoderFault::OK:
80 panic("Decoder fault instruction without decoder fault.\n");
81 }
82
83 panic("Unhandled fault type");
84}
85
86const char *
88{
89 switch (faultId) {
90 case DecoderFault::OK:
91 return "OK";
92
93 case DecoderFault::UNALIGNED:
94 return "UnalignedInstruction";
95
96 case DecoderFault::PANIC:
97 return "DecoderPanic";
98 }
99
100 panic("Unhandled fault type");
101}
102
103std::string
105 Addr pc, const loader::SymbolTable *symtab) const
106{
107 return csprintf("gem5fault %s", faultName());
108}
109
110
111
112FailUnimplemented::FailUnimplemented(const char *_mnemonic,
113 ExtMachInst _machInst)
114 : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
115{
116 // don't call execute() (which panics) if we're on a
117 // speculative path
118 flags[IsNonSpeculative] = true;
119 flags[IsInvalid] = true;
120}
121
122FailUnimplemented::FailUnimplemented(const char *_mnemonic,
123 ExtMachInst _machInst,
124 const std::string& _fullMnemonic)
125 : ArmStaticInst(_mnemonic, _machInst, No_OpClass),
126 fullMnemonic(_fullMnemonic)
127{
128 // don't call execute() (which panics) if we're on a
129 // speculative path
130 flags[IsNonSpeculative] = true;
131 flags[IsInvalid] = true;
132}
133
134Fault
136{
137 return std::make_shared<UndefinedInstruction>(machInst, false, mnemonic);
138}
139
140std::string
142 Addr pc, const loader::SymbolTable *symtab) const
143{
144 return csprintf("%-10s (unimplemented)",
145 fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
146}
147
148
149
150WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
151 ExtMachInst _machInst)
152 : ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
153{
154 // don't call execute() (which panics) if we're on a
155 // speculative path
156 flags[IsNonSpeculative] = true;
157}
158
159WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
160 ExtMachInst _machInst,
161 const std::string& _fullMnemonic)
162 : ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false),
163 fullMnemonic(_fullMnemonic)
164{
165 // don't call execute() (which panics) if we're on a
166 // speculative path
167 flags[IsNonSpeculative] = true;
168}
169
170Fault
172{
173 if (!warned) {
174 warn("\tinstruction '%s' unimplemented\n",
175 fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
176 warned = true;
177 }
178
179 return NoFault;
180}
181
182std::string
184 Addr pc, const loader::SymbolTable *symtab) const
185{
186 return csprintf("%-10s (unimplemented)",
187 fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
188}
189
191 : ArmStaticInst("Illegal Execution", _machInst, No_OpClass)
192{}
193
194Fault
196{
197 return std::make_shared<IllegalInstSetStateFault>();
198}
199
201 : ArmStaticInst("DebugStep", _machInst, No_OpClass)
202{ }
203
204Fault
206{
207 PCState pc_state = xc->pcState().as<PCState>();
208 pc_state.debugStep(false);
209 xc->pcState(pc_state);
210
212
213 bool ldx = sd->getSstep()->getLdx();
214
215 return std::make_shared<SoftwareStepFault>(machInst, ldx,
216 pc_state.stepped());
217}
218
219} // namespace gem5
SelfDebug * getSelfDebug() const
Definition isa.hh:181
DebugStep(ArmISA::ExtMachInst _machInst)
Definition pseudo.cc:200
Fault execute(ExecContext *xc, trace::InstRecord *traceData) const override
Definition pseudo.cc:205
DecoderFaultInst(ArmISA::ExtMachInst _machInst)
Definition pseudo.cc:50
Fault execute(ExecContext *xc, trace::InstRecord *traceData) const override
Definition pseudo.cc:61
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition pseudo.cc:104
const char * faultName() const
Definition pseudo.cc:87
ArmISA::DecoderFault faultId
Definition pseudo.hh:52
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
virtual const PCStateBase & pcState() const =0
std::string fullMnemonic
Full mnemonic for MRC and MCR instructions including the coproc.
Definition pseudo.hh:78
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition pseudo.cc:141
FailUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst)
Fault execute(ExecContext *xc, trace::InstRecord *traceData) const override
Definition pseudo.cc:135
Fault execute(ExecContext *xc, trace::InstRecord *traceData) const override
Definition pseudo.cc:195
IllegalExecInst(ArmISA::ExtMachInst _machInst)
Definition pseudo.cc:190
Target & as()
Definition pcstate.hh:73
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition pcstate.hh:108
const char * mnemonic
Base mnemonic (e.g., "add").
std::bitset< Num_Flags > flags
Flag values for this instruction.
std::string fullMnemonic
Full mnemonic for MRC and MCR instructions including the coproc.
Definition pseudo.hh:108
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition pseudo.cc:183
WarnUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst)
bool warned
Have we warned on this instruction yet?
Definition pseudo.hh:105
Fault execute(ExecContext *xc, trace::InstRecord *traceData) const override
Definition pseudo.cc:171
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
#define warn(...)
Definition logging.hh:256
DecoderFault
Instruction decoder fault codes in ExtMachInst.
Definition types.hh:367
Bitfield< 4 > sd
Bitfield< 4 > pc
uint64_t ExtMachInst
Definition types.hh:43
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
std::string csprintf(const char *format, const Args &...args)
Definition cprintf.hh:161
constexpr decltype(nullptr) NoFault
Definition types.hh:253

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