gem5  v21.1.0.2
pseudo.cc
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40 
41 #include "arch/arm/insts/pseudo.hh"
42 
43 #include "cpu/exec_context.hh"
44 
45 namespace gem5
46 {
47 
48 using namespace ArmISA;
49 
51  : ArmStaticInst("gem5decoderFault", _machInst, No_OpClass),
52  faultId(static_cast<DecoderFault>(
53  static_cast<uint8_t>(_machInst.decoderFault)))
54 {
55  // Don't call execute() if we're on a speculative path and the
56  // fault is an internal panic fault.
57  flags[IsNonSpeculative] = (faultId == DecoderFault::PANIC);
58 }
59 
60 Fault
62 {
63  const PCState pc_state(xc->pcState());
64  const Addr pc(pc_state.instAddr());
65 
66  switch (faultId) {
68  if (machInst.aarch64) {
69  return std::make_shared<PCAlignmentFault>(pc);
70  } else {
71  // TODO: We should check if we the receiving end is in
72  // aarch64 mode and raise a PCAlignment fault instead.
73  return std::make_shared<PrefetchAbort>(
75  }
76 
78  panic("Internal error in instruction decoder\n");
79 
80  case DecoderFault::OK:
81  panic("Decoder fault instruction without decoder fault.\n");
82  }
83 
84  panic("Unhandled fault type");
85 }
86 
87 const char *
89 {
90  switch (faultId) {
91  case DecoderFault::OK:
92  return "OK";
93 
95  return "UnalignedInstruction";
96 
98  return "DecoderPanic";
99  }
100 
101  panic("Unhandled fault type");
102 }
103 
104 std::string
106  Addr pc, const loader::SymbolTable *symtab) const
107 {
108  return csprintf("gem5fault %s", faultName());
109 }
110 
111 
112 
113 FailUnimplemented::FailUnimplemented(const char *_mnemonic,
114  ExtMachInst _machInst)
115  : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
116 {
117  // don't call execute() (which panics) if we're on a
118  // speculative path
119  flags[IsNonSpeculative] = true;
120 }
121 
122 FailUnimplemented::FailUnimplemented(const char *_mnemonic,
123  ExtMachInst _machInst,
124  const std::string& _fullMnemonic)
125  : ArmStaticInst(_mnemonic, _machInst, No_OpClass),
126  fullMnemonic(_fullMnemonic)
127 {
128  // don't call execute() (which panics) if we're on a
129  // speculative path
130  flags[IsNonSpeculative] = true;
131 }
132 
133 Fault
135 {
136  return std::make_shared<UndefinedInstruction>(machInst, false, mnemonic);
137 }
138 
139 std::string
141  Addr pc, const loader::SymbolTable *symtab) const
142 {
143  return csprintf("%-10s (unimplemented)",
144  fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
145 }
146 
147 
148 
149 WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
150  ExtMachInst _machInst)
151  : ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
152 {
153  // don't call execute() (which panics) if we're on a
154  // speculative path
155  flags[IsNonSpeculative] = true;
156 }
157 
158 WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
159  ExtMachInst _machInst,
160  const std::string& _fullMnemonic)
161  : ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false),
162  fullMnemonic(_fullMnemonic)
163 {
164  // don't call execute() (which panics) if we're on a
165  // speculative path
166  flags[IsNonSpeculative] = true;
167 }
168 
169 Fault
171 {
172  if (!warned) {
173  warn("\tinstruction '%s' unimplemented\n",
174  fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
175  warned = true;
176  }
177 
178  return NoFault;
179 }
180 
181 std::string
183  Addr pc, const loader::SymbolTable *symtab) const
184 {
185  return csprintf("%-10s (unimplemented)",
186  fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
187 }
188 
190  : ArmStaticInst("Illegal Execution", _machInst, No_OpClass)
191 {}
192 
193 Fault
195 {
196  return std::make_shared<IllegalInstSetStateFault>();
197 }
198 
200  : ArmStaticInst("DebugStep", _machInst, No_OpClass)
201 { }
202 
203 Fault
205 {
206  PCState pc_state(xc->pcState());
207  pc_state.debugStep(false);
208  xc->pcState(pc_state);
209 
211 
212  bool ldx = sd->getSstep()->getLdx();
213 
214  return std::make_shared<SoftwareStepFault>(machInst, ldx,
215  pc_state.stepped());
216 
217 }
218 
219 } // namespace gem5
gem5::WarnUnimplemented::WarnUnimplemented
WarnUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst)
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::UNALIGNED
@ UNALIGNED
Unaligned instruction fault.
Definition: types.hh:352
warn
#define warn(...)
Definition: logging.hh:245
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::FailUnimplemented::fullMnemonic
std::string fullMnemonic
Full mnemonic for MRC and MCR instructions including the coproc.
Definition: pseudo.hh:78
gem5::WarnUnimplemented::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pseudo.cc:182
gem5::IllegalExecInst::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:194
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::FailUnimplemented::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pseudo.cc:140
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::DecoderFaultInst::faultId
ArmISA::DecoderFault faultId
Definition: pseudo.hh:52
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::PANIC
@ PANIC
Internal gem5 error.
Definition: types.hh:354
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:149
gem5::FailUnimplemented::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:134
gem5::WarnUnimplemented::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:170
gem5::DebugStep::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:204
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:43
gem5::DecoderFaultInst::faultName
const char * faultName() const
Definition: pseudo.cc:88
gem5::ExecContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::DecoderFaultInst::DecoderFaultInst
DecoderFaultInst(ArmISA::ExtMachInst _machInst)
Definition: pseudo.cc:50
gem5::ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::WarnUnimplemented::warned
bool warned
Have we warned on this instruction yet?
Definition: pseudo.hh:105
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::DecoderFault
DecoderFault
Instruction decoder fault codes in ExtMachInst.
Definition: types.hh:349
gem5::WarnUnimplemented::fullMnemonic
std::string fullMnemonic
Full mnemonic for MRC and MCR instructions including the coproc.
Definition: pseudo.hh:108
gem5::FailUnimplemented::FailUnimplemented
FailUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst)
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::DecoderFaultInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pseudo.cc:105
gem5::ArmISA::ArmFault::AlignmentFault
@ AlignmentFault
Definition: faults.hh:97
gem5::ArmISA::OK
@ OK
No fault.
Definition: types.hh:351
pseudo.hh
gem5::DecoderFaultInst::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:61
gem5::IllegalExecInst::IllegalExecInst
IllegalExecInst(ArmISA::ExtMachInst _machInst)
Definition: pseudo.cc:189
gem5::ArmISA::ISA::getSelfDebug
SelfDebug * getSelfDebug() const
Definition: isa.hh:524
exec_context.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISA::sd
Bitfield< 4 > sd
Definition: misc_types.hh:774
gem5::GenericISA::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address the bytes of this instruction came from.
Definition: types.hh:73
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::decoderFault
decoderFault
Definition: types.hh:61
gem5::DebugStep::DebugStep
DebugStep(ArmISA::ExtMachInst _machInst)
Definition: pseudo.cc:199
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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