gem5  v21.2.1.1
pseudo.cc
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40 
41 #include "arch/arm/insts/pseudo.hh"
42 
43 #include "cpu/exec_context.hh"
44 
45 namespace gem5
46 {
47 
48 using namespace ArmISA;
49 
51  : ArmStaticInst("gem5decoderFault", _machInst, No_OpClass),
52  faultId(static_cast<DecoderFault>(
53  static_cast<uint8_t>(_machInst.decoderFault)))
54 {
55  // Don't call execute() if we're on a speculative path and the
56  // fault is an internal panic fault.
57  flags[IsNonSpeculative] = (faultId == DecoderFault::PANIC);
58 }
59 
60 Fault
62 {
63  const Addr pc = xc->pcState().instAddr();
64 
65  switch (faultId) {
67  if (machInst.aarch64) {
68  return std::make_shared<PCAlignmentFault>(pc);
69  } else {
70  // TODO: We should check if we the receiving end is in
71  // aarch64 mode and raise a PCAlignment fault instead.
72  return std::make_shared<PrefetchAbort>(
74  }
75 
77  panic("Internal error in instruction decoder\n");
78 
79  case DecoderFault::OK:
80  panic("Decoder fault instruction without decoder fault.\n");
81  }
82 
83  panic("Unhandled fault type");
84 }
85 
86 const char *
88 {
89  switch (faultId) {
90  case DecoderFault::OK:
91  return "OK";
92 
94  return "UnalignedInstruction";
95 
97  return "DecoderPanic";
98  }
99 
100  panic("Unhandled fault type");
101 }
102 
103 std::string
105  Addr pc, const loader::SymbolTable *symtab) const
106 {
107  return csprintf("gem5fault %s", faultName());
108 }
109 
110 
111 
112 FailUnimplemented::FailUnimplemented(const char *_mnemonic,
113  ExtMachInst _machInst)
114  : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
115 {
116  // don't call execute() (which panics) if we're on a
117  // speculative path
118  flags[IsNonSpeculative] = true;
119 }
120 
121 FailUnimplemented::FailUnimplemented(const char *_mnemonic,
122  ExtMachInst _machInst,
123  const std::string& _fullMnemonic)
124  : ArmStaticInst(_mnemonic, _machInst, No_OpClass),
125  fullMnemonic(_fullMnemonic)
126 {
127  // don't call execute() (which panics) if we're on a
128  // speculative path
129  flags[IsNonSpeculative] = true;
130 }
131 
132 Fault
134 {
135  return std::make_shared<UndefinedInstruction>(machInst, false, mnemonic);
136 }
137 
138 std::string
140  Addr pc, const loader::SymbolTable *symtab) const
141 {
142  return csprintf("%-10s (unimplemented)",
143  fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
144 }
145 
146 
147 
148 WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
149  ExtMachInst _machInst)
150  : ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
151 {
152  // don't call execute() (which panics) if we're on a
153  // speculative path
154  flags[IsNonSpeculative] = true;
155 }
156 
157 WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
158  ExtMachInst _machInst,
159  const std::string& _fullMnemonic)
160  : ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false),
161  fullMnemonic(_fullMnemonic)
162 {
163  // don't call execute() (which panics) if we're on a
164  // speculative path
165  flags[IsNonSpeculative] = true;
166 }
167 
168 Fault
170 {
171  if (!warned) {
172  warn("\tinstruction '%s' unimplemented\n",
173  fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
174  warned = true;
175  }
176 
177  return NoFault;
178 }
179 
180 std::string
182  Addr pc, const loader::SymbolTable *symtab) const
183 {
184  return csprintf("%-10s (unimplemented)",
185  fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
186 }
187 
189  : ArmStaticInst("Illegal Execution", _machInst, No_OpClass)
190 {}
191 
192 Fault
194 {
195  return std::make_shared<IllegalInstSetStateFault>();
196 }
197 
199  : ArmStaticInst("DebugStep", _machInst, No_OpClass)
200 { }
201 
202 Fault
204 {
205  PCState pc_state = xc->pcState().as<PCState>();
206  pc_state.debugStep(false);
207  xc->pcState(pc_state);
208 
210 
211  bool ldx = sd->getSstep()->getLdx();
212 
213  return std::make_shared<SoftwareStepFault>(machInst, ldx,
214  pc_state.stepped());
215 }
216 
217 } // namespace gem5
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::WarnUnimplemented::WarnUnimplemented
WarnUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst)
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::UNALIGNED
@ UNALIGNED
Unaligned instruction fault.
Definition: types.hh:352
warn
#define warn(...)
Definition: logging.hh:246
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:65
gem5::FailUnimplemented::fullMnemonic
std::string fullMnemonic
Full mnemonic for MRC and MCR instructions including the coproc.
Definition: pseudo.hh:78
gem5::WarnUnimplemented::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pseudo.cc:181
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::IllegalExecInst::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:193
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::FailUnimplemented::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pseudo.cc:139
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::DecoderFaultInst::faultId
ArmISA::DecoderFault faultId
Definition: pseudo.hh:52
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::PANIC
@ PANIC
Internal gem5 error.
Definition: types.hh:354
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:151
gem5::FailUnimplemented::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:133
gem5::WarnUnimplemented::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:169
gem5::DebugStep::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:203
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:43
gem5::DecoderFaultInst::faultName
const char * faultName() const
Definition: pseudo.cc:87
gem5::DecoderFaultInst::DecoderFaultInst
DecoderFaultInst(ArmISA::ExtMachInst _machInst)
Definition: pseudo.cc:50
gem5::ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:102
gem5::WarnUnimplemented::warned
bool warned
Have we warned on this instruction yet?
Definition: pseudo.hh:105
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::DecoderFault
DecoderFault
Instruction decoder fault codes in ExtMachInst.
Definition: types.hh:349
gem5::WarnUnimplemented::fullMnemonic
std::string fullMnemonic
Full mnemonic for MRC and MCR instructions including the coproc.
Definition: pseudo.hh:108
gem5::FailUnimplemented::FailUnimplemented
FailUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst)
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::DecoderFaultInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pseudo.cc:104
gem5::ExecContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::ArmFault::AlignmentFault
@ AlignmentFault
Definition: faults.hh:97
gem5::ArmISA::OK
@ OK
No fault.
Definition: types.hh:351
pseudo.hh
gem5::DecoderFaultInst::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: pseudo.cc:61
gem5::IllegalExecInst::IllegalExecInst
IllegalExecInst(ArmISA::ExtMachInst _machInst)
Definition: pseudo.cc:188
gem5::ArmISA::ISA::getSelfDebug
SelfDebug * getSelfDebug() const
Definition: isa.hh:633
exec_context.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISA::sd
Bitfield< 4 > sd
Definition: misc_types.hh:775
gem5::Trace::InstRecord
Definition: insttracer.hh:61
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:280
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::decoderFault
decoderFault
Definition: types.hh:61
gem5::DebugStep::DebugStep
DebugStep(ArmISA::ExtMachInst _machInst)
Definition: pseudo.cc:198
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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