gem5  v21.1.0.2
branch64.cc
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37 
39 
40 namespace gem5
41 {
42 
43 namespace ArmISA
44 {
45 
48 {
49  ArmISA::PCState pcs = branchPC;
50  pcs.instNPC(pcs.pc() + imm);
51  pcs.advance();
52  return pcs;
53 }
54 
57 {
58  ArmISA::PCState pcs = branchPC;
59  pcs.instNPC(pcs.pc() + imm);
60  pcs.advance();
61  return pcs;
62 }
63 
66 {
67  ArmISA::PCState pcs = branchPC;
68  pcs.instNPC(pcs.pc() + imm2);
69  pcs.advance();
70  return pcs;
71 }
72 
73 std::string
75  Addr pc, const loader::SymbolTable *symtab) const
76 {
77  std::stringstream ss;
78  printMnemonic(ss, "", false, true, condCode);
79  printTarget(ss, pc + imm, symtab);
80  return ss.str();
81 }
82 
83 std::string
85  Addr pc, const loader::SymbolTable *symtab) const
86 {
87  std::stringstream ss;
88  printMnemonic(ss, "", false);
89  printTarget(ss, pc + imm, symtab);
90  return ss.str();
91 }
92 
93 std::string
95  Addr pc, const loader::SymbolTable *symtab) const
96 {
97  std::stringstream ss;
98  printMnemonic(ss, "", false);
99  printIntReg(ss, op1);
100  return ss.str();
101 }
102 
103 std::string
105  Addr pc, const loader::SymbolTable *symtab) const
106 {
107  std::stringstream ss;
108  printMnemonic(ss, "", false);
109  printIntReg(ss, op1);
110  ccprintf(ss, ", ");
111  printIntReg(ss, op2);
112  return ss.str();
113 }
114 
115 std::string
117  Addr pc, const loader::SymbolTable *symtab) const
118 {
119  std::stringstream ss;
120  printMnemonic(ss, "", false);
121  if (op1 != INTREG_X30)
122  printIntReg(ss, op1);
123  return ss.str();
124 }
125 
126 std::string
128  Addr pc, const loader::SymbolTable *symtab) const
129 {
130  std::stringstream ss;
131  printMnemonic(ss, "", false);
132  if (op1 != INTREG_X30)
133  printIntReg(ss, op1);
134  return ss.str();
135 }
136 
137 std::string
139  Addr pc, const loader::SymbolTable *symtab) const
140 {
141  std::stringstream ss;
142  printMnemonic(ss, "", false);
143  return ss.str();
144 }
145 
146 std::string
148  Addr pc, const loader::SymbolTable *symtab) const
149 {
150  std::stringstream ss;
151  printMnemonic(ss, "", false);
152  return ss.str();
153 }
154 
155 std::string
157  Addr pc, const loader::SymbolTable *symtab) const
158 {
159  std::stringstream ss;
160  printMnemonic(ss, "", false);
161  printIntReg(ss, op1);
162  ccprintf(ss, ", ");
163  printTarget(ss, pc + imm, symtab);
164  return ss.str();
165 }
166 
167 std::string
169  Addr pc, const loader::SymbolTable *symtab) const
170 {
171  std::stringstream ss;
172  printMnemonic(ss, "", false);
173  printIntReg(ss, op1);
174  ccprintf(ss, ", #%#x, ", imm1);
175  printTarget(ss, pc + imm2, symtab);
176  return ss.str();
177 }
178 
179 } // namespace ArmISA
180 } // namespace gem5
gem5::ArmISA::BranchImmReg64::imm
int64_t imm
Definition: branch64.hh:175
gem5::ArmISA::BranchImmCond64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:74
gem5::ArmISA::BranchRet64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:116
gem5::ArmISA::BranchImm64::imm
int64_t imm
Definition: branch64.hh:52
gem5::ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:377
gem5::ArmISA::BranchRegReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:104
gem5::ArmISA::BranchImmReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:156
gem5::ArmISA::BranchReg64::op1
IntRegIndex op1
Definition: branch64.hh:107
branch64.hh
gem5::ArmISA::BranchImmReg64::branchTarget
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const override
Return the target address for a PC-relative branch.
Definition: branch64.cc:56
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::BranchImmImmReg64::op1
IntRegIndex op1
Definition: branch64.hh:200
gem5::ArmISA::BranchImm64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:84
gem5::ArmISA::BranchRetA64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:127
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::ArmStaticInst::printTarget
void printTarget(std::ostream &os, Addr target, const loader::SymbolTable *symtab) const
Definition: static_inst.cc:398
gem5::ArmISA::BranchEret64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:138
gem5::ArmISA::BranchImmCond64::condCode
ConditionCode condCode
Definition: branch64.hh:74
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::ArmISA::BranchEretA64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:147
gem5::ArmISA::BranchReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:94
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::BranchImmReg64::op1
IntRegIndex op1
Definition: branch64.hh:176
gem5::ArmISA::BranchImmImmReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:168
gem5::ArmISA::BranchRegReg64::op1
IntRegIndex op1
Definition: branch64.hh:90
gem5::ArmISA::BranchRegReg64::op2
IntRegIndex op2
Definition: branch64.hh:91
gem5::ArmISA::BranchImmImmReg64::branchTarget
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const override
Return the target address for a PC-relative branch.
Definition: branch64.cc:65
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::BranchImm64::branchTarget
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const override
Return the target address for a PC-relative branch.
Definition: branch64.cc:47
gem5::GenericISA::DelaySlotPCState::advance
void advance()
Definition: types.hh:337
gem5::ArmISA::BranchImmImmReg64::imm1
int64_t imm1
Definition: branch64.hh:198
gem5::ArmISA::BranchImmImmReg64::imm2
int64_t imm2
Definition: branch64.hh:199
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40

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