gem5  v21.2.1.1
branch64.cc
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37 
39 
40 namespace gem5
41 {
42 
43 namespace ArmISA
44 {
45 
46 std::unique_ptr<PCStateBase>
47 BranchImm64::branchTarget(const PCStateBase &branch_pc) const
48 {
49  PCStateBase *pcs = branch_pc.clone();
50  auto &apc = pcs->as<PCState>();
51  apc.instNPC(apc.pc() + imm);
52  apc.advance();
53  return std::unique_ptr<PCStateBase>{pcs};
54 }
55 
56 std::unique_ptr<PCStateBase>
58 {
59  PCStateBase *pcs = branch_pc.clone();
60  auto &apc = pcs->as<PCState>();
61  apc.instNPC(apc.pc() + imm);
62  apc.advance();
63  return std::unique_ptr<PCStateBase>{pcs};
64 }
65 
66 std::unique_ptr<PCStateBase>
68 {
69  PCStateBase *pcs = branch_pc.clone();
70  auto &apc = pcs->as<PCState>();
71  apc.instNPC(apc.pc() + imm2);
72  apc.advance();
73  return std::unique_ptr<PCStateBase>{pcs};
74 }
75 
76 std::string
78  Addr pc, const loader::SymbolTable *symtab) const
79 {
80  std::stringstream ss;
81  printMnemonic(ss, "", false, true, condCode);
82  printTarget(ss, pc + imm, symtab);
83  return ss.str();
84 }
85 
86 std::string
88  Addr pc, const loader::SymbolTable *symtab) const
89 {
90  std::stringstream ss;
91  printMnemonic(ss, "", false);
92  printTarget(ss, pc + imm, symtab);
93  return ss.str();
94 }
95 
96 std::string
98  Addr pc, const loader::SymbolTable *symtab) const
99 {
100  std::stringstream ss;
101  printMnemonic(ss, "", false);
102  printIntReg(ss, op1);
103  return ss.str();
104 }
105 
106 std::string
108  Addr pc, const loader::SymbolTable *symtab) const
109 {
110  std::stringstream ss;
111  printMnemonic(ss, "", false);
112  printIntReg(ss, op1);
113  ccprintf(ss, ", ");
114  printIntReg(ss, op2);
115  return ss.str();
116 }
117 
118 std::string
120  Addr pc, const loader::SymbolTable *symtab) const
121 {
122  std::stringstream ss;
123  printMnemonic(ss, "", false);
124  if (op1 != INTREG_X30)
125  printIntReg(ss, op1);
126  return ss.str();
127 }
128 
129 std::string
131  Addr pc, const loader::SymbolTable *symtab) const
132 {
133  std::stringstream ss;
134  printMnemonic(ss, "", false);
135  if (op1 != INTREG_X30)
136  printIntReg(ss, op1);
137  return ss.str();
138 }
139 
140 std::string
142  Addr pc, const loader::SymbolTable *symtab) const
143 {
144  std::stringstream ss;
145  printMnemonic(ss, "", false);
146  return ss.str();
147 }
148 
149 std::string
151  Addr pc, const loader::SymbolTable *symtab) const
152 {
153  std::stringstream ss;
154  printMnemonic(ss, "", false);
155  return ss.str();
156 }
157 
158 std::string
160  Addr pc, const loader::SymbolTable *symtab) const
161 {
162  std::stringstream ss;
163  printMnemonic(ss, "", false);
164  printIntReg(ss, op1);
165  ccprintf(ss, ", ");
166  printTarget(ss, pc + imm, symtab);
167  return ss.str();
168 }
169 
170 std::string
172  Addr pc, const loader::SymbolTable *symtab) const
173 {
174  std::stringstream ss;
175  printMnemonic(ss, "", false);
176  printIntReg(ss, op1);
177  ccprintf(ss, ", #%#x, ", imm1);
178  printTarget(ss, pc + imm2, symtab);
179  return ss.str();
180 }
181 
182 } // namespace ArmISA
183 } // namespace gem5
gem5::ArmISA::BranchImmReg64::imm
int64_t imm
Definition: branch64.hh:174
gem5::ArmISA::BranchImmCond64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:77
gem5::ArmISA::BranchRet64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:119
gem5::ArmISA::BranchImm64::imm
int64_t imm
Definition: branch64.hh:52
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ArmISA::BranchImmReg64::branchTarget
std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &branch_pc) const override
Return the target address for a PC-relative branch.
Definition: branch64.cc:57
gem5::ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:377
gem5::ArmISA::BranchRegReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:107
gem5::ArmISA::BranchImmReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:159
gem5::ArmISA::BranchReg64::op1
IntRegIndex op1
Definition: branch64.hh:107
branch64.hh
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::BranchImmImmReg64::op1
IntRegIndex op1
Definition: branch64.hh:199
gem5::ArmISA::BranchImm64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:87
gem5::ArmISA::BranchRetA64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:130
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::ArmStaticInst::printTarget
void printTarget(std::ostream &os, Addr target, const loader::SymbolTable *symtab) const
Definition: static_inst.cc:398
gem5::ArmISA::BranchEret64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:141
gem5::ArmISA::BranchImmImmReg64::branchTarget
std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &branch_pc) const override
Return the target address for a PC-relative branch.
Definition: branch64.cc:67
gem5::ArmISA::BranchImmCond64::condCode
ConditionCode condCode
Definition: branch64.hh:74
gem5::ArmISA::BranchEretA64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:150
gem5::ArmISA::BranchReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:97
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::BranchImmReg64::op1
IntRegIndex op1
Definition: branch64.hh:175
gem5::ArmISA::BranchImmImmReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:171
gem5::ArmISA::BranchRegReg64::op1
IntRegIndex op1
Definition: branch64.hh:90
gem5::ArmISA::BranchRegReg64::op2
IntRegIndex op2
Definition: branch64.hh:91
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:60
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::BranchImmImmReg64::imm1
int64_t imm1
Definition: branch64.hh:197
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ArmISA::BranchImmImmReg64::imm2
int64_t imm2
Definition: branch64.hh:198
gem5::ArmISA::BranchImm64::branchTarget
std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &branch_pc) const override
Return the target address for a PC-relative branch.
Definition: branch64.cc:47
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::PCStateBase::clone
virtual PCStateBase * clone() const =0
gem5::GenericISA::SimplePCState::advance
void advance() override
Definition: pcstate.hh:376

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