gem5  v22.0.0.2
branch64.hh
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37 
38 #ifndef __ARCH_ARM_INSTS_BRANCH64_HH__
39 #define __ARCH_ARM_INSTS_BRANCH64_HH__
40 
42 
43 namespace gem5
44 {
45 
46 namespace ArmISA
47 {
48 // Branch to a target computed with an immediate
49 class BranchImm64 : public ArmStaticInst
50 {
51  protected:
52  int64_t imm;
53 
54  public:
55  BranchImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
56  int64_t _imm) :
57  ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
58  {}
59 
60  std::unique_ptr<PCStateBase> branchTarget(
61  const PCStateBase &branch_pc) const override;
62 
65 
66  std::string generateDisassembly(
67  Addr pc, const loader::SymbolTable *symtab) const override;
68 };
69 
70 // Conditionally Branch to a target computed with an immediate
72 {
73  protected:
75 
76  public:
77  BranchImmCond64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
78  int64_t _imm, ConditionCode _condCode) :
79  BranchImm64(mnem, _machInst, __opClass, _imm), condCode(_condCode)
80  {}
81 
82  std::string generateDisassembly(
83  Addr pc, const loader::SymbolTable *symtab) const override;
84 };
85 
86 // Branch to a target computed with two registers
88 {
89  protected:
92 
93  public:
94  BranchRegReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
95  RegIndex _op1, RegIndex _op2) :
96  ArmStaticInst(mnem, _machInst, __opClass), op1(_op1), op2(_op2)
97  {}
98 
99  std::string generateDisassembly(
100  Addr pc, const loader::SymbolTable *symtab) const override;
101 };
102 
103 // Branch to a target computed with a register
105 {
106  protected:
108 
109  public:
110  BranchReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
111  RegIndex _op1) :
112  ArmStaticInst(mnem, _machInst, __opClass), op1(_op1)
113  {}
114 
115  std::string generateDisassembly(
116  Addr pc, const loader::SymbolTable *symtab) const override;
117 };
118 
119 // Ret instruction
120 class BranchRet64 : public BranchReg64
121 {
122  public:
123  BranchRet64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
124  RegIndex _op1) :
125  BranchReg64(mnem, _machInst, __opClass, _op1)
126  {}
127 
128  std::string generateDisassembly(
129  Addr pc, const loader::SymbolTable *symtab) const override;
130 };
131 
132 // RetAA/RetAB instruction
134 {
135  public:
136  BranchRetA64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
137  BranchRegReg64(mnem, _machInst, __opClass, int_reg::X30, int_reg::Spx)
138  {}
139 
140  std::string generateDisassembly(
141  Addr pc, const loader::SymbolTable *symtab) const override;
142 };
143 
144 // Eret instruction
146 {
147  public:
148  BranchEret64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
149  ArmStaticInst(mnem, _machInst, __opClass)
150  {}
151 
152  std::string generateDisassembly(
153  Addr pc, const loader::SymbolTable *symtab) const override;
154 };
155 
156 // EretA/B instruction
158 {
159  protected:
161 
162  public:
163  BranchEretA64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
164  ArmStaticInst(mnem, _machInst, __opClass), op1(int_reg::Spx)
165  {}
166 
167  std::string generateDisassembly(
168  Addr pc, const loader::SymbolTable *symtab) const override;
169 };
170 // Branch to a target computed with an immediate and a register
172 {
173  protected:
174  int64_t imm;
176 
177  public:
178  BranchImmReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
179  int64_t _imm, RegIndex _op1) :
180  ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
181  {}
182 
183  std::unique_ptr<PCStateBase> branchTarget(
184  const PCStateBase &branch_pc) const override;
185 
188 
189  std::string generateDisassembly(
190  Addr pc, const loader::SymbolTable *symtab) const override;
191 };
192 
193 // Branch to a target computed with two immediates
195 {
196  protected:
197  int64_t imm1;
198  int64_t imm2;
200 
201  public:
202  BranchImmImmReg64(const char *mnem, ExtMachInst _machInst,
203  OpClass __opClass, int64_t _imm1, int64_t _imm2,
204  RegIndex _op1) :
205  ArmStaticInst(mnem, _machInst, __opClass),
206  imm1(_imm1), imm2(_imm2), op1(_op1)
207  {}
208 
209  std::unique_ptr<PCStateBase> branchTarget(
210  const PCStateBase &branch_pc) const override;
211 
214 
215  std::string generateDisassembly(
216  Addr pc, const loader::SymbolTable *symtab) const override;
217 };
218 
219 } // namespace ArmISA
220 } // namespace gem5
221 
222 #endif //__ARCH_ARM_INSTS_BRANCH_HH__
gem5::ArmISA::BranchRegReg64
Definition: branch64.hh:87
gem5::ArmISA::BranchImmReg64::imm
int64_t imm
Definition: branch64.hh:174
gem5::ArmISA::BranchRegReg64::BranchRegReg64
BranchRegReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _op1, RegIndex _op2)
Definition: branch64.hh:94
gem5::ArmISA::BranchImmCond64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:77
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:65
gem5::ArmISA::BranchRet64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:119
gem5::ArmISA::BranchImm64::imm
int64_t imm
Definition: branch64.hh:52
gem5::ArmISA::BranchRetA64
Definition: branch64.hh:133
gem5::ArmISA::BranchImmReg64::BranchImmReg64
BranchImmReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int64_t _imm, RegIndex _op1)
Definition: branch64.hh:178
gem5::ArmISA::BranchImmCond64
Definition: branch64.hh:71
gem5::ArmISA::BranchImmReg64::branchTarget
std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &branch_pc) const override
Return the target address for a PC-relative branch.
Definition: branch64.cc:57
gem5::ArmISA::BranchEretA64::op1
RegIndex op1
Definition: branch64.hh:160
gem5::ArmISA::BranchRegReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:107
gem5::ArmISA::BranchImmReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:159
gem5::ArmISA::BranchReg64::BranchReg64
BranchReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _op1)
Definition: branch64.hh:110
gem5::ArmISA::BranchEretA64
Definition: branch64.hh:157
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::BranchImm64
Definition: branch64.hh:49
gem5::ArmISA::BranchImm64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:87
gem5::ArmISA::BranchRetA64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:130
gem5::ArmISA::BranchEret64
Definition: branch64.hh:145
gem5::ArmISA::BranchRetA64::BranchRetA64
BranchRetA64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: branch64.hh:136
gem5::ArmISA::BranchReg64
Definition: branch64.hh:104
gem5::ArmISA::BranchEret64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:141
gem5::ArmISA::BranchRegReg64::op1
RegIndex op1
Definition: branch64.hh:90
gem5::ArmISA::BranchImmImmReg64::branchTarget
std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &branch_pc) const override
Return the target address for a PC-relative branch.
Definition: branch64.cc:67
gem5::ArmISA::BranchImmCond64::condCode
ConditionCode condCode
Definition: branch64.hh:74
gem5::ArmISA::BranchRet64
Definition: branch64.hh:120
gem5::ArmISA::BranchImmImmReg64::op1
RegIndex op1
Definition: branch64.hh:199
gem5::ArmISA::BranchEretA64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:150
gem5::ArmISA::BranchRegReg64::op2
RegIndex op2
Definition: branch64.hh:91
gem5::ArmISA::BranchReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:97
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::BranchImmImmReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:171
gem5::ArmISA::BranchImmReg64
Definition: branch64.hh:171
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::ArmISA::BranchImmReg64::op1
RegIndex op1
Definition: branch64.hh:175
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:82
static_inst.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::BranchRet64::BranchRet64
BranchRet64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _op1)
Definition: branch64.hh:123
gem5::StaticInst::branchTarget
virtual std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:46
gem5::ArmISA::BranchImm64::BranchImm64
BranchImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int64_t _imm)
Definition: branch64.hh:55
gem5::ArmISA::BranchImmImmReg64
Definition: branch64.hh:194
gem5::ArmISA::BranchImmImmReg64::imm1
int64_t imm1
Definition: branch64.hh:197
gem5::ArmISA::BranchEret64::BranchEret64
BranchEret64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: branch64.hh:148
gem5::ArmISA::BranchImmImmReg64::BranchImmImmReg64
BranchImmImmReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int64_t _imm1, int64_t _imm2, RegIndex _op1)
Definition: branch64.hh:202
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ArmISA::BranchImmImmReg64::imm2
int64_t imm2
Definition: branch64.hh:198
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ArmISA::BranchImm64::branchTarget
std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &branch_pc) const override
Return the target address for a PC-relative branch.
Definition: branch64.cc:47
gem5::ArmISA::BranchEretA64::BranchEretA64
BranchEretA64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: branch64.hh:163
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::BranchReg64::op1
RegIndex op1
Definition: branch64.hh:107
gem5::ArmISA::BranchImmCond64::BranchImmCond64
BranchImmCond64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int64_t _imm, ConditionCode _condCode)
Definition: branch64.hh:77

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