gem5  v21.1.0.2
branch64.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2011-2013 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef __ARCH_ARM_INSTS_BRANCH64_HH__
39 #define __ARCH_ARM_INSTS_BRANCH64_HH__
40 
42 
43 namespace gem5
44 {
45 
46 namespace ArmISA
47 {
48 // Branch to a target computed with an immediate
49 class BranchImm64 : public ArmStaticInst
50 {
51  protected:
52  int64_t imm;
53 
54  public:
55  BranchImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
56  int64_t _imm) :
57  ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
58  {}
59 
61  const ArmISA::PCState &branchPC) const override;
62 
65 
66  std::string generateDisassembly(
67  Addr pc, const loader::SymbolTable *symtab) const override;
68 };
69 
70 // Conditionally Branch to a target computed with an immediate
72 {
73  protected:
75 
76  public:
77  BranchImmCond64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
78  int64_t _imm, ConditionCode _condCode) :
79  BranchImm64(mnem, _machInst, __opClass, _imm), condCode(_condCode)
80  {}
81 
82  std::string generateDisassembly(
83  Addr pc, const loader::SymbolTable *symtab) const override;
84 };
85 
86 // Branch to a target computed with two registers
88 {
89  protected:
90  IntRegIndex op1;
91  IntRegIndex op2;
92 
93  public:
94  BranchRegReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
95  IntRegIndex _op1, IntRegIndex _op2) :
96  ArmStaticInst(mnem, _machInst, __opClass), op1(_op1), op2(_op2)
97  {}
98 
99  std::string generateDisassembly(
100  Addr pc, const loader::SymbolTable *symtab) const override;
101 };
102 
103 // Branch to a target computed with a register
105 {
106  protected:
107  IntRegIndex op1;
108 
109  public:
110  BranchReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
111  IntRegIndex _op1) :
112  ArmStaticInst(mnem, _machInst, __opClass), op1(_op1)
113  {}
114 
115  std::string generateDisassembly(
116  Addr pc, const loader::SymbolTable *symtab) const override;
117 };
118 
119 // Ret instruction
120 class BranchRet64 : public BranchReg64
121 {
122  public:
123  BranchRet64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
124  IntRegIndex _op1) :
125  BranchReg64(mnem, _machInst, __opClass, _op1)
126  {}
127 
128  std::string generateDisassembly(
129  Addr pc, const loader::SymbolTable *symtab) const override;
130 };
131 
132 // RetAA/RetAB instruction
134 {
135  public:
136  BranchRetA64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
137  BranchRegReg64(mnem, _machInst, __opClass, INTREG_X30,
138  makeSP(INTREG_SPX))
139  {}
140 
141  std::string generateDisassembly(
142  Addr pc, const loader::SymbolTable *symtab) const override;
143 };
144 
145 // Eret instruction
147 {
148  public:
149  BranchEret64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
150  ArmStaticInst(mnem, _machInst, __opClass)
151  {}
152 
153  std::string generateDisassembly(
154  Addr pc, const loader::SymbolTable *symtab) const override;
155 };
156 
157 // EretA/B instruction
159 {
160  protected:
161  IntRegIndex op1;
162 
163  public:
164  BranchEretA64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
165  ArmStaticInst(mnem, _machInst, __opClass), op1(makeSP(INTREG_SPX))
166  {}
167 
168  std::string generateDisassembly(
169  Addr pc, const loader::SymbolTable *symtab) const override;
170 };
171 // Branch to a target computed with an immediate and a register
173 {
174  protected:
175  int64_t imm;
176  IntRegIndex op1;
177 
178  public:
179  BranchImmReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
180  int64_t _imm, IntRegIndex _op1) :
181  ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
182  {}
183 
185  const ArmISA::PCState &branchPC) const override;
186 
189 
190  std::string generateDisassembly(
191  Addr pc, const loader::SymbolTable *symtab) const override;
192 };
193 
194 // Branch to a target computed with two immediates
196 {
197  protected:
198  int64_t imm1;
199  int64_t imm2;
200  IntRegIndex op1;
201 
202  public:
203  BranchImmImmReg64(const char *mnem, ExtMachInst _machInst,
204  OpClass __opClass, int64_t _imm1, int64_t _imm2,
205  IntRegIndex _op1) :
206  ArmStaticInst(mnem, _machInst, __opClass),
207  imm1(_imm1), imm2(_imm2), op1(_op1)
208  {}
209 
211  const ArmISA::PCState &branchPC) const override;
212 
215 
216  std::string generateDisassembly(
217  Addr pc, const loader::SymbolTable *symtab) const override;
218 };
219 
220 } // namespace ArmISA
221 } // namespace gem5
222 
223 #endif //__ARCH_ARM_INSTS_BRANCH_HH__
gem5::ArmISA::BranchRegReg64
Definition: branch64.hh:87
gem5::ArmISA::BranchImmReg64::imm
int64_t imm
Definition: branch64.hh:175
gem5::ArmISA::BranchImmCond64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:74
gem5::ArmISA::BranchImmImmReg64::BranchImmImmReg64
BranchImmImmReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int64_t _imm1, int64_t _imm2, IntRegIndex _op1)
Definition: branch64.hh:203
gem5::ArmISA::BranchImmReg64::BranchImmReg64
BranchImmReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int64_t _imm, IntRegIndex _op1)
Definition: branch64.hh:179
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::ArmISA::BranchRet64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:116
gem5::ArmISA::BranchImm64::imm
int64_t imm
Definition: branch64.hh:52
gem5::ArmISA::BranchRetA64
Definition: branch64.hh:133
gem5::ArmISA::BranchImmCond64
Definition: branch64.hh:71
gem5::ArmISA::BranchRegReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:104
gem5::ArmISA::BranchImmReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:156
gem5::ArmISA::BranchReg64::op1
IntRegIndex op1
Definition: branch64.hh:107
gem5::ArmISA::BranchRet64::BranchRet64
BranchRet64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1)
Definition: branch64.hh:123
gem5::ArmISA::BranchEretA64
Definition: branch64.hh:158
gem5::ArmISA::BranchImmReg64::branchTarget
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const override
Return the target address for a PC-relative branch.
Definition: branch64.cc:56
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::BranchImmImmReg64::op1
IntRegIndex op1
Definition: branch64.hh:200
gem5::ArmISA::BranchImm64
Definition: branch64.hh:49
gem5::ArmISA::BranchImm64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:84
gem5::ArmISA::BranchRetA64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:127
gem5::ArmISA::BranchEret64
Definition: branch64.hh:146
gem5::ArmISA::BranchRetA64::BranchRetA64
BranchRetA64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: branch64.hh:136
gem5::ArmISA::BranchReg64
Definition: branch64.hh:104
gem5::ArmISA::BranchEret64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:138
gem5::ArmISA::BranchReg64::BranchReg64
BranchReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1)
Definition: branch64.hh:110
gem5::ArmISA::BranchEretA64::op1
IntRegIndex op1
Definition: branch64.hh:161
gem5::ArmISA::BranchImmCond64::condCode
ConditionCode condCode
Definition: branch64.hh:74
gem5::ArmISA::BranchRet64
Definition: branch64.hh:120
gem5::StaticInst::branchTarget
virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:61
gem5::ArmISA::BranchRegReg64::BranchRegReg64
BranchRegReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2)
Definition: branch64.hh:94
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::ArmISA::BranchEretA64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:147
gem5::ArmISA::BranchReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:94
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::BranchImmReg64::op1
IntRegIndex op1
Definition: branch64.hh:176
gem5::ArmISA::BranchImmImmReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:168
gem5::ArmISA::BranchImmReg64
Definition: branch64.hh:172
gem5::ArmISA::BranchRegReg64::op1
IntRegIndex op1
Definition: branch64.hh:90
gem5::ArmISA::BranchRegReg64::op2
IntRegIndex op2
Definition: branch64.hh:91
gem5::ArmISA::makeSP
static IntRegIndex makeSP(IntRegIndex reg)
Definition: int.hh:513
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::BranchImmImmReg64::branchTarget
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const override
Return the target address for a PC-relative branch.
Definition: branch64.cc:65
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:67
static_inst.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::BranchImm64::branchTarget
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const override
Return the target address for a PC-relative branch.
Definition: branch64.cc:47
gem5::ArmISA::BranchImm64::BranchImm64
BranchImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int64_t _imm)
Definition: branch64.hh:55
gem5::ArmISA::BranchImmImmReg64
Definition: branch64.hh:195
gem5::ArmISA::BranchImmImmReg64::imm1
int64_t imm1
Definition: branch64.hh:198
gem5::ArmISA::BranchEret64::BranchEret64
BranchEret64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: branch64.hh:149
gem5::ArmISA::BranchImmImmReg64::imm2
int64_t imm2
Definition: branch64.hh:199
gem5::ArmISA::BranchEretA64::BranchEretA64
BranchEretA64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: branch64.hh:164
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::BranchImmCond64::BranchImmCond64
BranchImmCond64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int64_t _imm, ConditionCode _condCode)
Definition: branch64.hh:77

Generated on Tue Sep 21 2021 12:24:34 for gem5 by doxygen 1.8.17