gem5  v21.1.0.2
gem5::CheckerCPU Member List

This is the complete list of members for gem5::CheckerCPU, including all inherited members.

_cacheLineSizegem5::BaseCPUprotected
_cpuIdgem5::BaseCPUprotected
_dataRequestorIdgem5::BaseCPUprotected
_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_instRequestorIdgem5::BaseCPUprotected
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
_pidgem5::BaseCPUprotected
_socketIdgem5::BaseCPUprotected
_switchedOutgem5::BaseCPUprotected
_taskIdgem5::BaseCPUprotected
activateContext(ThreadID thread_num)gem5::BaseCPUvirtual
addressMonitorgem5::BaseCPUprivate
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) overridegem5::CheckerCPUinline
gem5::ExecContext::amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)gem5::ExecContextinlinevirtual
armMonitor(Addr address) overridegem5::CheckerCPUinlinevirtual
gem5::BaseCPU::armMonitor(ThreadID tid, Addr address)gem5::BaseCPU
BaseCPU(const Params &params, bool is_checker=false)gem5::BaseCPU
baseStatsgem5::BaseCPU
cacheLineSize() constgem5::BaseCPUinline
changedPCgem5::CheckerCPU
CheckerCPU(const Params &p)gem5::CheckerCPU
checkFlags(const RequestPtr &unverified_req, Addr vAddr, Addr pAddr, int flags)gem5::CheckerCPU
checkInterrupts(ThreadID tid) constgem5::BaseCPUinline
clearInterrupt(ThreadID tid, int int_num, int index)gem5::BaseCPUinline
clearInterrupts(ThreadID tid)gem5::BaseCPUinline
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated()gem5::Clockedinlineprotectedvirtual
contextToThread(ContextID cid)gem5::BaseCPUinline
CPU_STATE_ON enum valuegem5::BaseCPUprotected
CPU_STATE_SLEEP enum valuegem5::BaseCPUprotected
CPU_STATE_WAKEUP enum valuegem5::BaseCPUprotected
cpuId() constgem5::BaseCPUinline
cpuListgem5::BaseCPUprivatestatic
CPUState enum namegem5::BaseCPUprotected
curCycle() constgem5::Clockedinline
curMacroStaticInstgem5::CheckerCPUprotected
currentFunctionEndgem5::BaseCPUprivate
currentFunctionStartgem5::BaseCPUprivate
currentSection()gem5::Serializablestatic
curStaticInstgem5::CheckerCPUprotected
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
dataRequestorId() constgem5::BaseCPUinline
dcachePortgem5::CheckerCPUprotected
demapPage(Addr vaddr, uint64_t asn) overridegem5::CheckerCPUinlinevirtual
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
deschedulePowerGatingEvent()gem5::BaseCPU
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
dumpAndExit()gem5::CheckerCPU
enableFunctionTrace()gem5::BaseCPUprivate
enterPwrGating()gem5::BaseCPUprotected
enterPwrGatingEventgem5::BaseCPUprotected
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
exitOnErrorgem5::CheckerCPU
find(const char *name)gem5::SimObjectstatic
findContext(ThreadContext *tc)gem5::BaseCPU
flushTLBs()gem5::BaseCPU
frequency() constgem5::Clockedinline
functionEntryTickgem5::BaseCPUprivate
functionTraceStreamgem5::BaseCPUprivate
functionTracingEnabledgem5::BaseCPUprivate
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
genMemFragmentRequest(Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) constgem5::CheckerCPU
getAddrMonitor() overridegem5::CheckerCPUinlinevirtual
getContext(int tn)gem5::BaseCPUinlinevirtual
getCpuAddrMonitor(ThreadID tid)gem5::BaseCPUinline
getCurrentInstCount(ThreadID tid)gem5::BaseCPU
getDataPort() overridegem5::CheckerCPUinlinevirtual
getHtmTransactionalDepth() const overridegem5::CheckerCPUinlinevirtual
getHtmTransactionUid() const overridegem5::CheckerCPUinlinevirtual
getInstPort() overridegem5::CheckerCPUinlinevirtual
getInterruptController(ThreadID tid)gem5::BaseCPUinline
getMMUPtr()gem5::CheckerCPUinline
getPid() constgem5::BaseCPUinline
getPort(const std::string &if_name, PortID idx=InvalidPortID) overridegem5::BaseCPUvirtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
getTracer()gem5::BaseCPUinline
getWritableVecPredRegOperand(const StaticInst *si, int idx) overridegem5::CheckerCPUinlinevirtual
getWritableVecRegOperand(const StaticInst *si, int idx) overridegem5::CheckerCPUinlinevirtual
globalStatsgem5::BaseCPUprotectedstatic
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
haltContext(ThreadID thread_num)gem5::BaseCPUvirtual
handleError()gem5::CheckerCPUinline
icachePortgem5::CheckerCPUprotected
inHtmTransactionalState() const overridegem5::CheckerCPUinlinevirtual
init() overridegem5::CheckerCPUvirtual
initiateHtmCmd(Request::Flags flags) overridegem5::CheckerCPUinlinevirtual
initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)gem5::ExecContextinlinevirtual
initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)gem5::ExecContextinlinevirtual
initState()gem5::SimObjectvirtual
instAddr()gem5::CheckerCPUinline
instCntgem5::BaseCPUprotected
instCount()gem5::BaseCPUinline
instRequestorId() constgem5::BaseCPUinline
interruptsgem5::BaseCPUprotected
invldPidgem5::BaseCPUstatic
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
microPC()gem5::CheckerCPUinline
miscRegIdxsgem5::CheckerCPUprotected
mmugem5::CheckerCPUprotected
mwait(PacketPtr pkt) overridegem5::CheckerCPUinlinevirtual
gem5::BaseCPU::mwait(ThreadID tid, PacketPtr pkt)gem5::BaseCPU
mwaitAtomic(ThreadContext *tc) overridegem5::CheckerCPUinlinevirtual
gem5::BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)gem5::BaseCPU
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
newHtmTransactionUid() const overridegem5::CheckerCPUinlinevirtual
newPCStategem5::CheckerCPU
nextCycle() constgem5::Clockedinline
nextInstAddr()gem5::CheckerCPUinline
notifyFork()gem5::Drainableinlinevirtual
numContexts()gem5::BaseCPUinline
numInstgem5::CheckerCPUprotected
numLoadgem5::CheckerCPU
numSimulatedCPUs()gem5::BaseCPUinlinestatic
numSimulatedInsts()gem5::BaseCPUinlinestatic
numSimulatedOps()gem5::BaseCPUinlinestatic
numThreadsgem5::BaseCPU
gem5::operator=(const Group &)=deletegem5::statistics::Group
gem5::Clocked::operator=(Clocked &)=deletegem5::Clockedprotected
Params typedefgem5::ClockedObject
params() constgem5::SimObjectinline
PARAMS(CheckerCPU)gem5::CheckerCPU
gem5::BaseCPU::PARAMS(BaseCPU)gem5::BaseCPU
pathgem5::Serializableprivatestatic
pcState() const overridegem5::CheckerCPUinlinevirtual
pcState(const TheISA::PCState &val) overridegem5::CheckerCPUinlinevirtual
pmuProbePoint(const char *name)gem5::BaseCPUprotected
postInterrupt(ThreadID tid, int int_num, int index)gem5::BaseCPU
powerGatingOnIdlegem5::BaseCPUprotected
powerStategem5::ClockedObject
ppActiveCyclesgem5::BaseCPUprotected
ppAllCyclesgem5::BaseCPUprotected
ppRetiredBranchesgem5::BaseCPUprotected
ppRetiredInstsgem5::BaseCPUprotected
ppRetiredInstsPCgem5::BaseCPUprotected
ppRetiredLoadsgem5::BaseCPUprotected
ppRetiredStoresgem5::BaseCPUprotected
ppSleepinggem5::BaseCPUprotected
preDumpStats()gem5::statistics::Groupvirtual
previousCyclegem5::BaseCPUprotected
previousStategem5::BaseCPUprotected
probeInstCommit(const StaticInstPtr &inst, Addr pc)gem5::BaseCPUvirtual
probeManagergem5::SimObjectprivate
pwrGatingLatencygem5::BaseCPUprotected
readCCRegOperand(const StaticInst *si, int idx) overridegem5::CheckerCPUinlinevirtual
readFloatRegOperandBits(const StaticInst *si, int idx) overridegem5::CheckerCPUinlinevirtual
readIntRegOperand(const StaticInst *si, int idx) overridegem5::CheckerCPUinlinevirtual
readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) overridegem5::CheckerCPU
gem5::ExecContext::readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)gem5::ExecContextinlinevirtual
readMemAccPredicate() const overridegem5::CheckerCPUinlinevirtual
readMiscReg(int misc_reg) overridegem5::CheckerCPUinlinevirtual
readMiscRegNoEffect(int misc_reg) constgem5::CheckerCPUinline
readMiscRegOperand(const StaticInst *si, int idx) overridegem5::CheckerCPUinlinevirtual
readPredicate() const overridegem5::CheckerCPUinlinevirtual
readStCondFailures() const overridegem5::CheckerCPUinlinevirtual
readVecElemOperand(const StaticInst *si, int idx) const overridegem5::CheckerCPUinlinevirtual
readVecPredRegOperand(const StaticInst *si, int idx) const overridegem5::CheckerCPUinlinevirtual
readVecRegOperand(const StaticInst *si, int idx) const overridegem5::CheckerCPUinlinevirtual
recordPCChange(const TheISA::PCState &val)gem5::CheckerCPUinline
registerThreadContexts()gem5::BaseCPU
regProbeListeners()gem5::SimObjectvirtual
regProbePoints() overridegem5::BaseCPUvirtual
regStats() overridegem5::BaseCPUvirtual
requestorIdgem5::CheckerCPUprotected
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetClock() constgem5::Clockedinlineprotected
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
resultgem5::CheckerCPUprotected
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
scheduleInstStop(ThreadID tid, Counter insts, const char *cause)gem5::BaseCPU
schedulePowerGatingEvent()gem5::BaseCPU
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::CheckerCPUvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
serializeThread(CheckpointOut &cp, ThreadID tid) constgem5::BaseCPUinlinevirtual
setCCRegOperand(const StaticInst *si, int idx, RegVal val) overridegem5::CheckerCPUinlinevirtual
setCurTick(Tick newVal)gem5::EventManagerinline
setDcachePort(RequestPort *dcache_port)gem5::CheckerCPU
setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) overridegem5::CheckerCPUinlinevirtual
setIcachePort(RequestPort *icache_port)gem5::CheckerCPU
setIntRegOperand(const StaticInst *si, int idx, RegVal val) overridegem5::CheckerCPUinlinevirtual
setMemAccPredicate(bool val) overridegem5::CheckerCPUinlinevirtual
setMiscReg(int misc_reg, RegVal val) overridegem5::CheckerCPUinlinevirtual
setMiscRegNoEffect(int misc_reg, RegVal val)gem5::CheckerCPUinline
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) overridegem5::CheckerCPUinlinevirtual
setPid(uint32_t pid)gem5::BaseCPUinline
setPredicate(bool val) overridegem5::CheckerCPUinlinevirtual
setScalarResult(T &&t)gem5::CheckerCPUinline
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
setStCondFailures(unsigned int sc_failures) overridegem5::CheckerCPUinlinevirtual
setSystem(System *system)gem5::CheckerCPU
setVecElemOperand(const StaticInst *si, int idx, const TheISA::VecElem val) overridegem5::CheckerCPUinlinevirtual
setVecElemResult(T &&t)gem5::CheckerCPUinline
setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) overridegem5::CheckerCPUinlinevirtual
setVecPredResult(T &&t)gem5::CheckerCPUinline
setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val) overridegem5::CheckerCPUinlinevirtual
setVecResult(T &&t)gem5::CheckerCPUinline
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
socketId() constgem5::BaseCPUinline
startNumInstgem5::CheckerCPUprotected
startNumLoadgem5::CheckerCPU
startup() overridegem5::BaseCPUvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
suspendContext(ThreadID thread_num)gem5::BaseCPUvirtual
switchedOut() constgem5::BaseCPUinline
switchOut()gem5::BaseCPUvirtual
syscallRetryLatencygem5::BaseCPU
systemgem5::BaseCPU
systemPtrgem5::CheckerCPUprotected
takeOverFrom(BaseCPU *cpu)gem5::BaseCPUvirtual
taskId() constgem5::BaseCPUinline
taskId(uint32_t id)gem5::BaseCPUinline
tcgem5::CheckerCPUprotected
tcBase() const overridegem5::CheckerCPUinlinevirtual
threadgem5::CheckerCPU
threadBase()gem5::CheckerCPUinline
threadContextsgem5::BaseCPUprotected
tickgem5::Clockedmutableprivate
ticksToCycles(Tick t) constgem5::Clockedinline
totalInsts() const overridegem5::CheckerCPUinlinevirtual
totalOps() const overridegem5::CheckerCPUinlinevirtual
traceFunctions(Addr pc)gem5::BaseCPUinline
traceFunctionsInternal(Addr pc)gem5::BaseCPUprivate
tracergem5::BaseCPUprotected
unserialize(CheckpointIn &cp) overridegem5::CheckerCPUvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
unserializeThread(CheckpointIn &cp, ThreadID tid)gem5::BaseCPUinlinevirtual
unverifiedMemDatagem5::CheckerCPU
unverifiedReqgem5::CheckerCPU
unverifiedResultgem5::CheckerCPU
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
updateCycleCounters(CPUState state)gem5::BaseCPUinlineprotected
updateOnErrorgem5::CheckerCPU
verifyMemoryMode() constgem5::BaseCPUinlinevirtual
voltage() constgem5::Clockedinline
wakeup(ThreadID tid) overridegem5::CheckerCPUinlinevirtual
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
warnOnlyOnLoadErrorgem5::CheckerCPU
willChangePCgem5::CheckerCPU
workItemBegin()gem5::BaseCPUinline
workItemEnd()gem5::BaseCPUinline
workloadgem5::CheckerCPUprotected
writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) overridegem5::CheckerCPU
gem5::ExecContext::writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0gem5::ExecContextpure virtual
youngestSNgem5::CheckerCPU
zeroReggem5::CheckerCPUprotected
~BaseCPU()gem5::BaseCPUvirtual
~CheckerCPU()gem5::CheckerCPUvirtual
~Clocked()gem5::Clockedinlineprotectedvirtual
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

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