| _cacheLineSize | gem5::BaseCPU | protected |
| _cpuId | gem5::BaseCPU | protected |
| _dataRequestorId | gem5::BaseCPU | protected |
| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _instRequestorId | gem5::BaseCPU | protected |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| _pid | gem5::BaseCPU | protected |
| _socketId | gem5::BaseCPU | protected |
| _switchedOut | gem5::BaseCPU | protected |
| _taskId | gem5::BaseCPU | protected |
| activateContext(ThreadID thread_num) | gem5::BaseCPU | virtual |
| addressMonitor | gem5::BaseCPU | private |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override | gem5::CheckerCPU | inline |
| gem5::ExecContext::amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) | gem5::ExecContext | inlinevirtual |
| armMonitor(Addr address) override | gem5::CheckerCPU | inlinevirtual |
| gem5::BaseCPU::armMonitor(ThreadID tid, Addr address) | gem5::BaseCPU | |
| BaseCPU(const Params ¶ms, bool is_checker=false) | gem5::BaseCPU | |
| baseStats | gem5::BaseCPU | |
| cacheLineSize() const | gem5::BaseCPU | inline |
| changedPC | gem5::CheckerCPU | |
| CheckerCPU(const Params &p) | gem5::CheckerCPU | |
| checkFlags(const RequestPtr &unverified_req, Addr vAddr, Addr pAddr, int flags) | gem5::CheckerCPU | |
| checkInterrupts(ThreadID tid) const | gem5::BaseCPU | inline |
| clearInterrupt(ThreadID tid, int int_num, int index) | gem5::BaseCPU | inline |
| clearInterrupts(ThreadID tid) | gem5::BaseCPU | inline |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| commitStats | gem5::BaseCPU | |
| contextToThread(ContextID cid) | gem5::BaseCPU | inline |
| CPU_STATE_ON enum value | gem5::BaseCPU | protected |
| CPU_STATE_SLEEP enum value | gem5::BaseCPU | protected |
| CPU_STATE_WAKEUP enum value | gem5::BaseCPU | protected |
| cpuId() const | gem5::BaseCPU | inline |
| cpuList | gem5::BaseCPU | privatestatic |
| CPUState enum name | gem5::BaseCPU | protected |
| curCycle() const | gem5::Clocked | inline |
| curMacroStaticInst | gem5::CheckerCPU | protected |
| currentFunctionEnd | gem5::BaseCPU | private |
| currentFunctionStart | gem5::BaseCPU | private |
| currentSection() | gem5::Serializable | static |
| curStaticInst | gem5::CheckerCPU | protected |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| dataRequestorId() const | gem5::BaseCPU | inline |
| dcachePort | gem5::CheckerCPU | protected |
| demapPage(Addr vaddr, uint64_t asn) override | gem5::CheckerCPU | inlinevirtual |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| deschedulePowerGatingEvent() | gem5::BaseCPU | |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| dumpAndExit() | gem5::CheckerCPU | |
| enableFunctionTrace() | gem5::BaseCPU | private |
| enterPwrGating() | gem5::BaseCPU | protected |
| enterPwrGatingEvent | gem5::BaseCPU | protected |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| executeStats | gem5::BaseCPU | |
| exitOnError | gem5::CheckerCPU | |
| fetchStats | gem5::BaseCPU | |
| find(const char *name) | gem5::SimObject | static |
| findContext(ThreadContext *tc) | gem5::BaseCPU | |
| flushTLBs() | gem5::BaseCPU | |
| frequency() const | gem5::Clocked | inline |
| functionEntryTick | gem5::BaseCPU | private |
| functionTraceStream | gem5::BaseCPU | private |
| functionTracingEnabled | gem5::BaseCPU | private |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| genMemFragmentRequest(Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const | gem5::CheckerCPU | |
| getAddrMonitor() override | gem5::CheckerCPU | inlinevirtual |
| getContext(int tn) | gem5::BaseCPU | inlinevirtual |
| getCpuAddrMonitor(ThreadID tid) | gem5::BaseCPU | inline |
| getCurrentInstCount(ThreadID tid) | gem5::BaseCPU | |
| getDataPort() override | gem5::CheckerCPU | inlinevirtual |
| getHtmTransactionalDepth() const override | gem5::CheckerCPU | inlinevirtual |
| getHtmTransactionUid() const override | gem5::CheckerCPU | inlinevirtual |
| getInstPort() override | gem5::CheckerCPU | inlinevirtual |
| getInterruptController(ThreadID tid) | gem5::BaseCPU | inline |
| getMMUPtr() | gem5::CheckerCPU | inline |
| getPid() const | gem5::BaseCPU | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::BaseCPU | virtual |
| getProbeManager() | gem5::SimObject | |
| getRegOperand(const StaticInst *si, int idx) override | gem5::CheckerCPU | inlinevirtual |
| getRegOperand(const StaticInst *si, int idx, void *val) override | gem5::CheckerCPU | inlinevirtual |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| getTracer() | gem5::BaseCPU | inline |
| getWritableRegOperand(const StaticInst *si, int idx) override | gem5::CheckerCPU | inlinevirtual |
| globalStats | gem5::BaseCPU | protectedstatic |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| haltContext(ThreadID thread_num) | gem5::BaseCPU | virtual |
| handleError() | gem5::CheckerCPU | inline |
| htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) | gem5::BaseCPU | inlinevirtual |
| icachePort | gem5::CheckerCPU | protected |
| inHtmTransactionalState() const override | gem5::CheckerCPU | inlinevirtual |
| init() override | gem5::CheckerCPU | virtual |
| initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) | gem5::ExecContext | inlinevirtual |
| initiateMemMgmtCmd(Request::Flags flags) override | gem5::CheckerCPU | inlinevirtual |
| initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) | gem5::ExecContext | inlinevirtual |
| initState() | gem5::SimObject | virtual |
| instCnt | gem5::BaseCPU | protected |
| instCount() | gem5::BaseCPU | inline |
| instRequestorId() const | gem5::BaseCPU | inline |
| interrupts | gem5::BaseCPU | protected |
| invldPid | gem5::BaseCPU | static |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| miscRegIdxs | gem5::CheckerCPU | protected |
| mmu | gem5::CheckerCPU | protected |
| modelResetPort | gem5::BaseCPU | protected |
| mwait(PacketPtr pkt) override | gem5::CheckerCPU | inlinevirtual |
| gem5::BaseCPU::mwait(ThreadID tid, PacketPtr pkt) | gem5::BaseCPU | |
| mwaitAtomic(ThreadContext *tc) override | gem5::CheckerCPU | inlinevirtual |
| gem5::BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu) | gem5::BaseCPU | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| newHtmTransactionUid() const override | gem5::CheckerCPU | inlinevirtual |
| newPCState | gem5::CheckerCPU | |
| nextCycle() const | gem5::Clocked | inline |
| notifyFork() | gem5::Drainable | inlinevirtual |
| numContexts() | gem5::BaseCPU | inline |
| numInst | gem5::CheckerCPU | protected |
| numLoad | gem5::CheckerCPU | |
| numSimulatedCPUs() | gem5::BaseCPU | inlinestatic |
| numSimulatedInsts() | gem5::BaseCPU | inlinestatic |
| numSimulatedOps() | gem5::BaseCPU | inlinestatic |
| numThreads | gem5::BaseCPU | |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| PARAMS(CheckerCPU) | gem5::CheckerCPU | |
| gem5::BaseCPU::PARAMS(BaseCPU) | gem5::BaseCPU | |
| Params typedef | gem5::ClockedObject | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| pcState() const override | gem5::CheckerCPU | inlinevirtual |
| pcState(const PCStateBase &val) override | gem5::CheckerCPU | inlinevirtual |
| pmuProbePoint(const char *name) | gem5::BaseCPU | protected |
| postInterrupt(ThreadID tid, int int_num, int index) | gem5::BaseCPU | |
| powerGatingOnIdle | gem5::BaseCPU | protected |
| powerState | gem5::ClockedObject | |
| ppActiveCycles | gem5::BaseCPU | protected |
| ppAllCycles | gem5::BaseCPU | protected |
| ppRetiredBranches | gem5::BaseCPU | protected |
| ppRetiredInsts | gem5::BaseCPU | protected |
| ppRetiredInstsPC | gem5::BaseCPU | protected |
| ppRetiredLoads | gem5::BaseCPU | protected |
| ppRetiredStores | gem5::BaseCPU | protected |
| ppSleeping | gem5::BaseCPU | protected |
| preDumpStats() | gem5::statistics::Group | virtual |
| previousCycle | gem5::BaseCPU | protected |
| previousState | gem5::BaseCPU | protected |
| probeInstCommit(const StaticInstPtr &inst, Addr pc) | gem5::BaseCPU | virtual |
| probeManager | gem5::SimObject | private |
| pwrGatingLatency | gem5::BaseCPU | protected |
| readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override | gem5::CheckerCPU | |
| gem5::ExecContext::readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) | gem5::ExecContext | inlinevirtual |
| readMemAccPredicate() const override | gem5::CheckerCPU | inlinevirtual |
| readMiscReg(int misc_reg) override | gem5::CheckerCPU | inlinevirtual |
| readMiscRegNoEffect(int misc_reg) const | gem5::CheckerCPU | inline |
| readMiscRegOperand(const StaticInst *si, int idx) override | gem5::CheckerCPU | inlinevirtual |
| readPredicate() const override | gem5::CheckerCPU | inlinevirtual |
| readStCondFailures() const override | gem5::CheckerCPU | inlinevirtual |
| recordPCChange(const PCStateBase &val) | gem5::CheckerCPU | inline |
| registerThreadContexts() | gem5::BaseCPU | |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() override | gem5::BaseCPU | virtual |
| regStats() override | gem5::BaseCPU | virtual |
| requestorId | gem5::CheckerCPU | protected |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| result | gem5::CheckerCPU | protected |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| scheduleInstStop(ThreadID tid, Counter insts, std::string cause) | gem5::BaseCPU | |
| scheduleInstStopAnyThread(Counter max_insts) | gem5::BaseCPU | |
| schedulePowerGatingEvent() | gem5::BaseCPU | |
| scheduleSimpointsInstStop(std::vector< Counter > inst_starts) | gem5::BaseCPU | |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::CheckerCPU | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| serializeThread(CheckpointOut &cp, ThreadID tid) const | gem5::BaseCPU | inlinevirtual |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setDcachePort(RequestPort *dcache_port) | gem5::CheckerCPU | |
| setIcachePort(RequestPort *icache_port) | gem5::CheckerCPU | |
| setMemAccPredicate(bool val) override | gem5::CheckerCPU | inlinevirtual |
| setMiscReg(int misc_reg, RegVal val) override | gem5::CheckerCPU | inlinevirtual |
| setMiscRegNoEffect(int misc_reg, RegVal val) | gem5::CheckerCPU | inline |
| setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override | gem5::CheckerCPU | inlinevirtual |
| setPid(uint32_t pid) | gem5::BaseCPU | inline |
| setPredicate(bool val) override | gem5::CheckerCPU | inlinevirtual |
| setRegOperand(const StaticInst *si, int idx, RegVal val) override | gem5::CheckerCPU | inlinevirtual |
| setRegOperand(const StaticInst *si, int idx, const void *val) override | gem5::CheckerCPU | inlinevirtual |
| setReset(bool state) | gem5::BaseCPU | virtual |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| setStCondFailures(unsigned int sc_failures) override | gem5::CheckerCPU | inlinevirtual |
| setSystem(System *system) | gem5::CheckerCPU | |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| socketId() const | gem5::BaseCPU | inline |
| startNumInst | gem5::CheckerCPU | protected |
| startNumLoad | gem5::CheckerCPU | |
| startup() override | gem5::BaseCPU | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::statistics::Group | private |
| suspendContext(ThreadID thread_num) | gem5::BaseCPU | virtual |
| switchedOut() const | gem5::BaseCPU | inline |
| switchOut() | gem5::BaseCPU | virtual |
| syscallRetryLatency | gem5::BaseCPU | |
| system | gem5::BaseCPU | |
| systemPtr | gem5::CheckerCPU | protected |
| takeOverFrom(BaseCPU *cpu) | gem5::BaseCPU | virtual |
| taskId() const | gem5::BaseCPU | inline |
| taskId(uint32_t id) | gem5::BaseCPU | inline |
| tc | gem5::CheckerCPU | protected |
| tcBase() const override | gem5::CheckerCPU | inlinevirtual |
| thread | gem5::CheckerCPU | |
| threadBase() | gem5::CheckerCPU | inline |
| threadContexts | gem5::BaseCPU | protected |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| totalInsts() const override | gem5::CheckerCPU | inlinevirtual |
| totalOps() const override | gem5::CheckerCPU | inlinevirtual |
| traceFunctions(Addr pc) | gem5::BaseCPU | inline |
| traceFunctionsInternal(Addr pc) | gem5::BaseCPU | private |
| tracer | gem5::BaseCPU | protected |
| unserialize(CheckpointIn &cp) override | gem5::CheckerCPU | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| unserializeThread(CheckpointIn &cp, ThreadID tid) | gem5::BaseCPU | inlinevirtual |
| unverifiedMemData | gem5::CheckerCPU | |
| unverifiedReq | gem5::CheckerCPU | |
| unverifiedResult | gem5::CheckerCPU | |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| updateCycleCounters(CPUState state) | gem5::BaseCPU | inlineprotected |
| updateOnError | gem5::CheckerCPU | |
| verifyMemoryMode() const | gem5::BaseCPU | inlinevirtual |
| voltage() const | gem5::Clocked | inline |
| wakeup(ThreadID tid) override | gem5::CheckerCPU | inlinevirtual |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| warnOnlyOnLoadError | gem5::CheckerCPU | |
| willChangePC | gem5::CheckerCPU | |
| workItemBegin() | gem5::BaseCPU | inline |
| workItemEnd() | gem5::BaseCPU | inline |
| workload | gem5::CheckerCPU | protected |
| writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override | gem5::CheckerCPU | |
| gem5::ExecContext::writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0 | gem5::ExecContext | pure virtual |
| youngestSN | gem5::CheckerCPU | |
| ~BaseCPU() | gem5::BaseCPU | virtual |
| ~CheckerCPU() | gem5::CheckerCPU | virtual |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |