gem5  v21.2.0.0
Public Member Functions | Public Attributes | Protected Attributes | List of all members
gem5::CheckerCPU Class Reference

CheckerCPU class. More...

#include <cpu.hh>

Inheritance diagram for gem5::CheckerCPU:
gem5::ExecContext gem5::Checker< gem5::RefCountingPtr > gem5::Checker< DynInstPtr > gem5::DummyChecker gem5::o3::Checker

Public Member Functions

void init () override
 
 PARAMS (CheckerCPU)
 
 CheckerCPU (const Params &p)
 
virtual ~CheckerCPU ()
 
void setSystem (System *system)
 
void setIcachePort (RequestPort *icache_port)
 
void setDcachePort (RequestPort *dcache_port)
 
PortgetDataPort () override
 
PortgetInstPort () override
 
BaseMMUgetMMUPtr ()
 
virtual Counter totalInsts () const override
 
virtual Counter totalOps () const override
 
void serialize (CheckpointOut &cp) const override
 
void unserialize (CheckpointIn &cp) override
 
RegVal readIntRegOperand (const StaticInst *si, int idx) override
 Reads an integer register. More...
 
RegVal readFloatRegOperandBits (const StaticInst *si, int idx) override
 Reads a floating point register in its binary format, instead of by value. More...
 
const TheISA::VecRegContainer & readVecRegOperand (const StaticInst *si, int idx) const override
 Read source vector register operand. More...
 
TheISA::VecRegContainer & getWritableVecRegOperand (const StaticInst *si, int idx) override
 Read destination vector register operand for modification. More...
 
RegVal readVecElemOperand (const StaticInst *si, int idx) const override
 Vector Elem Interfaces. More...
 
const TheISA::VecPredRegContainer & readVecPredRegOperand (const StaticInst *si, int idx) const override
 Predicate registers interface. More...
 
TheISA::VecPredRegContainer & getWritableVecPredRegOperand (const StaticInst *si, int idx) override
 Gets destination predicate register operand for modification. More...
 
RegVal readCCRegOperand (const StaticInst *si, int idx) override
 
void setIntRegOperand (const StaticInst *si, int idx, RegVal val) override
 Sets an integer register to a value. More...
 
void setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val) override
 Sets the bits of a floating point register of single width to a binary value. More...
 
void setCCRegOperand (const StaticInst *si, int idx, RegVal val) override
 
void setVecRegOperand (const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
 Sets a destination vector register operand to a value. More...
 
void setVecElemOperand (const StaticInst *si, int idx, RegVal val) override
 Sets a vector register to a value. More...
 
void setVecPredRegOperand (const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
 Sets a destination predicate register operand to a value. More...
 
bool readPredicate () const override
 
void setPredicate (bool val) override
 
bool readMemAccPredicate () const override
 
void setMemAccPredicate (bool val) override
 
uint64_t getHtmTransactionUid () const override
 
uint64_t newHtmTransactionUid () const override
 
Fault initiateHtmCmd (Request::Flags flags) override
 Initiate an HTM command, e.g. More...
 
bool inHtmTransactionalState () const override
 
uint64_t getHtmTransactionalDepth () const override
 
const PCStateBasepcState () const override
 
void pcState (const PCStateBase &val) override
 
RegVal readMiscRegNoEffect (int misc_reg) const
 
RegVal readMiscReg (int misc_reg) override
 Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...
 
void setMiscRegNoEffect (int misc_reg, RegVal val)
 
void setMiscReg (int misc_reg, RegVal val) override
 Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...
 
RegVal readMiscRegOperand (const StaticInst *si, int idx) override
 
void setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override
 
void recordPCChange (const PCStateBase &val)
 
void demapPage (Addr vaddr, uint64_t asn) override
 Invalidate a page in the DTLB and ITLB. More...
 
void armMonitor (Addr address) override
 
bool mwait (PacketPtr pkt) override
 
void mwaitAtomic (ThreadContext *tc) override
 
AddressMonitor * getAddrMonitor () override
 
RequestPtr genMemFragmentRequest (Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
 Helper function used to generate the request for a single fragment of a memory access. More...
 
Fault readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
 
Fault writeMem (uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
 
Fault amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 
unsigned int readStCondFailures () const override
 Returns the number of consecutive store conditional failures. More...
 
void setStCondFailures (unsigned int sc_failures) override
 Sets the number of consecutive store conditional failures. More...
 
void wakeup (ThreadID tid) override
 
void handleError ()
 
bool checkFlags (const RequestPtr &unverified_req, Addr vAddr, Addr pAddr, int flags)
 Checks if the flags set by the Checker and Checkee match. More...
 
void dumpAndExit ()
 
ThreadContexttcBase () const override
 Returns a pointer to the ThreadContext. More...
 
SimpleThreadthreadBase ()
 
- Public Member Functions inherited from gem5::ExecContext
virtual Fault readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
 Perform an atomic memory read operation. More...
 
virtual Fault initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
 Initiate a timing memory read operation. More...
 
virtual Fault writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0
 For atomic-mode contexts, perform an atomic memory write operation. More...
 
virtual Fault amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
 For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...
 
virtual Fault initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
 For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...
 

Public Attributes

SimpleThreadthread
 
Counter numLoad
 
Counter startNumLoad
 
InstResult unverifiedResult
 
RequestPtr unverifiedReq
 
uint8_t * unverifiedMemData
 
bool changedPC
 
bool willChangePC
 
std::unique_ptr< PCStateBasenewPCState
 
bool exitOnError
 
bool updateOnError
 
bool warnOnlyOnLoadError
 
InstSeqNum youngestSN
 

Protected Attributes

RequestorID requestorId
 id attached to all issued requests More...
 
const RegIndex zeroReg
 
std::vector< Process * > workload
 
SystemsystemPtr
 
RequestPorticachePort
 
RequestPortdcachePort
 
ThreadContexttc
 
BaseMMUmmu
 
std::queue< InstResultresult
 
StaticInstPtr curStaticInst
 
StaticInstPtr curMacroStaticInst
 
Counter numInst
 
Counter startNumInst
 
std::queue< int > miscRegIdxs
 

Detailed Description

CheckerCPU class.

Dynamically verifies instructions as they are completed by making sure that the instruction and its results match the independent execution of the benchmark inside the checker. The checker verifies instructions in order, regardless of the order in which instructions complete. There are certain results that can not be verified, specifically the result of a store conditional or the values of uncached accesses. In these cases, and with instructions marked as "IsUnverifiable", the checker assumes that the value from the main CPU's execution is correct and simply copies that value. It provides a CheckerThreadContext (see checker/thread_context.hh) that provides hooks for updating the Checker's state through any ThreadContext accesses. This allows the checker to be able to correctly verify instructions, even with external accesses to the ThreadContext that change state.

Definition at line 84 of file cpu.hh.

Constructor & Destructor Documentation

◆ CheckerCPU()

gem5::CheckerCPU::CheckerCPU ( const Params &  p)

◆ ~CheckerCPU()

gem5::CheckerCPU::~CheckerCPU ( )
virtual

Definition at line 92 of file cpu.cc.

Member Function Documentation

◆ amoMem()

Fault gem5::CheckerCPU::amoMem ( Addr  addr,
uint8_t *  data,
unsigned  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
inlineoverride

Definition at line 478 of file cpu.hh.

References panic.

◆ armMonitor()

void gem5::CheckerCPU::armMonitor ( Addr  address)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 433 of file cpu.hh.

◆ checkFlags()

bool gem5::CheckerCPU::checkFlags ( const RequestPtr unverified_req,
Addr  vAddr,
Addr  pAddr,
int  flags 
)

Checks if the flags set by the Checker and Checkee match.

Definition at line 357 of file cpu.cc.

Referenced by readMem(), and writeMem().

◆ demapPage()

void gem5::CheckerCPU::demapPage ( Addr  vaddr,
uint64_t  asn 
)
inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements gem5::ExecContext.

Definition at line 427 of file cpu.hh.

References gem5::BaseMMU::demapPage(), mmu, and gem5::MipsISA::vaddr.

◆ dumpAndExit()

void gem5::CheckerCPU::dumpAndExit ( )

◆ genMemFragmentRequest()

RequestPtr gem5::CheckerCPU::genMemFragmentRequest ( Addr  frag_addr,
int  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable,
int &  frag_size,
int &  size_left 
) const

Helper function used to generate the request for a single fragment of a memory access.

Takes care of setting up the appropriate byte-enable mask for the fragment, given the mask for the entire memory access.

Parameters
frag_addrStart address of the fragment.
sizeTotal size of the memory access in bytes.
flagsRequest flags.
byte_enableByte-enable mask for the entire memory access.
[out]frag_sizeFragment size.
[in,out]size_leftSize left to be processed in the memory access.
Returns
Pointer to the allocated Request, nullptr if the byte-enable mask is all-false for the fragment.

Definition at line 141 of file cpu.cc.

References gem5::addrBlockOffset(), gem5::ThreadContext::contextId(), gem5::PCStateBase::instAddr(), gem5::isAnyActiveElement(), gem5::SimpleThread::pcState(), requestorId, tc, and thread.

Referenced by readMem(), and writeMem().

◆ getAddrMonitor()

AddressMonitor* gem5::CheckerCPU::getAddrMonitor ( )
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 443 of file cpu.hh.

◆ getDataPort()

Port& gem5::CheckerCPU::getDataPort ( )
inlineoverride

Definition at line 106 of file cpu.hh.

References dcachePort.

◆ getHtmTransactionalDepth()

uint64_t gem5::CheckerCPU::getHtmTransactionalDepth ( ) const
inlineoverridevirtual

◆ getHtmTransactionUid()

uint64_t gem5::CheckerCPU::getHtmTransactionUid ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 324 of file cpu.hh.

References panic.

◆ getInstPort()

Port& gem5::CheckerCPU::getInstPort ( )
inlineoverride

Definition at line 115 of file cpu.hh.

References icachePort.

◆ getMMUPtr()

BaseMMU* gem5::CheckerCPU::getMMUPtr ( )
inline

Definition at line 154 of file cpu.hh.

References mmu.

◆ getWritableVecPredRegOperand()

TheISA::VecPredRegContainer& gem5::CheckerCPU::getWritableVecPredRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Gets destination predicate register operand for modification.

Implements gem5::ExecContext.

Definition at line 232 of file cpu.hh.

References gem5::SimpleThread::getWritableVecPredReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecPredRegClass.

◆ getWritableVecRegOperand()

TheISA::VecRegContainer& gem5::CheckerCPU::getWritableVecRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Read destination vector register operand for modification.

Implements gem5::ExecContext.

Definition at line 209 of file cpu.hh.

References gem5::SimpleThread::getWritableVecReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecRegClass.

◆ handleError()

void gem5::CheckerCPU::handleError ( )
inline

Definition at line 496 of file cpu.hh.

References dumpAndExit(), and exitOnError.

Referenced by readMem(), gem5::Checker< gem5::RefCountingPtr >::verify(), and writeMem().

◆ inHtmTransactionalState()

bool gem5::CheckerCPU::inHtmTransactionalState ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 345 of file cpu.hh.

References getHtmTransactionalDepth().

◆ init()

void gem5::CheckerCPU::init ( )
override

◆ initiateHtmCmd()

Fault gem5::CheckerCPU::initiateHtmCmd ( Request::Flags  flags)
inlineoverridevirtual

Initiate an HTM command, e.g.

tell Ruby we're starting/stopping a transaction

Implements gem5::ExecContext.

Definition at line 338 of file cpu.hh.

References gem5::NoFault, and panic.

◆ mwait()

bool gem5::CheckerCPU::mwait ( PacketPtr  pkt)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 434 of file cpu.hh.

◆ mwaitAtomic()

void gem5::CheckerCPU::mwaitAtomic ( ThreadContext tc)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 437 of file cpu.hh.

References gem5::SimpleThread::mmu, tc, and thread.

◆ newHtmTransactionUid()

uint64_t gem5::CheckerCPU::newHtmTransactionUid ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 331 of file cpu.hh.

References panic.

◆ PARAMS()

gem5::CheckerCPU::PARAMS ( CheckerCPU  )

◆ pcState() [1/2]

const PCStateBase& gem5::CheckerCPU::pcState ( ) const
inlineoverridevirtual

◆ pcState() [2/2]

void gem5::CheckerCPU::pcState ( const PCStateBase val)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 363 of file cpu.hh.

References DPRINTF, gem5::SimpleThread::pcState(), thread, and gem5::X86ISA::val.

◆ readCCRegOperand()

RegVal gem5::CheckerCPU::readCCRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

◆ readFloatRegOperandBits()

RegVal gem5::CheckerCPU::readFloatRegOperandBits ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Reads a floating point register in its binary format, instead of by value.

Implements gem5::ExecContext.

Definition at line 187 of file cpu.hh.

References gem5::FloatRegClass, gem5::SimpleThread::readFloatReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readIntRegOperand()

RegVal gem5::CheckerCPU::readIntRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Reads an integer register.

Implements gem5::ExecContext.

Definition at line 179 of file cpu.hh.

References gem5::IntRegClass, gem5::SimpleThread::readIntReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readMem()

Fault gem5::CheckerCPU::readMem ( Addr  addr,
uint8_t *  data,
unsigned  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable 
)
override

◆ readMemAccPredicate()

bool gem5::CheckerCPU::readMemAccPredicate ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 312 of file cpu.hh.

References gem5::SimpleThread::readMemAccPredicate(), and thread.

◆ readMiscReg()

RegVal gem5::CheckerCPU::readMiscReg ( int  misc_reg)
inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements gem5::ExecContext.

Definition at line 378 of file cpu.hh.

References gem5::SimpleThread::readMiscReg(), and thread.

◆ readMiscRegNoEffect()

RegVal gem5::CheckerCPU::readMiscRegNoEffect ( int  misc_reg) const
inline

Definition at line 372 of file cpu.hh.

References gem5::SimpleThread::readMiscRegNoEffect(), and thread.

◆ readMiscRegOperand()

RegVal gem5::CheckerCPU::readMiscRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

◆ readPredicate()

bool gem5::CheckerCPU::readPredicate ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 303 of file cpu.hh.

References gem5::SimpleThread::readPredicate(), and thread.

◆ readStCondFailures()

unsigned int gem5::CheckerCPU::readStCondFailures ( ) const
inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 485 of file cpu.hh.

References gem5::SimpleThread::readStCondFailures(), and thread.

◆ readVecElemOperand()

RegVal gem5::CheckerCPU::readVecElemOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Vector Elem Interfaces.

Reads an element of a vector register.

Implements gem5::ExecContext.

Definition at line 217 of file cpu.hh.

References gem5::SimpleThread::readVecElem(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readVecPredRegOperand()

const TheISA::VecPredRegContainer& gem5::CheckerCPU::readVecPredRegOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Predicate registers interface.

Reads source predicate register operand.

Implements gem5::ExecContext.

Definition at line 224 of file cpu.hh.

References gem5::SimpleThread::readVecPredReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecPredRegClass.

◆ readVecRegOperand()

const TheISA::VecRegContainer& gem5::CheckerCPU::readVecRegOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Read source vector register operand.

Implements gem5::ExecContext.

Definition at line 198 of file cpu.hh.

References gem5::SimpleThread::readVecReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecRegClass.

◆ recordPCChange()

void gem5::CheckerCPU::recordPCChange ( const PCStateBase val)
inline

Definition at line 420 of file cpu.hh.

References changedPC, newPCState, and gem5::X86ISA::val.

Referenced by gem5::CheckerThreadContext< TC >::pcState().

◆ serialize()

void gem5::CheckerCPU::serialize ( CheckpointOut cp) const
override

Definition at line 131 of file cpu.cc.

◆ setCCRegOperand()

void gem5::CheckerCPU::setCCRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

◆ setDcachePort()

void gem5::CheckerCPU::setDcachePort ( RequestPort dcache_port)

Definition at line 125 of file cpu.cc.

References dcachePort.

◆ setFloatRegOperandBits()

void gem5::CheckerCPU::setFloatRegOperandBits ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Sets the bits of a floating point register of single width to a binary value.

Implements gem5::ExecContext.

Definition at line 257 of file cpu.hh.

References gem5::FloatRegClass, gem5::X86ISA::reg, result, gem5::SimpleThread::setFloatReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setIcachePort()

void gem5::CheckerCPU::setIcachePort ( RequestPort icache_port)

Definition at line 119 of file cpu.cc.

References icachePort.

◆ setIntRegOperand()

void gem5::CheckerCPU::setIntRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Sets an integer register to a value.

Implements gem5::ExecContext.

Definition at line 248 of file cpu.hh.

References gem5::IntRegClass, gem5::X86ISA::reg, result, gem5::SimpleThread::setIntReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setMemAccPredicate()

void gem5::CheckerCPU::setMemAccPredicate ( bool  val)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 318 of file cpu.hh.

References gem5::SimpleThread::setMemAccPredicate(), thread, and gem5::X86ISA::val.

◆ setMiscReg()

void gem5::CheckerCPU::setMiscReg ( int  misc_reg,
RegVal  val 
)
inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements gem5::ExecContext.

Definition at line 393 of file cpu.hh.

References DPRINTF, miscRegIdxs, gem5::SimpleThread::setMiscReg(), thread, and gem5::X86ISA::val.

Referenced by setMiscRegOperand().

◆ setMiscRegNoEffect()

void gem5::CheckerCPU::setMiscRegNoEffect ( int  misc_reg,
RegVal  val 
)
inline

◆ setMiscRegOperand()

void gem5::CheckerCPU::setMiscRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

◆ setPredicate()

void gem5::CheckerCPU::setPredicate ( bool  val)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 306 of file cpu.hh.

References gem5::SimpleThread::setPredicate(), thread, and gem5::X86ISA::val.

◆ setStCondFailures()

void gem5::CheckerCPU::setStCondFailures ( unsigned int  sc_failures)
inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 490 of file cpu.hh.

◆ setSystem()

void gem5::CheckerCPU::setSystem ( System system)

◆ setVecElemOperand()

void gem5::CheckerCPU::setVecElemOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Sets a vector register to a value.

Implements gem5::ExecContext.

Definition at line 285 of file cpu.hh.

References gem5::X86ISA::reg, result, gem5::SimpleThread::setVecElem(), gem5::ArmISA::si, thread, gem5::X86ISA::val, and gem5::VecElemClass.

◆ setVecPredRegOperand()

void gem5::CheckerCPU::setVecPredRegOperand ( const StaticInst si,
int  idx,
const TheISA::VecPredRegContainer &  val 
)
inlineoverridevirtual

Sets a destination predicate register operand to a value.

Implements gem5::ExecContext.

Definition at line 294 of file cpu.hh.

References gem5::X86ISA::reg, result, gem5::SimpleThread::setVecPredReg(), gem5::ArmISA::si, thread, gem5::X86ISA::val, and gem5::VecPredRegClass.

◆ setVecRegOperand()

void gem5::CheckerCPU::setVecRegOperand ( const StaticInst si,
int  idx,
const TheISA::VecRegContainer &  val 
)
inlineoverridevirtual

Sets a destination vector register operand to a value.

Implements gem5::ExecContext.

Definition at line 275 of file cpu.hh.

References gem5::X86ISA::reg, result, gem5::SimpleThread::setVecReg(), gem5::ArmISA::si, thread, gem5::X86ISA::val, and gem5::VecRegClass.

◆ tcBase()

ThreadContext* gem5::CheckerCPU::tcBase ( ) const
inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements gem5::ExecContext.

Definition at line 507 of file cpu.hh.

References tc.

◆ threadBase()

SimpleThread* gem5::CheckerCPU::threadBase ( )
inline

Definition at line 508 of file cpu.hh.

References thread.

◆ totalInsts()

virtual Counter gem5::CheckerCPU::totalInsts ( ) const
inlineoverridevirtual

Definition at line 156 of file cpu.hh.

◆ totalOps()

virtual Counter gem5::CheckerCPU::totalOps ( ) const
inlineoverridevirtual

Definition at line 158 of file cpu.hh.

◆ unserialize()

void gem5::CheckerCPU::unserialize ( CheckpointIn cp)
override

Definition at line 136 of file cpu.cc.

◆ wakeup()

void gem5::CheckerCPU::wakeup ( ThreadID  tid)
inlineoverride

Definition at line 493 of file cpu.hh.

◆ writeMem()

Fault gem5::CheckerCPU::writeMem ( uint8_t *  data,
unsigned  size,
Addr  addr,
Request::Flags  flags,
uint64_t *  res,
const std::vector< bool > &  byte_enable 
)
override

Member Data Documentation

◆ changedPC

bool gem5::CheckerCPU::changedPC

Definition at line 514 of file cpu.hh.

Referenced by CheckerCPU(), and recordPCChange().

◆ curMacroStaticInst

StaticInstPtr gem5::CheckerCPU::curMacroStaticInst
protected

Definition at line 141 of file cpu.hh.

Referenced by CheckerCPU().

◆ curStaticInst

StaticInstPtr gem5::CheckerCPU::curStaticInst
protected

Definition at line 140 of file cpu.hh.

Referenced by CheckerCPU().

◆ dcachePort

RequestPort* gem5::CheckerCPU::dcachePort
protected

Definition at line 130 of file cpu.hh.

Referenced by getDataPort(), readMem(), and setDcachePort().

◆ exitOnError

bool gem5::CheckerCPU::exitOnError

◆ icachePort

RequestPort* gem5::CheckerCPU::icachePort
protected

Definition at line 129 of file cpu.hh.

Referenced by getInstPort(), and setIcachePort().

◆ miscRegIdxs

std::queue<int> gem5::CheckerCPU::miscRegIdxs
protected

Definition at line 147 of file cpu.hh.

Referenced by setMiscReg(), and setMiscRegNoEffect().

◆ mmu

BaseMMU* gem5::CheckerCPU::mmu
protected

Definition at line 134 of file cpu.hh.

Referenced by CheckerCPU(), demapPage(), getMMUPtr(), readMem(), setSystem(), and writeMem().

◆ newPCState

std::unique_ptr<PCStateBase> gem5::CheckerCPU::newPCState

Definition at line 516 of file cpu.hh.

Referenced by recordPCChange().

◆ numInst

Counter gem5::CheckerCPU::numInst
protected

Definition at line 144 of file cpu.hh.

Referenced by CheckerCPU().

◆ numLoad

Counter gem5::CheckerCPU::numLoad

Definition at line 161 of file cpu.hh.

Referenced by CheckerCPU().

◆ requestorId

RequestorID gem5::CheckerCPU::requestorId
protected

id attached to all issued requests

Definition at line 88 of file cpu.hh.

Referenced by genMemFragmentRequest(), and init().

◆ result

std::queue<InstResult> gem5::CheckerCPU::result
protected

◆ startNumInst

Counter gem5::CheckerCPU::startNumInst
protected

Definition at line 145 of file cpu.hh.

Referenced by CheckerCPU().

◆ startNumLoad

Counter gem5::CheckerCPU::startNumLoad

Definition at line 162 of file cpu.hh.

Referenced by CheckerCPU().

◆ systemPtr

System* gem5::CheckerCPU::systemPtr
protected

Definition at line 127 of file cpu.hh.

Referenced by init(), and setSystem().

◆ tc

ThreadContext* gem5::CheckerCPU::tc
protected

Definition at line 132 of file cpu.hh.

Referenced by genMemFragmentRequest(), init(), mwaitAtomic(), readMem(), setSystem(), tcBase(), and writeMem().

◆ thread

SimpleThread* gem5::CheckerCPU::thread

◆ unverifiedMemData

uint8_t* gem5::CheckerCPU::unverifiedMemData

Definition at line 512 of file cpu.hh.

Referenced by readMem(), and writeMem().

◆ unverifiedReq

RequestPtr gem5::CheckerCPU::unverifiedReq

Definition at line 511 of file cpu.hh.

Referenced by readMem(), and writeMem().

◆ unverifiedResult

InstResult gem5::CheckerCPU::unverifiedResult

Definition at line 510 of file cpu.hh.

◆ updateOnError

bool gem5::CheckerCPU::updateOnError

Definition at line 518 of file cpu.hh.

Referenced by CheckerCPU(), and gem5::Checker< gem5::RefCountingPtr >::handleError().

◆ warnOnlyOnLoadError

bool gem5::CheckerCPU::warnOnlyOnLoadError

Definition at line 519 of file cpu.hh.

Referenced by CheckerCPU().

◆ willChangePC

bool gem5::CheckerCPU::willChangePC

Definition at line 515 of file cpu.hh.

Referenced by CheckerCPU().

◆ workload

std::vector<Process*> gem5::CheckerCPU::workload
protected

Definition at line 125 of file cpu.hh.

Referenced by CheckerCPU(), and setSystem().

◆ youngestSN

InstSeqNum gem5::CheckerCPU::youngestSN

Definition at line 521 of file cpu.hh.

Referenced by CheckerCPU().

◆ zeroReg

const RegIndex gem5::CheckerCPU::zeroReg
protected

Definition at line 90 of file cpu.hh.


The documentation for this class was generated from the following files:

Generated on Tue Dec 21 2021 11:34:57 for gem5 by doxygen 1.8.17