gem5  v21.1.0.2
Public Member Functions | Public Attributes | Protected Attributes | List of all members
gem5::CheckerCPU Class Reference

CheckerCPU class. More...

#include <cpu.hh>

Inheritance diagram for gem5::CheckerCPU:
gem5::BaseCPU gem5::ExecContext gem5::ClockedObject gem5::SimObject gem5::Clocked gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named gem5::Checker< gem5::RefCountingPtr > gem5::Checker< DynInstPtr > gem5::DummyChecker gem5::o3::Checker

Public Member Functions

void init () override
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
 PARAMS (CheckerCPU)
 
 CheckerCPU (const Params &p)
 
virtual ~CheckerCPU ()
 
void setSystem (System *system)
 
void setIcachePort (RequestPort *icache_port)
 
void setDcachePort (RequestPort *dcache_port)
 
PortgetDataPort () override
 Purely virtual method that returns a reference to the data port. More...
 
PortgetInstPort () override
 Purely virtual method that returns a reference to the instruction port. More...
 
BaseMMUgetMMUPtr ()
 
virtual Counter totalInsts () const override
 
virtual Counter totalOps () const override
 
void serialize (CheckpointOut &cp) const override
 Serialize this object to the given output stream. More...
 
void unserialize (CheckpointIn &cp) override
 Reconstruct the state of this object from a checkpoint. More...
 
RegVal readIntRegOperand (const StaticInst *si, int idx) override
 Reads an integer register. More...
 
RegVal readFloatRegOperandBits (const StaticInst *si, int idx) override
 Reads a floating point register in its binary format, instead of by value. More...
 
const TheISA::VecRegContainer & readVecRegOperand (const StaticInst *si, int idx) const override
 Read source vector register operand. More...
 
TheISA::VecRegContainer & getWritableVecRegOperand (const StaticInst *si, int idx) override
 Read destination vector register operand for modification. More...
 
TheISA::VecElem readVecElemOperand (const StaticInst *si, int idx) const override
 Vector Elem Interfaces. More...
 
const TheISA::VecPredRegContainer & readVecPredRegOperand (const StaticInst *si, int idx) const override
 Predicate registers interface. More...
 
TheISA::VecPredRegContainer & getWritableVecPredRegOperand (const StaticInst *si, int idx) override
 Gets destination predicate register operand for modification. More...
 
RegVal readCCRegOperand (const StaticInst *si, int idx) override
 
template<typename T >
void setScalarResult (T &&t)
 
template<typename T >
void setVecResult (T &&t)
 
template<typename T >
void setVecElemResult (T &&t)
 
template<typename T >
void setVecPredResult (T &&t)
 
void setIntRegOperand (const StaticInst *si, int idx, RegVal val) override
 Sets an integer register to a value. More...
 
void setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val) override
 Sets the bits of a floating point register of single width to a binary value. More...
 
void setCCRegOperand (const StaticInst *si, int idx, RegVal val) override
 
void setVecRegOperand (const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
 Sets a destination vector register operand to a value. More...
 
void setVecElemOperand (const StaticInst *si, int idx, const TheISA::VecElem val) override
 Sets a vector register to a value. More...
 
void setVecPredRegOperand (const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
 Sets a destination predicate register operand to a value. More...
 
bool readPredicate () const override
 
void setPredicate (bool val) override
 
bool readMemAccPredicate () const override
 
void setMemAccPredicate (bool val) override
 
uint64_t getHtmTransactionUid () const override
 
uint64_t newHtmTransactionUid () const override
 
Fault initiateHtmCmd (Request::Flags flags) override
 Initiate an HTM command, e.g. More...
 
bool inHtmTransactionalState () const override
 
uint64_t getHtmTransactionalDepth () const override
 
TheISA::PCState pcState () const override
 
void pcState (const TheISA::PCState &val) override
 
Addr instAddr ()
 
Addr nextInstAddr ()
 
MicroPC microPC ()
 
RegVal readMiscRegNoEffect (int misc_reg) const
 
RegVal readMiscReg (int misc_reg) override
 Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...
 
void setMiscRegNoEffect (int misc_reg, RegVal val)
 
void setMiscReg (int misc_reg, RegVal val) override
 Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...
 
RegVal readMiscRegOperand (const StaticInst *si, int idx) override
 
void setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override
 
void recordPCChange (const TheISA::PCState &val)
 
void demapPage (Addr vaddr, uint64_t asn) override
 Invalidate a page in the DTLB and ITLB. More...
 
void armMonitor (Addr address) override
 
bool mwait (PacketPtr pkt) override
 
void mwaitAtomic (ThreadContext *tc) override
 
AddressMonitorgetAddrMonitor () override
 
RequestPtr genMemFragmentRequest (Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
 Helper function used to generate the request for a single fragment of a memory access. More...
 
Fault readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
 
Fault writeMem (uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
 
Fault amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 
unsigned int readStCondFailures () const override
 Returns the number of consecutive store conditional failures. More...
 
void setStCondFailures (unsigned int sc_failures) override
 Sets the number of consecutive store conditional failures. More...
 
void wakeup (ThreadID tid) override
 
void handleError ()
 
bool checkFlags (const RequestPtr &unverified_req, Addr vAddr, Addr pAddr, int flags)
 Checks if the flags set by the Checker and Checkee match. More...
 
void dumpAndExit ()
 
ThreadContexttcBase () const override
 Returns a pointer to the ThreadContext. More...
 
SimpleThreadthreadBase ()
 
- Public Member Functions inherited from gem5::BaseCPU
int cpuId () const
 Reads this CPU's ID. More...
 
uint32_t socketId () const
 Reads this CPU's Socket ID. More...
 
RequestorID dataRequestorId () const
 Reads this CPU's unique data requestor ID. More...
 
RequestorID instRequestorId () const
 Reads this CPU's unique instruction requestor ID. More...
 
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
 Get a port on this CPU. More...
 
uint32_t taskId () const
 Get cpu task id. More...
 
void taskId (uint32_t id)
 Set cpu task id. More...
 
uint32_t getPid () const
 
void setPid (uint32_t pid)
 
void workItemBegin ()
 
void workItemEnd ()
 
Tick instCount ()
 
BaseInterruptsgetInterruptController (ThreadID tid)
 
void postInterrupt (ThreadID tid, int int_num, int index)
 
void clearInterrupt (ThreadID tid, int int_num, int index)
 
void clearInterrupts (ThreadID tid)
 
bool checkInterrupts (ThreadID tid) const
 
Trace::InstTracergetTracer ()
 Provide access to the tracer pointer. More...
 
virtual void activateContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now active. More...
 
virtual void suspendContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now suspended. More...
 
virtual void haltContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now halted. More...
 
int findContext (ThreadContext *tc)
 Given a Thread Context pointer return the thread num. More...
 
virtual ThreadContextgetContext (int tn)
 Given a thread num get tho thread context for it. More...
 
unsigned numContexts ()
 Get the number of thread contexts available. More...
 
ThreadID contextToThread (ContextID cid)
 Convert ContextID to threadID. More...
 
 PARAMS (BaseCPU)
 
 BaseCPU (const Params &params, bool is_checker=false)
 
virtual ~BaseCPU ()
 
void startup () override
 startup() is the final initialization call before simulation. More...
 
void regStats () override
 Callback to set stat parameters. More...
 
void regProbePoints () override
 Register probe points for this object. More...
 
void registerThreadContexts ()
 
void deschedulePowerGatingEvent ()
 
void schedulePowerGatingEvent ()
 
virtual void switchOut ()
 Prepare for another CPU to take over execution. More...
 
virtual void takeOverFrom (BaseCPU *cpu)
 Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...
 
void flushTLBs ()
 Flush all TLBs in the CPU. More...
 
bool switchedOut () const
 Determine if the CPU is switched out. More...
 
virtual void verifyMemoryMode () const
 Verify that the system is in a memory mode supported by the CPU. More...
 
unsigned int cacheLineSize () const
 Get the cache line size of the system. More...
 
virtual void serializeThread (CheckpointOut &cp, ThreadID tid) const
 Serialize a single thread. More...
 
virtual void unserializeThread (CheckpointIn &cp, ThreadID tid)
 Unserialize one thread. More...
 
void scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
 Schedule an event that exits the simulation loops after a predefined number of instructions. More...
 
uint64_t getCurrentInstCount (ThreadID tid)
 Get the number of instructions executed by the specified thread on this CPU. More...
 
void traceFunctions (Addr pc)
 
void armMonitor (ThreadID tid, Addr address)
 
bool mwait (ThreadID tid, PacketPtr pkt)
 
void mwaitAtomic (ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
 
AddressMonitorgetCpuAddrMonitor (ThreadID tid)
 
virtual void probeInstCommit (const StaticInstPtr &inst, Addr pc)
 Helper method to trigger PMU probes for a committed instruction. More...
 
- Public Member Functions inherited from gem5::ClockedObject
 ClockedObject (const ClockedObjectParams &p)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::SimObject
const Paramsparams () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
 
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint. More...
 
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
 
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
 
virtual void memInvalidate ()
 Invalidate the contents of memory buffers. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::EventManager
EventQueueeventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue. More...
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
 
virtual void notifyFork ()
 Notify a child process of a fork. More...
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group. More...
 
virtual ~Group ()
 
virtual void resetStats ()
 Callback to reset stats. More...
 
virtual void preDumpStats ()
 Callback before stats are dumped. More...
 
void addStat (statistics::Info *info)
 Register a stat with this group. More...
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object. More...
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object. More...
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block. More...
 
const InforesolveStat (std::string name) const
 Resolve a stat by its name within this group. More...
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block. More...
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Groupoperator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 
- Public Member Functions inherited from gem5::Clocked
void updateClockPeriod ()
 Update the tick to the current tick. More...
 
Tick clockEdge (Cycles cycles=Cycles(0)) const
 Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...
 
Cycles curCycle () const
 Determine the current cycle, corresponding to a tick aligned to a clock edge. More...
 
Tick nextCycle () const
 Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...
 
uint64_t frequency () const
 
Tick clockPeriod () const
 
double voltage () const
 
Cycles ticksToCycles (Tick t) const
 
Tick cyclesToTicks (Cycles c) const
 
- Public Member Functions inherited from gem5::ExecContext
virtual Fault readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
 Perform an atomic memory read operation. More...
 
virtual Fault initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
 Initiate a timing memory read operation. More...
 
virtual Fault writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0
 For atomic-mode contexts, perform an atomic memory write operation. More...
 
virtual Fault amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
 For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...
 
virtual Fault initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
 For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...
 

Public Attributes

SimpleThreadthread
 
Counter numLoad
 
Counter startNumLoad
 
InstResult unverifiedResult
 
RequestPtr unverifiedReq
 
uint8_t * unverifiedMemData
 
bool changedPC
 
bool willChangePC
 
TheISA::PCState newPCState
 
bool exitOnError
 
bool updateOnError
 
bool warnOnlyOnLoadError
 
InstSeqNum youngestSN
 
- Public Attributes inherited from gem5::BaseCPU
ThreadID numThreads
 Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...
 
Systemsystem
 
gem5::BaseCPU::BaseCPUStats baseStats
 
Cycles syscallRetryLatency
 
- Public Attributes inherited from gem5::ClockedObject
PowerStatepowerState
 

Protected Attributes

RequestorID requestorId
 id attached to all issued requests More...
 
const RegIndex zeroReg
 
std::vector< Process * > workload
 
SystemsystemPtr
 
RequestPorticachePort
 
RequestPortdcachePort
 
ThreadContexttc
 
BaseMMUmmu
 
std::queue< InstResultresult
 
StaticInstPtr curStaticInst
 
StaticInstPtr curMacroStaticInst
 
Counter numInst
 
Counter startNumInst
 
std::queue< int > miscRegIdxs
 
- Protected Attributes inherited from gem5::BaseCPU
Tick instCnt
 Instruction count used for SPARC misc register. More...
 
int _cpuId
 
const uint32_t _socketId
 Each cpu will have a socket ID that corresponds to its physical location in the system. More...
 
RequestorID _instRequestorId
 instruction side request id that must be placed in all requests More...
 
RequestorID _dataRequestorId
 data side request id that must be placed in all requests More...
 
uint32_t _taskId
 An intrenal representation of a task identifier within gem5. More...
 
uint32_t _pid
 The current OS process ID that is executing on this processor. More...
 
bool _switchedOut
 Is the CPU switched out or active? More...
 
const unsigned int _cacheLineSize
 Cache the cache line size that we get from the system. More...
 
std::vector< BaseInterrupts * > interrupts
 
std::vector< ThreadContext * > threadContexts
 
Trace::InstTracertracer
 
Cycles previousCycle
 
CPUState previousState
 
const Cycles pwrGatingLatency
 
const bool powerGatingOnIdle
 
EventFunctionWrapper enterPwrGatingEvent
 
probing::PMUUPtr ppRetiredInsts
 Instruction commit probe point. More...
 
probing::PMUUPtr ppRetiredInstsPC
 
probing::PMUUPtr ppRetiredLoads
 Retired load instructions. More...
 
probing::PMUUPtr ppRetiredStores
 Retired store instructions. More...
 
probing::PMUUPtr ppRetiredBranches
 Retired branches (any type) More...
 
probing::PMUUPtr ppAllCycles
 CPU cycle counter even if any thread Context is suspended. More...
 
probing::PMUUPtr ppActiveCycles
 CPU cycle counter, only counts if any thread contexts is active. More...
 
ProbePointArg< bool > * ppSleeping
 ProbePoint that signals transitions of threadContexts sets. More...
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters. More...
 
- Protected Attributes inherited from gem5::EventManager
EventQueueeventq
 A pointer to this object's event queue. More...
 

Additional Inherited Members

- Public Types inherited from gem5::ClockedObject
using Params = ClockedObjectParams
 Parameters of ClockedObject. More...
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 
- Static Public Member Functions inherited from gem5::BaseCPU
static int numSimulatedCPUs ()
 
static Counter numSimulatedInsts ()
 
static Counter numSimulatedOps ()
 
- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system. More...
 
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
static SimObjectResolvergetSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 
- Static Public Attributes inherited from gem5::BaseCPU
static const uint32_t invldPid = std::numeric_limits<uint32_t>::max()
 Invalid or unknown Pid. More...
 
- Protected Types inherited from gem5::BaseCPU
enum  CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }
 
- Protected Member Functions inherited from gem5::BaseCPU
void updateCycleCounters (CPUState state)
 base method keeping track of cycle progression More...
 
void enterPwrGating ()
 
probing::PMUUPtr pmuProbePoint (const char *name)
 Helper method to instantiate probe points belonging to this object. More...
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
virtual void drainResume ()
 Resume execution after a successful drain. More...
 
void signalDrainDone () const
 Signal that an object is drained. More...
 
- Protected Member Functions inherited from gem5::Clocked
 Clocked (ClockDomain &clk_domain)
 Create a clocked object and set the clock domain based on the parameters. More...
 
 Clocked (Clocked &)=delete
 
Clockedoperator= (Clocked &)=delete
 
virtual ~Clocked ()
 Virtual destructor due to inheritance. More...
 
void resetClock () const
 Reset the object's clock using the current global tick value. More...
 
virtual void clockPeriodUpdated ()
 A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...
 
- Static Protected Attributes inherited from gem5::BaseCPU
static std::unique_ptr< GlobalStatsglobalStats
 Pointer to the global stat structure. More...
 

Detailed Description

CheckerCPU class.

Dynamically verifies instructions as they are completed by making sure that the instruction and its results match the independent execution of the benchmark inside the checker. The checker verifies instructions in order, regardless of the order in which instructions complete. There are certain results that can not be verified, specifically the result of a store conditional or the values of uncached accesses. In these cases, and with instructions marked as "IsUnverifiable", the checker assumes that the value from the main CPU's execution is correct and simply copies that value. It provides a CheckerThreadContext (see checker/thread_context.hh) that provides hooks for updating the Checker's state through any ThreadContext accesses. This allows the checker to be able to correctly verify instructions, even with external accesses to the ThreadContext that change state.

Definition at line 84 of file cpu.hh.

Constructor & Destructor Documentation

◆ CheckerCPU()

gem5::CheckerCPU::CheckerCPU ( const Params p)

◆ ~CheckerCPU()

gem5::CheckerCPU::~CheckerCPU ( )
virtual

Definition at line 92 of file cpu.cc.

Member Function Documentation

◆ amoMem()

Fault gem5::CheckerCPU::amoMem ( Addr  addr,
uint8_t *  data,
unsigned  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
inlineoverride

Definition at line 513 of file cpu.hh.

References panic.

◆ armMonitor()

void gem5::CheckerCPU::armMonitor ( Addr  address)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 470 of file cpu.hh.

References gem5::BaseCPU::armMonitor().

◆ checkFlags()

bool gem5::CheckerCPU::checkFlags ( const RequestPtr unverified_req,
Addr  vAddr,
Addr  pAddr,
int  flags 
)

Checks if the flags set by the Checker and Checkee match.

Definition at line 356 of file cpu.cc.

Referenced by readMem(), and writeMem().

◆ demapPage()

void gem5::CheckerCPU::demapPage ( Addr  vaddr,
uint64_t  asn 
)
inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements gem5::ExecContext.

Definition at line 464 of file cpu.hh.

References gem5::BaseMMU::demapPage(), mmu, and gem5::MipsISA::vaddr.

◆ dumpAndExit()

void gem5::CheckerCPU::dumpAndExit ( )

◆ genMemFragmentRequest()

RequestPtr gem5::CheckerCPU::genMemFragmentRequest ( Addr  frag_addr,
int  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable,
int &  frag_size,
int &  size_left 
) const

Helper function used to generate the request for a single fragment of a memory access.

Takes care of setting up the appropriate byte-enable mask for the fragment, given the mask for the entire memory access.

Parameters
frag_addrStart address of the fragment.
sizeTotal size of the memory access in bytes.
flagsRequest flags.
byte_enableByte-enable mask for the entire memory access.
[out]frag_sizeFragment size.
[in,out]size_leftSize left to be processed in the memory access.
Returns
Pointer to the allocated Request, nullptr if the byte-enable mask is all-false for the fragment.

Definition at line 140 of file cpu.cc.

References gem5::addrBlockOffset(), gem5::BaseCPU::cacheLineSize(), gem5::ThreadContext::contextId(), gem5::isAnyActiveElement(), gem5::SimpleThread::pcState(), requestorId, tc, and thread.

Referenced by readMem(), and writeMem().

◆ getAddrMonitor()

AddressMonitor* gem5::CheckerCPU::getAddrMonitor ( )
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 479 of file cpu.hh.

References gem5::BaseCPU::getCpuAddrMonitor().

◆ getDataPort()

Port& gem5::CheckerCPU::getDataPort ( )
inlineoverridevirtual

Purely virtual method that returns a reference to the data port.

All subclasses must implement this method.

Returns
a reference to the data port

Implements gem5::BaseCPU.

Definition at line 106 of file cpu.hh.

References dcachePort.

◆ getHtmTransactionalDepth()

uint64_t gem5::CheckerCPU::getHtmTransactionalDepth ( ) const
inlineoverridevirtual

◆ getHtmTransactionUid()

uint64_t gem5::CheckerCPU::getHtmTransactionUid ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 362 of file cpu.hh.

References panic.

◆ getInstPort()

Port& gem5::CheckerCPU::getInstPort ( )
inlineoverridevirtual

Purely virtual method that returns a reference to the instruction port.

All subclasses must implement this method.

Returns
a reference to the instruction port

Implements gem5::BaseCPU.

Definition at line 115 of file cpu.hh.

References icachePort.

◆ getMMUPtr()

BaseMMU* gem5::CheckerCPU::getMMUPtr ( )
inline

Definition at line 154 of file cpu.hh.

References mmu.

Referenced by gem5::BaseCPU::flushTLBs(), and gem5::BaseCPU::takeOverFrom().

◆ getWritableVecPredRegOperand()

TheISA::VecPredRegContainer& gem5::CheckerCPU::getWritableVecPredRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Gets destination predicate register operand for modification.

Implements gem5::ExecContext.

Definition at line 238 of file cpu.hh.

References gem5::SimpleThread::getWritableVecPredReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecPredRegClass.

◆ getWritableVecRegOperand()

TheISA::VecRegContainer& gem5::CheckerCPU::getWritableVecRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Read destination vector register operand for modification.

Implements gem5::ExecContext.

Definition at line 215 of file cpu.hh.

References gem5::SimpleThread::getWritableVecReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecRegClass.

◆ handleError()

void gem5::CheckerCPU::handleError ( )
inline

Definition at line 530 of file cpu.hh.

References dumpAndExit(), and exitOnError.

Referenced by readMem(), gem5::Checker< gem5::RefCountingPtr >::verify(), and writeMem().

◆ inHtmTransactionalState()

bool gem5::CheckerCPU::inHtmTransactionalState ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 383 of file cpu.hh.

References getHtmTransactionalDepth().

◆ init()

void gem5::CheckerCPU::init ( )
overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::BaseCPU.

Definition at line 59 of file cpu.cc.

References gem5::ThreadContext::getIsaPtr(), gem5::System::getRequestorId(), requestorId, gem5::BaseISA::setThreadContext(), systemPtr, and tc.

◆ initiateHtmCmd()

Fault gem5::CheckerCPU::initiateHtmCmd ( Request::Flags  flags)
inlineoverridevirtual

Initiate an HTM command, e.g.

tell Ruby we're starting/stopping a transaction

Implements gem5::ExecContext.

Definition at line 376 of file cpu.hh.

References gem5::NoFault, and panic.

◆ instAddr()

Addr gem5::CheckerCPU::instAddr ( )
inline

Definition at line 403 of file cpu.hh.

References gem5::SimpleThread::instAddr(), and thread.

◆ microPC()

MicroPC gem5::CheckerCPU::microPC ( )
inline

Definition at line 405 of file cpu.hh.

References gem5::SimpleThread::microPC(), and thread.

◆ mwait()

bool gem5::CheckerCPU::mwait ( PacketPtr  pkt)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 471 of file cpu.hh.

References gem5::BaseCPU::mwait().

◆ mwaitAtomic()

void gem5::CheckerCPU::mwaitAtomic ( ThreadContext tc)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 474 of file cpu.hh.

References gem5::SimpleThread::mmu, gem5::BaseCPU::mwaitAtomic(), tc, and thread.

◆ newHtmTransactionUid()

uint64_t gem5::CheckerCPU::newHtmTransactionUid ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 369 of file cpu.hh.

References panic.

◆ nextInstAddr()

Addr gem5::CheckerCPU::nextInstAddr ( )
inline

Definition at line 404 of file cpu.hh.

References gem5::SimpleThread::nextInstAddr(), and thread.

◆ PARAMS()

gem5::CheckerCPU::PARAMS ( CheckerCPU  )

◆ pcState() [1/2]

TheISA::PCState gem5::CheckerCPU::pcState ( ) const
inlineoverridevirtual

◆ pcState() [2/2]

void gem5::CheckerCPU::pcState ( const TheISA::PCState &  val)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 397 of file cpu.hh.

References DPRINTF, gem5::SimpleThread::pcState(), thread, and gem5::X86ISA::val.

◆ readCCRegOperand()

RegVal gem5::CheckerCPU::readCCRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

◆ readFloatRegOperandBits()

RegVal gem5::CheckerCPU::readFloatRegOperandBits ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Reads a floating point register in its binary format, instead of by value.

Implements gem5::ExecContext.

Definition at line 193 of file cpu.hh.

References gem5::FloatRegClass, gem5::SimpleThread::readFloatReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readIntRegOperand()

RegVal gem5::CheckerCPU::readIntRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Reads an integer register.

Implements gem5::ExecContext.

Definition at line 185 of file cpu.hh.

References gem5::IntRegClass, gem5::SimpleThread::readIntReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readMem()

Fault gem5::CheckerCPU::readMem ( Addr  addr,
uint8_t *  data,
unsigned  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable 
)
override

◆ readMemAccPredicate()

bool gem5::CheckerCPU::readMemAccPredicate ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 350 of file cpu.hh.

References gem5::SimpleThread::readMemAccPredicate(), and thread.

◆ readMiscReg()

RegVal gem5::CheckerCPU::readMiscReg ( int  misc_reg)
inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements gem5::ExecContext.

Definition at line 415 of file cpu.hh.

References gem5::SimpleThread::readMiscReg(), and thread.

◆ readMiscRegNoEffect()

RegVal gem5::CheckerCPU::readMiscRegNoEffect ( int  misc_reg) const
inline

Definition at line 409 of file cpu.hh.

References gem5::SimpleThread::readMiscRegNoEffect(), and thread.

◆ readMiscRegOperand()

RegVal gem5::CheckerCPU::readMiscRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

◆ readPredicate()

bool gem5::CheckerCPU::readPredicate ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 341 of file cpu.hh.

References gem5::SimpleThread::readPredicate(), and thread.

◆ readStCondFailures()

unsigned int gem5::CheckerCPU::readStCondFailures ( ) const
inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 520 of file cpu.hh.

References gem5::SimpleThread::readStCondFailures(), and thread.

◆ readVecElemOperand()

TheISA::VecElem gem5::CheckerCPU::readVecElemOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Vector Elem Interfaces.

Reads an element of a vector register.

Implements gem5::ExecContext.

Definition at line 223 of file cpu.hh.

References gem5::SimpleThread::readVecElem(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readVecPredRegOperand()

const TheISA::VecPredRegContainer& gem5::CheckerCPU::readVecPredRegOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Predicate registers interface.

Reads source predicate register operand.

Implements gem5::ExecContext.

Definition at line 230 of file cpu.hh.

References gem5::SimpleThread::readVecPredReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecPredRegClass.

◆ readVecRegOperand()

const TheISA::VecRegContainer& gem5::CheckerCPU::readVecRegOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Read source vector register operand.

Implements gem5::ExecContext.

Definition at line 204 of file cpu.hh.

References gem5::SimpleThread::readVecReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecRegClass.

◆ recordPCChange()

void gem5::CheckerCPU::recordPCChange ( const TheISA::PCState &  val)
inline

Definition at line 457 of file cpu.hh.

References changedPC, newPCState, and gem5::X86ISA::val.

Referenced by gem5::CheckerThreadContext< TC >::pcState().

◆ serialize()

void gem5::CheckerCPU::serialize ( CheckpointOut cp) const
overridevirtual

Serialize this object to the given output stream.

Note
CPU models should normally overload the serializeThread() method instead of the serialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.
Parameters
cpThe stream to serialize to.

Reimplemented from gem5::BaseCPU.

Definition at line 130 of file cpu.cc.

◆ setCCRegOperand()

void gem5::CheckerCPU::setCCRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

◆ setDcachePort()

void gem5::CheckerCPU::setDcachePort ( RequestPort dcache_port)

Definition at line 124 of file cpu.cc.

References dcachePort.

◆ setFloatRegOperandBits()

void gem5::CheckerCPU::setFloatRegOperandBits ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Sets the bits of a floating point register of single width to a binary value.

Implements gem5::ExecContext.

Definition at line 295 of file cpu.hh.

References gem5::FloatRegClass, gem5::X86ISA::reg, gem5::SimpleThread::setFloatReg(), setScalarResult(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setIcachePort()

void gem5::CheckerCPU::setIcachePort ( RequestPort icache_port)

Definition at line 118 of file cpu.cc.

References icachePort.

◆ setIntRegOperand()

void gem5::CheckerCPU::setIntRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Sets an integer register to a value.

Implements gem5::ExecContext.

Definition at line 286 of file cpu.hh.

References gem5::IntRegClass, gem5::X86ISA::reg, gem5::SimpleThread::setIntReg(), setScalarResult(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setMemAccPredicate()

void gem5::CheckerCPU::setMemAccPredicate ( bool  val)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 356 of file cpu.hh.

References gem5::SimpleThread::setMemAccPredicate(), thread, and gem5::X86ISA::val.

◆ setMiscReg()

void gem5::CheckerCPU::setMiscReg ( int  misc_reg,
RegVal  val 
)
inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements gem5::ExecContext.

Definition at line 430 of file cpu.hh.

References DPRINTF, miscRegIdxs, gem5::SimpleThread::setMiscReg(), thread, and gem5::X86ISA::val.

Referenced by setMiscRegOperand().

◆ setMiscRegNoEffect()

void gem5::CheckerCPU::setMiscRegNoEffect ( int  misc_reg,
RegVal  val 
)
inline

◆ setMiscRegOperand()

void gem5::CheckerCPU::setMiscRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

◆ setPredicate()

void gem5::CheckerCPU::setPredicate ( bool  val)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 344 of file cpu.hh.

References gem5::SimpleThread::setPredicate(), thread, and gem5::X86ISA::val.

◆ setScalarResult()

template<typename T >
void gem5::CheckerCPU::setScalarResult ( T &&  t)
inline

Definition at line 255 of file cpu.hh.

References result, gem5::InstResult::Scalar, and gem5::ArmISA::t.

Referenced by setCCRegOperand(), setFloatRegOperandBits(), and setIntRegOperand().

◆ setStCondFailures()

void gem5::CheckerCPU::setStCondFailures ( unsigned int  sc_failures)
inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 524 of file cpu.hh.

◆ setSystem()

void gem5::CheckerCPU::setSystem ( System system)

◆ setVecElemOperand()

void gem5::CheckerCPU::setVecElemOperand ( const StaticInst si,
int  idx,
const TheISA::VecElem  val 
)
inlineoverridevirtual

Sets a vector register to a value.

Implements gem5::ExecContext.

Definition at line 323 of file cpu.hh.

References gem5::X86ISA::reg, gem5::SimpleThread::setVecElem(), setVecElemResult(), gem5::ArmISA::si, thread, gem5::X86ISA::val, and gem5::VecElemClass.

◆ setVecElemResult()

template<typename T >
void gem5::CheckerCPU::setVecElemResult ( T &&  t)
inline

Definition at line 271 of file cpu.hh.

References result, gem5::ArmISA::t, and gem5::InstResult::VecElem.

Referenced by setVecElemOperand().

◆ setVecPredRegOperand()

void gem5::CheckerCPU::setVecPredRegOperand ( const StaticInst si,
int  idx,
const TheISA::VecPredRegContainer &  val 
)
inlineoverridevirtual

Sets a destination predicate register operand to a value.

Implements gem5::ExecContext.

Definition at line 332 of file cpu.hh.

References gem5::X86ISA::reg, gem5::SimpleThread::setVecPredReg(), setVecPredResult(), gem5::ArmISA::si, thread, gem5::X86ISA::val, and gem5::VecPredRegClass.

◆ setVecPredResult()

template<typename T >
void gem5::CheckerCPU::setVecPredResult ( T &&  t)
inline

Definition at line 279 of file cpu.hh.

References result, gem5::ArmISA::t, and gem5::InstResult::VecPredReg.

Referenced by setVecPredRegOperand().

◆ setVecRegOperand()

void gem5::CheckerCPU::setVecRegOperand ( const StaticInst si,
int  idx,
const TheISA::VecRegContainer &  val 
)
inlineoverridevirtual

Sets a destination vector register operand to a value.

Implements gem5::ExecContext.

Definition at line 313 of file cpu.hh.

References gem5::X86ISA::reg, gem5::SimpleThread::setVecReg(), setVecResult(), gem5::ArmISA::si, thread, gem5::X86ISA::val, and gem5::VecRegClass.

◆ setVecResult()

template<typename T >
void gem5::CheckerCPU::setVecResult ( T &&  t)
inline

Definition at line 263 of file cpu.hh.

References result, gem5::ArmISA::t, and gem5::InstResult::VecReg.

Referenced by setVecRegOperand().

◆ tcBase()

ThreadContext* gem5::CheckerCPU::tcBase ( ) const
inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements gem5::ExecContext.

Definition at line 541 of file cpu.hh.

References tc.

◆ threadBase()

SimpleThread* gem5::CheckerCPU::threadBase ( )
inline

Definition at line 542 of file cpu.hh.

References thread.

◆ totalInsts()

virtual Counter gem5::CheckerCPU::totalInsts ( ) const
inlineoverridevirtual

Implements gem5::BaseCPU.

Definition at line 156 of file cpu.hh.

◆ totalOps()

virtual Counter gem5::CheckerCPU::totalOps ( ) const
inlineoverridevirtual

Implements gem5::BaseCPU.

Definition at line 161 of file cpu.hh.

◆ unserialize()

void gem5::CheckerCPU::unserialize ( CheckpointIn cp)
overridevirtual

Reconstruct the state of this object from a checkpoint.

Note
CPU models should normally overload the unserializeThread() method instead of the unserialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.
Parameters
cpThe checkpoint use.

Reimplemented from gem5::BaseCPU.

Definition at line 135 of file cpu.cc.

◆ wakeup()

void gem5::CheckerCPU::wakeup ( ThreadID  tid)
inlineoverridevirtual

Implements gem5::BaseCPU.

Definition at line 527 of file cpu.hh.

◆ writeMem()

Fault gem5::CheckerCPU::writeMem ( uint8_t *  data,
unsigned  size,
Addr  addr,
Request::Flags  flags,
uint64_t *  res,
const std::vector< bool > &  byte_enable 
)
override

Member Data Documentation

◆ changedPC

bool gem5::CheckerCPU::changedPC

Definition at line 548 of file cpu.hh.

Referenced by CheckerCPU(), and recordPCChange().

◆ curMacroStaticInst

StaticInstPtr gem5::CheckerCPU::curMacroStaticInst
protected

Definition at line 141 of file cpu.hh.

Referenced by CheckerCPU().

◆ curStaticInst

StaticInstPtr gem5::CheckerCPU::curStaticInst
protected

Definition at line 140 of file cpu.hh.

Referenced by CheckerCPU().

◆ dcachePort

RequestPort* gem5::CheckerCPU::dcachePort
protected

Definition at line 130 of file cpu.hh.

Referenced by getDataPort(), readMem(), and setDcachePort().

◆ exitOnError

bool gem5::CheckerCPU::exitOnError

◆ icachePort

RequestPort* gem5::CheckerCPU::icachePort
protected

Definition at line 129 of file cpu.hh.

Referenced by getInstPort(), and setIcachePort().

◆ miscRegIdxs

std::queue<int> gem5::CheckerCPU::miscRegIdxs
protected

Definition at line 147 of file cpu.hh.

Referenced by setMiscReg(), and setMiscRegNoEffect().

◆ mmu

BaseMMU* gem5::CheckerCPU::mmu
protected

Definition at line 134 of file cpu.hh.

Referenced by CheckerCPU(), demapPage(), getMMUPtr(), readMem(), setSystem(), and writeMem().

◆ newPCState

TheISA::PCState gem5::CheckerCPU::newPCState

Definition at line 550 of file cpu.hh.

Referenced by recordPCChange().

◆ numInst

Counter gem5::CheckerCPU::numInst
protected

Definition at line 144 of file cpu.hh.

Referenced by CheckerCPU().

◆ numLoad

Counter gem5::CheckerCPU::numLoad

Definition at line 167 of file cpu.hh.

Referenced by CheckerCPU().

◆ requestorId

RequestorID gem5::CheckerCPU::requestorId
protected

id attached to all issued requests

Definition at line 88 of file cpu.hh.

Referenced by genMemFragmentRequest(), and init().

◆ result

std::queue<InstResult> gem5::CheckerCPU::result
protected

Definition at line 138 of file cpu.hh.

Referenced by setScalarResult(), setVecElemResult(), setVecPredResult(), and setVecResult().

◆ startNumInst

Counter gem5::CheckerCPU::startNumInst
protected

Definition at line 145 of file cpu.hh.

Referenced by CheckerCPU().

◆ startNumLoad

Counter gem5::CheckerCPU::startNumLoad

Definition at line 168 of file cpu.hh.

Referenced by CheckerCPU().

◆ systemPtr

System* gem5::CheckerCPU::systemPtr
protected

Definition at line 127 of file cpu.hh.

Referenced by init(), and setSystem().

◆ tc

ThreadContext* gem5::CheckerCPU::tc
protected

Definition at line 132 of file cpu.hh.

Referenced by genMemFragmentRequest(), init(), mwaitAtomic(), readMem(), setSystem(), tcBase(), and writeMem().

◆ thread

SimpleThread* gem5::CheckerCPU::thread

◆ unverifiedMemData

uint8_t* gem5::CheckerCPU::unverifiedMemData

Definition at line 546 of file cpu.hh.

Referenced by readMem(), and writeMem().

◆ unverifiedReq

RequestPtr gem5::CheckerCPU::unverifiedReq

Definition at line 545 of file cpu.hh.

Referenced by readMem(), and writeMem().

◆ unverifiedResult

InstResult gem5::CheckerCPU::unverifiedResult

Definition at line 544 of file cpu.hh.

◆ updateOnError

bool gem5::CheckerCPU::updateOnError

Definition at line 552 of file cpu.hh.

Referenced by CheckerCPU(), and gem5::Checker< gem5::RefCountingPtr >::handleError().

◆ warnOnlyOnLoadError

bool gem5::CheckerCPU::warnOnlyOnLoadError

Definition at line 553 of file cpu.hh.

Referenced by CheckerCPU().

◆ willChangePC

bool gem5::CheckerCPU::willChangePC

Definition at line 549 of file cpu.hh.

Referenced by CheckerCPU().

◆ workload

std::vector<Process*> gem5::CheckerCPU::workload
protected

Definition at line 125 of file cpu.hh.

Referenced by CheckerCPU(), and setSystem().

◆ youngestSN

InstSeqNum gem5::CheckerCPU::youngestSN

Definition at line 555 of file cpu.hh.

Referenced by CheckerCPU().

◆ zeroReg

const RegIndex gem5::CheckerCPU::zeroReg
protected

Definition at line 90 of file cpu.hh.


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:27:23 for gem5 by doxygen 1.8.17