#include <cpu.hh>

Inheritance diagram for gem5::CheckerCPU:

Public Member Functions
void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

	PARAMS (CheckerCPU)

	CheckerCPU (const Params &p)

virtual	~CheckerCPU ()

void	setSystem (System *system)

void	setIcachePort (RequestPort *icache_port)

void	setDcachePort (RequestPort *dcache_port)

Port &	getDataPort () override
	Purely virtual method that returns a reference to the data port. More...

Port &	getInstPort () override
	Purely virtual method that returns a reference to the instruction port. More...

BaseMMU *	getMMUPtr ()

virtual Counter	totalInsts () const override

virtual Counter	totalOps () const override

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

RegVal	getRegOperand (const StaticInst *si, int idx) override

void	getRegOperand (const StaticInst si, int idx, void val) override

void *	getWritableRegOperand (const StaticInst *si, int idx) override

void	setRegOperand (const StaticInst *si, int idx, RegVal val) override

void	setRegOperand (const StaticInst si, int idx, const void val) override

bool	readPredicate () const override

void	setPredicate (bool val) override

bool	readMemAccPredicate () const override

void	setMemAccPredicate (bool val) override

uint64_t	getHtmTransactionUid () const override

uint64_t	newHtmTransactionUid () const override

Fault	initiateMemMgmtCmd (Request::Flags flags) override
	Initiate a memory management command with no valid address. More...

bool	inHtmTransactionalState () const override

uint64_t	getHtmTransactionalDepth () const override

const PCStateBase &	pcState () const override

void	pcState (const PCStateBase &val) override

RegVal	readMiscRegNoEffect (int misc_reg) const

RegVal	readMiscReg (int misc_reg) override
	Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...

void	setMiscRegNoEffect (int misc_reg, RegVal val)

void	setMiscReg (int misc_reg, RegVal val) override
	Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...

RegVal	readMiscRegOperand (const StaticInst *si, int idx) override

void	setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override

void	recordPCChange (const PCStateBase &val)

void	demapPage (Addr vaddr, uint64_t asn) override
	Invalidate a page in the DTLB and ITLB. More...

void	armMonitor (Addr address) override

bool	mwait (PacketPtr pkt) override

void	mwaitAtomic (ThreadContext *tc) override

AddressMonitor *	getAddrMonitor () override

RequestPtr	genMemFragmentRequest (Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
	Helper function used to generate the request for a single fragment of a memory access. More...

Fault	readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override

Fault	writeMem (uint8_t data, unsigned size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable) override

Fault	amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override

unsigned int	readStCondFailures () const override
	Returns the number of consecutive store conditional failures. More...

void	setStCondFailures (unsigned int sc_failures) override
	Sets the number of consecutive store conditional failures. More...

void	wakeup (ThreadID tid) override

void	handleError ()

bool	checkFlags (const RequestPtr &unverified_req, Addr vAddr, Addr pAddr, int flags)
	Checks if the flags set by the Checker and Checkee match. More...

void	dumpAndExit ()

ThreadContext *	tcBase () const override
	Returns a pointer to the ThreadContext. More...

SimpleThread *	threadBase ()

Public Member Functions inherited from gem5::BaseCPU
int	cpuId () const
	Reads this CPU's ID. More...

uint32_t	socketId () const
	Reads this CPU's Socket ID. More...

RequestorID	dataRequestorId () const
	Reads this CPU's unique data requestor ID. More...

RequestorID	instRequestorId () const
	Reads this CPU's unique instruction requestor ID. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU. More...

uint32_t	taskId () const
	Get cpu task id. More...

void	taskId (uint32_t id)
	Set cpu task id. More...

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadID tid) const

trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer. More...

virtual void	activateContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now active. More...

virtual void	suspendContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now suspended. More...

virtual void	haltContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now halted. More...

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num. More...

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it. More...

unsigned	numContexts ()
	Get the number of thread contexts available. More...

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID. More...

	PARAMS (BaseCPU)

	BaseCPU (const Params &params, bool is_checker=false)

virtual	~BaseCPU ()

void	startup () override
	startup() is the final initialization call before simulation. More...

void	regStats () override
	Callback to set stat parameters. More...

void	regProbePoints () override
	Register probe points for this object. More...

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

virtual void	switchOut ()
	Prepare for another CPU to take over execution. More...

virtual void	takeOverFrom (BaseCPU *cpu)
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...

void	flushTLBs ()
	Flush all TLBs in the CPU. More...

bool	switchedOut () const
	Determine if the CPU is switched out. More...

virtual void	verifyMemoryMode () const
	Verify that the system is in a memory mode supported by the CPU. More...

unsigned int	cacheLineSize () const
	Get the cache line size of the system. More...

virtual void	serializeThread (CheckpointOut &cp, ThreadID tid) const
	Serialize a single thread. More...

virtual void	unserializeThread (CheckpointIn &cp, ThreadID tid)
	Unserialize one thread. More...

void	scheduleInstStop (ThreadID tid, Counter insts, std::string cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions. More...

void	scheduleSimpointsInstStop (std::vector< Counter > inst_starts)
	Schedule simpoint events using the scheduleInstStop function. More...

void	scheduleInstStopAnyThread (Counter max_insts)
	Schedule an exit event when any threads in the core reach the max_insts instructions using the scheduleInstStop function. More...

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU. More...

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseMMU mmu)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

virtual void	htmSendAbortSignal (ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)
	This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away. More...

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction. More...

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (statistics::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Public Member Functions inherited from gem5::ExecContext
virtual Fault	readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
	Perform an atomic memory read operation. More...

virtual Fault	initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
	Initiate a timing memory read operation. More...

virtual Fault	writeMem (uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable)=0
	For atomic-mode contexts, perform an atomic memory write operation. More...

virtual Fault	amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...

virtual Fault	initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...

Public Attributes
SimpleThread *	thread

Counter	numLoad

Counter	startNumLoad

InstResult	unverifiedResult

RequestPtr	unverifiedReq

uint8_t *	unverifiedMemData

bool	changedPC

bool	willChangePC

std::unique_ptr< PCStateBase >	newPCState

bool	exitOnError

bool	updateOnError

bool	warnOnlyOnLoadError

InstSeqNum	youngestSN

Public Attributes inherited from gem5::BaseCPU
ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...

System *	system

gem5::BaseCPU::BaseCPUStats	baseStats

Cycles	syscallRetryLatency

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Protected Attributes
RequestorID	requestorId
	id attached to all issued requests More...

std::vector< Process * >	workload

System *	systemPtr

RequestPort *	icachePort

RequestPort *	dcachePort

ThreadContext *	tc

BaseMMU *	mmu

std::queue< InstResult >	result

StaticInstPtr	curStaticInst

StaticInstPtr	curMacroStaticInst

Counter	numInst

Counter	startNumInst

std::queue< int >	miscRegIdxs

Protected Attributes inherited from gem5::BaseCPU
Tick	instCnt
	Instruction count used for SPARC misc register. More...

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system. More...

RequestorID	_instRequestorId
	instruction side request id that must be placed in all requests More...

RequestorID	_dataRequestorId
	data side request id that must be placed in all requests More...

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5. More...

uint32_t	_pid
	The current OS process ID that is executing on this processor. More...

bool	_switchedOut
	Is the CPU switched out or active? More...

const unsigned int	_cacheLineSize
	Cache the cache line size that we get from the system. More...

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

probing::PMUUPtr	ppRetiredInsts
	Instruction commit probe point. More...

probing::PMUUPtr	ppRetiredInstsPC

probing::PMUUPtr	ppRetiredLoads
	Retired load instructions. More...

probing::PMUUPtr	ppRetiredStores
	Retired store instructions. More...

probing::PMUUPtr	ppRetiredBranches
	Retired branches (any type) More...

probing::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended. More...

probing::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active. More...

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets. More...

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Additional Inherited Members
Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject. More...

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Static Public Member Functions inherited from gem5::BaseCPU
static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Static Public Attributes inherited from gem5::BaseCPU
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid. More...

Protected Types inherited from gem5::BaseCPU
enum	CPUState { CPU_STATE_ON , CPU_STATE_SLEEP , CPU_STATE_WAKEUP }

Protected Member Functions inherited from gem5::BaseCPU
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression More...

void	enterPwrGating ()

probing::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object. More...

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Static Protected Attributes inherited from gem5::BaseCPU
static std::unique_ptr< GlobalStats >	globalStats
	Pointer to the global stat structure. More...

Detailed Description

CheckerCPU class.

Dynamically verifies instructions as they are completed by making sure that the instruction and its results match the independent execution of the benchmark inside the checker. The checker verifies instructions in order, regardless of the order in which instructions complete. There are certain results that can not be verified, specifically the result of a store conditional or the values of uncached accesses. In these cases, and with instructions marked as "IsUnverifiable", the checker assumes that the value from the main CPU's execution is correct and simply copies that value. It provides a CheckerThreadContext (see checker/thread_context.hh) that provides hooks for updating the Checker's state through any ThreadContext accesses. This allows the checker to be able to correctly verify instructions, even with external accesses to the ThreadContext that change state.

Definition at line 84 of file cpu.hh.

Constructor & Destructor Documentation

◆ CheckerCPU()

gem5::CheckerCPU::CheckerCPU ( const Params & p )

Definition at line 65 of file cpu.cc.

References changedPC, curMacroStaticInst, curStaticInst, exitOnError, mmu, numInst, numLoad, gem5::VegaISA::p, startNumInst, startNumLoad, updateOnError, warnOnlyOnLoadError, willChangePC, workload, and youngestSN.

◆ ~CheckerCPU()

gem5::CheckerCPU::~CheckerCPU ( )

virtual

Definition at line 91 of file cpu.cc.

Member Function Documentation

◆ amoMem()

Fault gem5::CheckerCPU::amoMem	(	Addr	addr,
		uint8_t *	data,
		unsigned	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlineoverride

Definition at line 394 of file cpu.hh.

References panic.

◆ armMonitor()

void gem5::CheckerCPU::armMonitor ( Addr address )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 349 of file cpu.hh.

References gem5::BaseCPU::armMonitor().

◆ checkFlags()

bool gem5::CheckerCPU::checkFlags	(	const RequestPtr &	unverified_req,
		Addr	vAddr,
		Addr	pAddr,
		int	flags
	)

Checks if the flags set by the Checker and Checkee match.

Definition at line 356 of file cpu.cc.

References flags.

Referenced by readMem(), and writeMem().

◆ demapPage()

void gem5::CheckerCPU::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements gem5::ExecContext.

Definition at line 343 of file cpu.hh.

References gem5::BaseMMU::demapPage(), mmu, and gem5::MipsISA::vaddr.

◆ dumpAndExit()

void gem5::CheckerCPU::dumpAndExit ( )

Definition at line 373 of file cpu.cc.

References gem5::curTick(), panic, gem5::SimpleThread::pcState(), thread, and warn.

Referenced by gem5::Checker< DynInstPtr >::dumpAndExit(), handleError(), and gem5::Checker< DynInstPtr >::handleError().

◆ genMemFragmentRequest()

RequestPtr gem5::CheckerCPU::genMemFragmentRequest	(	Addr	frag_addr,
		int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable,
		int &	frag_size,
		int &	size_left
	)		const

Helper function used to generate the request for a single fragment of a memory access.

Takes care of setting up the appropriate byte-enable mask for the fragment, given the mask for the entire memory access.

Parameters

	frag_addr	Start address of the fragment.
	size	Total size of the memory access in bytes.
	flags	Request flags.
	byte_enable	Byte-enable mask for the entire memory access.
[out]	frag_size	Fragment size.
[in,out]	size_left	Size left to be processed in the memory access.

Returns: Pointer to the allocated Request, nullptr if the byte-enable mask is all-false for the fragment.

Definition at line 140 of file cpu.cc.

References gem5::addrBlockOffset(), gem5::BaseCPU::cacheLineSize(), gem5::ThreadContext::contextId(), flags, gem5::PCStateBase::instAddr(), gem5::isAnyActiveElement(), gem5::SimpleThread::pcState(), requestorId, tc, and thread.

Referenced by readMem(), and writeMem().

◆ getAddrMonitor()

AddressMonitor* gem5::CheckerCPU::getAddrMonitor ( )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 359 of file cpu.hh.

References gem5::BaseCPU::getCpuAddrMonitor().

◆ getDataPort()

Port& gem5::CheckerCPU::getDataPort ( )

inlineoverridevirtual

Purely virtual method that returns a reference to the data port.

All subclasses must implement this method.

Returns: a reference to the data port

Implements gem5::BaseCPU.

Definition at line 104 of file cpu.hh.

References dcachePort.

◆ getHtmTransactionalDepth()

uint64_t gem5::CheckerCPU::getHtmTransactionalDepth ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 267 of file cpu.hh.

References gem5::SimpleThread::htmTransactionStarts, gem5::SimpleThread::htmTransactionStops, and thread.

Referenced by inHtmTransactionalState().

◆ getHtmTransactionUid()

uint64_t gem5::CheckerCPU::getHtmTransactionUid ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 240 of file cpu.hh.

References panic.

◆ getInstPort()

Port& gem5::CheckerCPU::getInstPort ( )

inlineoverridevirtual

Purely virtual method that returns a reference to the instruction port.

All subclasses must implement this method.

Returns: a reference to the instruction port

Implements gem5::BaseCPU.

Definition at line 113 of file cpu.hh.

References icachePort.

◆ getMMUPtr()

BaseMMU* gem5::CheckerCPU::getMMUPtr ( )

inline

Definition at line 152 of file cpu.hh.

References mmu.

Referenced by gem5::BaseCPU::flushTLBs(), and gem5::BaseCPU::takeOverFrom().

◆ getRegOperand() [1/2]

RegVal gem5::CheckerCPU::getRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 177 of file cpu.hh.

References gem5::SimpleThread::getReg(), gem5::InvalidRegClass, gem5::MipsISA::is, gem5::ArmISA::si, and thread.

◆ getRegOperand() [2/2]

void gem5::CheckerCPU::getRegOperand	(	const StaticInst *	si,
		int	idx,
		void *	val
	)

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 186 of file cpu.hh.

References gem5::SimpleThread::getReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ getWritableRegOperand()

void* gem5::CheckerCPU::getWritableRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 192 of file cpu.hh.

References gem5::SimpleThread::getWritableReg(), gem5::ArmISA::si, and thread.

◆ handleError()

void gem5::CheckerCPU::handleError ( )

inline

Definition at line 412 of file cpu.hh.

References dumpAndExit(), and exitOnError.

Referenced by readMem(), gem5::Checker< DynInstPtr >::verify(), and writeMem().

◆ inHtmTransactionalState()

bool gem5::CheckerCPU::inHtmTransactionalState ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 261 of file cpu.hh.

References getHtmTransactionalDepth().

◆ init()

void gem5::CheckerCPU::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::BaseCPU.

Definition at line 59 of file cpu.cc.

References gem5::ThreadContext::getIsaPtr(), gem5::System::getRequestorId(), requestorId, gem5::BaseISA::setThreadContext(), systemPtr, and tc.

◆ initiateMemMgmtCmd()

Fault gem5::CheckerCPU::initiateMemMgmtCmd ( Request::Flags flags )

inlineoverridevirtual

Initiate a memory management command with no valid address.

Currently, these instructions need to bypass squashing in the O3 model Examples include HTM commands and TLBI commands. e.g. tell Ruby we're starting/stopping a HTM transaction, or tell Ruby to issue a TLBI operation

Implements gem5::ExecContext.

Definition at line 254 of file cpu.hh.

References gem5::NoFault, and panic.

◆ mwait()

bool gem5::CheckerCPU::mwait ( PacketPtr pkt )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 350 of file cpu.hh.

References gem5::BaseCPU::mwait().

◆ mwaitAtomic()

void gem5::CheckerCPU::mwaitAtomic ( ThreadContext * tc )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 353 of file cpu.hh.

References gem5::SimpleThread::mmu, gem5::BaseCPU::mwaitAtomic(), tc, and thread.

◆ newHtmTransactionUid()

uint64_t gem5::CheckerCPU::newHtmTransactionUid ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 247 of file cpu.hh.

References panic.

◆ PARAMS()

gem5::CheckerCPU::PARAMS ( CheckerCPU )

◆ pcState() [1/2]

const PCStateBase& gem5::CheckerCPU::pcState ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 274 of file cpu.hh.

References gem5::SimpleThread::pcState(), and thread.

Referenced by gem5::Checker< DynInstPtr >::advancePC(), gem5::Checker< DynInstPtr >::handlePendingInt(), and gem5::Checker< DynInstPtr >::verify().

◆ pcState() [2/2]

void gem5::CheckerCPU::pcState ( const PCStateBase & val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 279 of file cpu.hh.

References DPRINTF, gem5::SimpleThread::pcState(), thread, and gem5::X86ISA::val.

◆ readMem()

Fault gem5::CheckerCPU::readMem	(	Addr	addr,
		uint8_t *	data,
		unsigned	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable
	)

override

Definition at line 167 of file cpu.cc.

References gem5::X86ISA::addr, checkFlags(), gem5::Packet::createRead(), gem5::curTick(), data, gem5::Packet::dataStatic(), dcachePort, flags, genMemFragmentRequest(), handleError(), mmu, gem5::Request::NO_ACCESS, gem5::NoFault, gem5::BaseMMU::Read, gem5::RequestPort::sendFunctional(), tc, gem5::BaseMMU::translateFunctional(), unverifiedMemData, unverifiedReq, and warn.

◆ readMemAccPredicate()

bool gem5::CheckerCPU::readMemAccPredicate ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 228 of file cpu.hh.

References gem5::SimpleThread::readMemAccPredicate(), and thread.

◆ readMiscReg()

RegVal gem5::CheckerCPU::readMiscReg ( int misc_reg )

inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements gem5::ExecContext.

Definition at line 294 of file cpu.hh.

References gem5::SimpleThread::readMiscReg(), and thread.

◆ readMiscRegNoEffect()

RegVal gem5::CheckerCPU::readMiscRegNoEffect ( int misc_reg ) const

inline

Definition at line 288 of file cpu.hh.

References gem5::SimpleThread::readMiscRegNoEffect(), and thread.

◆ readMiscRegOperand()

RegVal gem5::CheckerCPU::readMiscRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 318 of file cpu.hh.

References gem5::MiscRegClass, gem5::SimpleThread::readMiscReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readPredicate()

bool gem5::CheckerCPU::readPredicate ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 219 of file cpu.hh.

References gem5::SimpleThread::readPredicate(), and thread.

◆ readStCondFailures()

unsigned int gem5::CheckerCPU::readStCondFailures ( ) const

inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 401 of file cpu.hh.

References gem5::SimpleThread::readStCondFailures(), and thread.

◆ recordPCChange()

void gem5::CheckerCPU::recordPCChange ( const PCStateBase & val )

inline

Definition at line 336 of file cpu.hh.

References changedPC, newPCState, gem5::ArmISA::set, and gem5::X86ISA::val.

Referenced by gem5::CheckerThreadContext< TC >::pcState().

◆ serialize()

void gem5::CheckerCPU::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize this object to the given output stream.

Note: CPU models should normally overload the serializeThread() method instead of the serialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.

Parameters

cp	The stream to serialize to.

Reimplemented from gem5::BaseCPU.

Definition at line 130 of file cpu.cc.

◆ setDcachePort()

void gem5::CheckerCPU::setDcachePort ( RequestPort * dcache_port )

Definition at line 124 of file cpu.cc.

References dcachePort.

◆ setIcachePort()

void gem5::CheckerCPU::setIcachePort ( RequestPort * icache_port )

Definition at line 118 of file cpu.cc.

References icachePort.

◆ setMemAccPredicate()

void gem5::CheckerCPU::setMemAccPredicate ( bool val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 234 of file cpu.hh.

References gem5::SimpleThread::setMemAccPredicate(), thread, and gem5::X86ISA::val.

◆ setMiscReg()

void gem5::CheckerCPU::setMiscReg	(	int	misc_reg,
		RegVal	val
	)

inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements gem5::ExecContext.

Definition at line 309 of file cpu.hh.

References DPRINTF, miscRegIdxs, gem5::SimpleThread::setMiscReg(), thread, and gem5::X86ISA::val.

Referenced by setMiscRegOperand().

◆ setMiscRegNoEffect()

void gem5::CheckerCPU::setMiscRegNoEffect	(	int	misc_reg,
		RegVal	val
	)

inline

Definition at line 300 of file cpu.hh.

References DPRINTF, miscRegIdxs, gem5::SimpleThread::setMiscRegNoEffect(), thread, and gem5::X86ISA::val.

◆ setMiscRegOperand()

void gem5::CheckerCPU::setMiscRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 326 of file cpu.hh.

References gem5::RegId::index(), gem5::MiscRegClass, gem5::X86ISA::reg, setMiscReg(), gem5::ArmISA::si, and gem5::X86ISA::val.

◆ setPredicate()

void gem5::CheckerCPU::setPredicate ( bool val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 222 of file cpu.hh.

References gem5::SimpleThread::setPredicate(), thread, and gem5::X86ISA::val.

◆ setRegOperand() [1/2]

void gem5::CheckerCPU::setRegOperand	(	const StaticInst *	si,
		int	idx,
		const void *	val
	)

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 209 of file cpu.hh.

References gem5::RegId::flatten(), gem5::SimpleThread::getIsaPtr(), gem5::InvalidRegClass, gem5::MipsISA::is, gem5::RegId::regClass(), result, gem5::SimpleThread::setReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setRegOperand() [2/2]

void gem5::CheckerCPU::setRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 198 of file cpu.hh.

References gem5::RegId::flatten(), gem5::SimpleThread::getIsaPtr(), gem5::InvalidRegClass, gem5::MipsISA::is, gem5::RegId::regClass(), result, gem5::SimpleThread::setReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setStCondFailures()

void gem5::CheckerCPU::setStCondFailures ( unsigned int sc_failures )

inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 406 of file cpu.hh.

◆ setSystem()

void gem5::CheckerCPU::setSystem ( System * system )

Definition at line 96 of file cpu.cc.

References gem5::FullSystem, gem5::SimpleThread::getTC(), mmu, gem5::VegaISA::p, gem5::SimObject::params(), gem5::BaseCPU::system, systemPtr, tc, thread, gem5::BaseCPU::threadContexts, and workload.

Referenced by gem5::BaseSimpleCPU::BaseSimpleCPU().

◆ tcBase()

ThreadContext* gem5::CheckerCPU::tcBase ( ) const

inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements gem5::ExecContext.

Definition at line 423 of file cpu.hh.

References tc.

◆ threadBase()

SimpleThread* gem5::CheckerCPU::threadBase ( )

inline

Definition at line 424 of file cpu.hh.

References thread.

◆ totalInsts()

virtual Counter gem5::CheckerCPU::totalInsts ( ) const

inlineoverridevirtual

Implements gem5::BaseCPU.

Definition at line 154 of file cpu.hh.

◆ totalOps()

virtual Counter gem5::CheckerCPU::totalOps ( ) const

inlineoverridevirtual

Implements gem5::BaseCPU.

Definition at line 156 of file cpu.hh.

◆ unserialize()

void gem5::CheckerCPU::unserialize ( CheckpointIn & cp )

overridevirtual

Reconstruct the state of this object from a checkpoint.

Note: CPU models should normally overload the unserializeThread() method instead of the unserialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.

Parameters

cp	The checkpoint use.

Reimplemented from gem5::BaseCPU.

Definition at line 135 of file cpu.cc.

◆ wakeup()

void gem5::CheckerCPU::wakeup ( ThreadID tid )

inlineoverridevirtual

Implements gem5::BaseCPU.

Definition at line 409 of file cpu.hh.

◆ writeMem()

Fault gem5::CheckerCPU::writeMem	(	uint8_t *	data,
		unsigned	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable
	)

override

Definition at line 251 of file cpu.cc.

References gem5::X86ISA::addr, checkFlags(), gem5::curTick(), data, flags, genMemFragmentRequest(), handleError(), mmu, gem5::NoFault, gem5::Request::STORE_NO_DATA, tc, gem5::BaseMMU::translateFunctional(), unverifiedMemData, unverifiedReq, warn, and gem5::BaseMMU::Write.

Member Data Documentation

◆ changedPC

bool gem5::CheckerCPU::changedPC

Definition at line 430 of file cpu.hh.

Referenced by CheckerCPU(), and recordPCChange().

◆ curMacroStaticInst

StaticInstPtr gem5::CheckerCPU::curMacroStaticInst

protected

Definition at line 139 of file cpu.hh.

Referenced by CheckerCPU().

◆ curStaticInst

StaticInstPtr gem5::CheckerCPU::curStaticInst

protected

Definition at line 138 of file cpu.hh.

Referenced by CheckerCPU().

◆ dcachePort

RequestPort* gem5::CheckerCPU::dcachePort

protected

Definition at line 128 of file cpu.hh.

Referenced by getDataPort(), readMem(), and setDcachePort().

◆ exitOnError

bool gem5::CheckerCPU::exitOnError

Definition at line 433 of file cpu.hh.

Referenced by CheckerCPU(), handleError(), and gem5::Checker< DynInstPtr >::handleError().

◆ icachePort

RequestPort* gem5::CheckerCPU::icachePort

protected

Definition at line 127 of file cpu.hh.

Referenced by getInstPort(), and setIcachePort().

◆ miscRegIdxs

std::queue<int> gem5::CheckerCPU::miscRegIdxs

protected

Definition at line 145 of file cpu.hh.

Referenced by setMiscReg(), and setMiscRegNoEffect().

◆ mmu

BaseMMU* gem5::CheckerCPU::mmu

protected

Definition at line 132 of file cpu.hh.

Referenced by CheckerCPU(), demapPage(), getMMUPtr(), readMem(), setSystem(), and writeMem().

◆ newPCState

std::unique_ptr<PCStateBase> gem5::CheckerCPU::newPCState

Definition at line 432 of file cpu.hh.

Referenced by recordPCChange().

◆ numInst

Counter gem5::CheckerCPU::numInst

protected

Definition at line 142 of file cpu.hh.

Referenced by CheckerCPU().

◆ numLoad

Counter gem5::CheckerCPU::numLoad

Definition at line 159 of file cpu.hh.

Referenced by CheckerCPU().

◆ requestorId

RequestorID gem5::CheckerCPU::requestorId

protected

id attached to all issued requests

Definition at line 88 of file cpu.hh.

Referenced by genMemFragmentRequest(), and init().

◆ result

std::queue<InstResult> gem5::CheckerCPU::result

protected

Definition at line 136 of file cpu.hh.

Referenced by setRegOperand().

◆ startNumInst

Counter gem5::CheckerCPU::startNumInst

protected

Definition at line 143 of file cpu.hh.

Referenced by CheckerCPU().

◆ startNumLoad

Counter gem5::CheckerCPU::startNumLoad

Definition at line 160 of file cpu.hh.

Referenced by CheckerCPU().

◆ systemPtr

System* gem5::CheckerCPU::systemPtr

protected

Definition at line 125 of file cpu.hh.

Referenced by init(), and setSystem().

◆ tc

ThreadContext* gem5::CheckerCPU::tc

protected

Definition at line 130 of file cpu.hh.

Referenced by genMemFragmentRequest(), init(), mwaitAtomic(), readMem(), setSystem(), tcBase(), and writeMem().

◆ thread

SimpleThread* gem5::CheckerCPU::thread

Definition at line 150 of file cpu.hh.

Referenced by dumpAndExit(), genMemFragmentRequest(), getHtmTransactionalDepth(), getRegOperand(), getWritableRegOperand(), mwaitAtomic(), pcState(), readMemAccPredicate(), readMiscReg(), readMiscRegNoEffect(), readMiscRegOperand(), readPredicate(), readStCondFailures(), setMemAccPredicate(), setMiscReg(), setMiscRegNoEffect(), setPredicate(), setRegOperand(), setSystem(), and threadBase().

◆ unverifiedMemData

uint8_t* gem5::CheckerCPU::unverifiedMemData

Definition at line 428 of file cpu.hh.

Referenced by readMem(), and writeMem().

◆ unverifiedReq

RequestPtr gem5::CheckerCPU::unverifiedReq

Definition at line 427 of file cpu.hh.

Referenced by readMem(), and writeMem().

◆ unverifiedResult

InstResult gem5::CheckerCPU::unverifiedResult

Definition at line 426 of file cpu.hh.

◆ updateOnError

bool gem5::CheckerCPU::updateOnError

Definition at line 434 of file cpu.hh.

Referenced by CheckerCPU(), and gem5::Checker< DynInstPtr >::handleError().

◆ warnOnlyOnLoadError

bool gem5::CheckerCPU::warnOnlyOnLoadError

Definition at line 435 of file cpu.hh.

Referenced by CheckerCPU().

◆ willChangePC

bool gem5::CheckerCPU::willChangePC

Definition at line 431 of file cpu.hh.

Referenced by CheckerCPU().

◆ workload

std::vector<Process*> gem5::CheckerCPU::workload

protected

Definition at line 123 of file cpu.hh.

Referenced by CheckerCPU(), and setSystem().

◆ youngestSN

InstSeqNum gem5::CheckerCPU::youngestSN

Definition at line 437 of file cpu.hh.

Referenced by CheckerCPU().

The documentation for this class was generated from the following files:

cpu/checker/cpu.hh
cpu/checker/cpu.cc

Public Member Functions

Public Attributes

Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ CheckerCPU()

◆ ~CheckerCPU()

Member Function Documentation

◆ amoMem()

◆ armMonitor()

◆ checkFlags()

◆ demapPage()

◆ dumpAndExit()

◆ genMemFragmentRequest()

◆ getAddrMonitor()

◆ getDataPort()

◆ getHtmTransactionalDepth()

◆ getHtmTransactionUid()

◆ getInstPort()

◆ getMMUPtr()

◆ getRegOperand() [1/2]

◆ getRegOperand() [2/2]

◆ getWritableRegOperand()

◆ handleError()

◆ inHtmTransactionalState()

◆ init()

◆ initiateMemMgmtCmd()

◆ mwait()

◆ mwaitAtomic()

◆ newHtmTransactionUid()

◆ PARAMS()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ readMem()

◆ readMemAccPredicate()

◆ readMiscReg()

◆ readMiscRegNoEffect()

◆ readMiscRegOperand()

◆ readPredicate()

◆ readStCondFailures()

◆ recordPCChange()

◆ serialize()

◆ setDcachePort()

◆ setIcachePort()

◆ setMemAccPredicate()

◆ setMiscReg()

◆ setMiscRegNoEffect()

◆ setMiscRegOperand()

◆ setPredicate()

◆ setRegOperand() [1/2]

◆ setRegOperand() [2/2]

◆ setStCondFailures()

◆ setSystem()

◆ tcBase()

◆ threadBase()

◆ totalInsts()

◆ totalOps()

◆ unserialize()

◆ wakeup()

◆ writeMem()

Member Data Documentation

◆ changedPC

◆ curMacroStaticInst

◆ curStaticInst

◆ dcachePort

◆ exitOnError

◆ icachePort

◆ miscRegIdxs

◆ mmu

◆ newPCState

◆ numInst

◆ numLoad

◆ requestorId

◆ result

◆ startNumInst

◆ startNumLoad

◆ systemPtr

◆ tc

◆ thread