gem5  v22.1.0.0
Public Types | Static Public Attributes | Protected Types | Static Protected Attributes | List of all members
gem5::EventBase Class Reference

Common base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions. More...

#include <eventq.hh>

Inheritance diagram for gem5::EventBase:
gem5::BaseGlobalEvent gem5::Event gem5::BaseGlobalEventTemplate< GlobalEvent > gem5::BaseGlobalEventTemplate< GlobalSyncEvent > gem5::BaseGlobalEventTemplate< Derived > gem5::EventWrapper< sc_gem5::Scheduler, &Scheduler::timeAdvances > gem5::EventWrapper< gem5::memory::qos::MemSinkCtrl, &MemSinkCtrl::processNextReqEvent > gem5::EventWrapper< sc_gem5::Scheduler, &Scheduler::stop > gem5::EventWrapper< sc_gem5::Kernel, &Kernel::t0Handler > gem5::EventWrapper< sc_gem5::Scheduler, &Scheduler::maxTickFunc > gem5::EventWrapper< sc_gem5::Scheduler, &Scheduler::pause > gem5::EventWrapper< sc_gem5::Scheduler, &Scheduler::runReady > gem5::EventWrapper< gem5::SMMUv3DeviceInterface, &SMMUv3DeviceInterface::atsSendDeviceRetry > gem5::EventWrapper< gem5::PowerDomain, &PowerDomain::setFollowerPowerStates > gem5::EventWrapper< gem5::BaseRemoteGDB, &BaseRemoteGDB::detach > gem5::EventWrapper< gem5::BaseRemoteGDB, &BaseRemoteGDB::connect > gem5::EventWrapper< gem5::SMMUv3, &SMMUv3::processCommands > gem5::EventWrapper< gem5::BaseRemoteGDB, &BaseRemoteGDB::singleStep > gem5::AMDGPUInterruptHandler::DmaEvent gem5::AMDGPUSystemHub::ResponseEvent gem5::BaseGlobalEvent::BarrierEvent gem5::BasePixelPump::PixelEvent gem5::BaseRemoteGDB::TrapEvent gem5::CPUProgressEvent gem5::ComputeUnit::DataPort::SystemHubEvent gem5::ComputeUnit::ScalarDataPort::MemReqEvent gem5::ComputeUnit::ScalarDataPort::SystemHubEvent gem5::CountedExitEvent gem5::DVFSHandler::UpdateEvent gem5::DmaReadFifo::DmaDoneEvent gem5::EventFunctionWrapper gem5::EventWrapper< T, F > gem5::FetchUnit::SystemHubEvent gem5::GPUComputeDriver::DriverWakeupEvent gem5::HSAPacketProcessor::QueueProcessEvent gem5::HWScheduler::SchedulerWakeupEvent gem5::Intel8254Timer::Counter::CounterEvent gem5::LdsState::TickEvent gem5::LocalSimLoopExitEvent gem5::MC146818::RTCEvent gem5::MC146818::RTCTickEvent gem5::PyEvent gem5::RegisterFile::RegisterEvent gem5::SMMUDeviceRetryEvent gem5::TesterThread::DeadlockCheckEvent gem5::TesterThread::TesterThreadEvent gem5::TimingSimpleCPU::IprEvent gem5::TimingSimpleCPU::TimingCPUPort::TickEvent gem5::VegaISA::GpuTLB::TLBEvent gem5::X86ISA::GpuTLB::TLBEvent gem5::o3::Fetch::FinishTranslationEvent gem5::o3::InstructionQueue::FUCompletion gem5::o3::LSQUnit::WritebackEvent gem5::trace::TarmacParserRecord::TarmacParserRecordEvent sc_gem5::Scheduler::TimeSlot

Public Types

typedef int8_t Priority

Static Public Attributes

static const Priority Minimum_Pri = SCHAR_MIN
 Event priorities, to provide tie-breakers for events scheduled at the same cycle. More...
static const Priority Debug_Enable_Pri = -101
 If we enable tracing on a particular cycle, do that as the very first thing so we don't miss any of the events on that cycle (even if we enter the debugger). More...
static const Priority Debug_Break_Pri = -100
 Breakpoints should happen before anything else (except enabling trace output), so we don't miss any action when debugging. More...
static const Priority CPU_Switch_Pri = -31
 CPU switches schedule the new CPU's tick event for the same cycle (after unscheduling the old CPU's tick event). More...
static const Priority Delayed_Writeback_Pri = -1
 For some reason "delayed" inter-cluster writebacks are scheduled before regular writebacks (which have default priority). More...
static const Priority Default_Pri = 0
 Default is zero for historical reasons. More...
static const Priority DVFS_Update_Pri = 31
 DVFS update event leads to stats dump therefore given a lower priority to ensure all relevant states have been updated. More...
static const Priority Serialize_Pri = 32
 Serailization needs to occur before tick events also, so that a serialize/unserialize is identical to an on-line CPU switch. More...
static const Priority CPU_Tick_Pri = 50
 CPU ticks must come after other associated CPU events (such as writebacks). More...
static const Priority CPU_Exit_Pri = 64
 If we want to exit a thread in a CPU, it comes after CPU_Tick_Pri. More...
static const Priority Stat_Event_Pri = 90
 Statistics events (dump, reset, etc.) come after everything else, but before exit. More...
static const Priority Progress_Event_Pri = 95
 Progress events come at the end. More...
static const Priority Sim_Exit_Pri = 100
 If we want to exit on this cycle, it's the very last thing we do. More...
static const Priority Maximum_Pri = SCHAR_MAX
 Maximum priority. More...

Protected Types

typedef unsigned short FlagsType
typedef ::gem5::Flags< FlagsTypeFlags

Static Protected Attributes

static const FlagsType PublicRead = 0x003f
static const FlagsType PublicWrite = 0x001d
static const FlagsType Squashed = 0x0001
static const FlagsType Scheduled = 0x0002
static const FlagsType Managed = 0x0004
static const FlagsType AutoDelete = Managed
static const FlagsType Reserved0 = 0x0008
 This used to be AutoSerialize. More...
static const FlagsType IsExitEvent = 0x0010
static const FlagsType IsMainQueue = 0x0020
static const FlagsType Initialized = 0x7a40
static const FlagsType InitMask = 0xffc0

Detailed Description

Common base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions.

This class should not be used directly.

Definition at line 96 of file eventq.hh.

Member Typedef Documentation

◆ Flags

Definition at line 100 of file eventq.hh.

◆ FlagsType

typedef unsigned short gem5::EventBase::FlagsType

Definition at line 99 of file eventq.hh.

Member Data Documentation

◆ AutoDelete

const FlagsType gem5::EventBase::AutoDelete = Managed

◆ Initialized

const FlagsType gem5::EventBase::Initialized = 0x7a40

Definition at line 116 of file eventq.hh.

Referenced by gem5::Event::initialized(), and gem5::Event::unserialize().

◆ InitMask

const FlagsType gem5::EventBase::InitMask = 0xffc0

Definition at line 117 of file eventq.hh.

Referenced by gem5::Event::initialized().

◆ IsExitEvent

const FlagsType gem5::EventBase::IsExitEvent = 0x0010

Definition at line 114 of file eventq.hh.

Referenced by gem5::Event::isExitEvent().

◆ IsMainQueue

const FlagsType gem5::EventBase::IsMainQueue = 0x0020

Definition at line 115 of file eventq.hh.

Referenced by gem5::EventQueue::serviceOne().

◆ Managed

const FlagsType gem5::EventBase::Managed = 0x0004

◆ PublicRead

const FlagsType gem5::EventBase::PublicRead = 0x003f

Definition at line 102 of file eventq.hh.

Referenced by gem5::Event::getFlags(), and gem5::Event::isFlagSet().

◆ PublicWrite

const FlagsType gem5::EventBase::PublicWrite = 0x001d

Definition at line 103 of file eventq.hh.

Referenced by gem5::Event::clearFlags(), gem5::Event::Event(), and gem5::Event::setFlags().

◆ Reserved0

const FlagsType gem5::EventBase::Reserved0 = 0x0008

This used to be AutoSerialize.

This value can't be reused without changing the checkpoint version since the flag field gets serialized.

Definition at line 113 of file eventq.hh.

◆ Scheduled

const FlagsType gem5::EventBase::Scheduled = 0x0002

◆ Squashed

const FlagsType gem5::EventBase::Squashed = 0x0001

The documentation for this class was generated from the following file:

Generated on Wed Dec 21 2022 10:23:29 for gem5 by doxygen 1.9.1