gem5  v21.1.0.2
register_file.hh
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33 
34 #ifndef __REGISTER_FILE_HH__
35 #define __REGISTER_FILE_HH__
36 
37 #include <limits>
38 #include <vector>
39 
40 #include "base/statistics.hh"
41 #include "base/types.hh"
42 #include "gpu-compute/misc.hh"
43 #include "sim/sim_object.hh"
44 
45 namespace gem5
46 {
47 
48 class ComputeUnit;
49 class Shader;
50 class PoolManager;
51 class Wavefront;
52 
53 struct RegisterFileParams;
54 
55 // Abstract Register File
56 // This register file class can be inherited from to create both
57 // scalar and vector register files.
58 class RegisterFile : public SimObject
59 {
60  public:
61  RegisterFile(const RegisterFileParams &p);
62  virtual ~RegisterFile();
63  virtual void setParent(ComputeUnit *_computeUnit);
64  int numRegs() const { return _numRegs; }
65 
66  // State functions
67 
68  // Scoreboard functions
69  virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const;
70  virtual bool regBusy(int idx) const;
71  virtual void markReg(int regIdx, bool value);
72 
73  // Abstract Register Event
74  class RegisterEvent : public Event
75  {
76  protected:
78  int regIdx;
79 
80  public:
81  RegisterEvent(RegisterFile *_rf, int _regIdx)
82  : rf(_rf), regIdx(_regIdx) { setFlags(AutoDelete); }
83  };
84 
85  // Register Event to mark a register as free in the scoreboard/busy vector
87  {
88  public:
89  MarkRegFreeScbEvent(RegisterFile *_rf, int _regIdx)
90  : RegisterEvent(_rf, _regIdx) { }
91  void process();
92  };
93 
94  // Register Event to mark a register as busy in the scoreboard/busy vector
96  {
97  public:
98  MarkRegBusyScbEvent(RegisterFile *_rf, int _regIdx)
99  : RegisterEvent(_rf, _regIdx) { }
100  void process();
101  };
102 
103  // Schedule an event to mark a register as free/busy in
104  // the scoreboard/busy vector. Delay is already in Ticks
105  virtual void enqRegFreeEvent(uint32_t regIdx, uint64_t delay);
106  virtual void enqRegBusyEvent(uint32_t regIdx, uint64_t delay);
107 
108  // Schedule functions
109 
110  // The following functions are called by the SCH stage when attempting
111  // to move a wave from the readyList to the schList.
112  // canSchedule* checks if the RF is ready to provide operands for
113  // the instruction, while schedule* requests the RF to begin reading
114  // and writing of operands. Calling schedule* may only occur
115  // immediately after canSchedule* was called and returned True
118  virtual void scheduleReadOperands(Wavefront *w, GPUDynInstPtr ii);
119  virtual void scheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii);
120 
121  // The following function is called to check if all operands
122  // have been read for the given instruction
123  virtual bool operandReadComplete(Wavefront *w, GPUDynInstPtr ii);
124 
125  // The following two functions are only called by returning loads to
126  // check if the register file can support the incoming writes
128  GPUDynInstPtr ii);
129  // Queue the register writes. Assumes canScheduleWriteOperandsFromLoad
130  // was called immediately prior and returned True
132  GPUDynInstPtr ii);
133 
134  // ExecRF is invoked every cycle by the compute unit and may be
135  // used to model detailed timing of the register file.
136  virtual void exec();
137 
138  // Called to inform RF that an instruction is executing
139  // to schedule events for writeback, etc., as needed
140  virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii);
141 
142  // Debug functions
143  virtual std::string dump() const;
144 
145  virtual void dispatchInstruction(GPUDynInstPtr ii);
146 
147  protected:
149  int simdId;
150 
151  // flag indicating if a register is busy
153 
154  // numer of registers in this register file
155  int _numRegs;
156 
158  {
160 
161  // Total number of register reads per DWORD per thread
163  // Total number of register writes per DWORD per thread
165 
166  // Number of register file SRAM activations for reads.
167  // The register file may be implemented with multiple SRAMs. This stat
168  // tracks how many times the SRAMs are accessed for reads.
170  // Number of register file SRAM activations for writes
172  } stats;
173 };
174 
175 } // namespace gem5
176 
177 #endif // __REGISTER_FILE_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::RegisterFile
Definition: register_file.hh:58
gem5::RegisterFile::MarkRegBusyScbEvent::process
void process()
Definition: register_file.cc:185
gem5::RegisterFile::busy
std::vector< bool > busy
Definition: register_file.hh:152
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
gem5::RegisterFile::enqRegBusyEvent
virtual void enqRegBusyEvent(uint32_t regIdx, uint64_t delay)
Definition: register_file.cc:115
gem5::RegisterFile::MarkRegFreeScbEvent::process
void process()
Definition: register_file.cc:178
gem5::RegisterFile::enqRegFreeEvent
virtual void enqRegFreeEvent(uint32_t regIdx, uint64_t delay)
Definition: register_file.cc:106
gem5::Wavefront
Definition: wavefront.hh:62
misc.hh
gem5::RegisterFile::RegisterFileStats::RegisterFileStats
RegisterFileStats(statistics::Group *parent)
Definition: register_file.cc:195
gem5::RegisterFile::MarkRegFreeScbEvent::MarkRegFreeScbEvent
MarkRegFreeScbEvent(RegisterFile *_rf, int _regIdx)
Definition: register_file.hh:89
gem5::RegisterFile::RegisterFileStats
Definition: register_file.hh:157
gem5::RegisterFile::canScheduleReadOperands
virtual bool canScheduleReadOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:125
gem5::RegisterFile::stats
gem5::RegisterFile::RegisterFileStats stats
gem5::RegisterFile::dispatchInstruction
virtual void dispatchInstruction(GPUDynInstPtr ii)
Definition: register_file.cc:191
gem5::RegisterFile::markReg
virtual void markReg(int regIdx, bool value)
Definition: register_file.cc:98
gem5::RegisterFile::RegisterEvent::RegisterEvent
RegisterEvent(RegisterFile *_rf, int _regIdx)
Definition: register_file.hh:81
std::vector< bool >
gem5::RegisterFile::RegisterFileStats::registerWrites
statistics::Scalar registerWrites
Definition: register_file.hh:164
gem5::RegisterFile::waveExecuteInst
virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:170
gem5::RegisterFile::canScheduleWriteOperands
virtual bool canScheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:136
gem5::Event::setFlags
void setFlags(Flags _flags)
Definition: eventq.hh:328
gem5::RegisterFile::RegisterEvent::rf
RegisterFile * rf
Definition: register_file.hh:77
gem5::EventBase::AutoDelete
static const FlagsType AutoDelete
Definition: eventq.hh:107
gem5::ComputeUnit
Definition: compute_unit.hh:203
gem5::RegisterFile::regBusy
virtual bool regBusy(int idx) const
Definition: register_file.cc:92
gem5::RegisterFile::RegisterFileStats::registerReads
statistics::Scalar registerReads
Definition: register_file.hh:162
gem5::RegisterFile::RegisterEvent
Definition: register_file.hh:74
sim_object.hh
gem5::Event
Definition: eventq.hh:251
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::RegisterFile::MarkRegBusyScbEvent
Definition: register_file.hh:95
gem5::RegisterFile::_numRegs
int _numRegs
Definition: register_file.hh:155
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::RegisterFile::RegisterFile
RegisterFile(const RegisterFileParams &p)
Definition: register_file.cc:51
gem5::RegisterFile::exec
virtual void exec()
Definition: register_file.cc:165
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
gem5::RegisterFile::RegisterEvent::regIdx
int regIdx
Definition: register_file.hh:78
gem5::RegisterFile::scheduleWriteOperands
virtual void scheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:142
gem5::RegisterFile::numRegs
int numRegs() const
Definition: register_file.hh:64
gem5::RegisterFile::scheduleReadOperands
virtual void scheduleReadOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:131
gem5::RegisterFile::dump
virtual std::string dump() const
Definition: register_file.cc:72
types.hh
gem5::RegisterFile::canScheduleWriteOperandsFromLoad
virtual bool canScheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:147
gem5::RegisterFile::MarkRegBusyScbEvent::MarkRegBusyScbEvent
MarkRegBusyScbEvent(RegisterFile *_rf, int _regIdx)
Definition: register_file.hh:98
gem5::RegisterFile::operandReadComplete
virtual bool operandReadComplete(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:158
gem5::RegisterFile::scheduleWriteOperandsFromLoad
virtual void scheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:153
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::RegisterFile::setParent
virtual void setParent(ComputeUnit *_computeUnit)
Definition: register_file.cc:66
gem5::RegisterFile::computeUnit
ComputeUnit * computeUnit
Definition: register_file.hh:148
gem5::RegisterFile::simdId
int simdId
Definition: register_file.hh:149
gem5::RegisterFile::RegisterFileStats::sramWrites
statistics::Scalar sramWrites
Definition: register_file.hh:171
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RegisterFile::MarkRegFreeScbEvent
Definition: register_file.hh:86
gem5::RegisterFile::RegisterFileStats::sramReads
statistics::Scalar sramReads
Definition: register_file.hh:169
gem5::RegisterFile::~RegisterFile
virtual ~RegisterFile()
Definition: register_file.cc:61
gem5::RegisterFile::operandsReady
virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const
Definition: register_file.cc:86

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