gem5  v21.2.1.1
register_file.hh
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31 
32 #ifndef __REGISTER_FILE_HH__
33 #define __REGISTER_FILE_HH__
34 
35 #include <limits>
36 #include <vector>
37 
38 #include "base/statistics.hh"
39 #include "base/types.hh"
40 #include "gpu-compute/misc.hh"
41 #include "sim/sim_object.hh"
42 
43 namespace gem5
44 {
45 
46 class ComputeUnit;
47 class Shader;
48 class PoolManager;
49 class Wavefront;
50 
51 struct RegisterFileParams;
52 
53 // Abstract Register File
54 // This register file class can be inherited from to create both
55 // scalar and vector register files.
56 class RegisterFile : public SimObject
57 {
58  public:
59  RegisterFile(const RegisterFileParams &p);
60  virtual ~RegisterFile();
61  virtual void setParent(ComputeUnit *_computeUnit);
62  int numRegs() const { return _numRegs; }
63 
64  // State functions
65 
66  // Scoreboard functions
67  virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const;
68  virtual bool regBusy(int idx) const;
69  virtual void markReg(int regIdx, bool value);
70 
71  // Abstract Register Event
72  class RegisterEvent : public Event
73  {
74  protected:
76  int regIdx;
77 
78  public:
79  RegisterEvent(RegisterFile *_rf, int _regIdx)
80  : rf(_rf), regIdx(_regIdx) { setFlags(AutoDelete); }
81  };
82 
83  // Register Event to mark a register as free in the scoreboard/busy vector
85  {
86  public:
87  MarkRegFreeScbEvent(RegisterFile *_rf, int _regIdx)
88  : RegisterEvent(_rf, _regIdx) { }
89  void process();
90  };
91 
92  // Register Event to mark a register as busy in the scoreboard/busy vector
94  {
95  public:
96  MarkRegBusyScbEvent(RegisterFile *_rf, int _regIdx)
97  : RegisterEvent(_rf, _regIdx) { }
98  void process();
99  };
100 
101  // Schedule an event to mark a register as free/busy in
102  // the scoreboard/busy vector. Delay is already in Ticks
103  virtual void enqRegFreeEvent(uint32_t regIdx, uint64_t delay);
104  virtual void enqRegBusyEvent(uint32_t regIdx, uint64_t delay);
105 
106  // Schedule functions
107 
108  // The following functions are called by the SCH stage when attempting
109  // to move a wave from the readyList to the schList.
110  // canSchedule* checks if the RF is ready to provide operands for
111  // the instruction, while schedule* requests the RF to begin reading
112  // and writing of operands. Calling schedule* may only occur
113  // immediately after canSchedule* was called and returned True
116  virtual void scheduleReadOperands(Wavefront *w, GPUDynInstPtr ii);
117  virtual void scheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii);
118 
119  // The following function is called to check if all operands
120  // have been read for the given instruction
121  virtual bool operandReadComplete(Wavefront *w, GPUDynInstPtr ii);
122 
123  // The following two functions are only called by returning loads to
124  // check if the register file can support the incoming writes
126  GPUDynInstPtr ii);
127  // Queue the register writes. Assumes canScheduleWriteOperandsFromLoad
128  // was called immediately prior and returned True
130  GPUDynInstPtr ii);
131 
132  // ExecRF is invoked every cycle by the compute unit and may be
133  // used to model detailed timing of the register file.
134  virtual void exec();
135 
136  // Called to inform RF that an instruction is executing
137  // to schedule events for writeback, etc., as needed
138  virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii);
139 
140  // Debug functions
141  virtual std::string dump() const;
142 
143  virtual void dispatchInstruction(GPUDynInstPtr ii);
144 
145  protected:
147  int simdId;
148 
149  // flag indicating if a register is busy
151 
152  // numer of registers in this register file
153  int _numRegs;
154 
156  {
158 
159  // Total number of register reads per DWORD per thread
161  // Total number of register writes per DWORD per thread
163 
164  // Number of register file SRAM activations for reads.
165  // The register file may be implemented with multiple SRAMs. This stat
166  // tracks how many times the SRAMs are accessed for reads.
168  // Number of register file SRAM activations for writes
170  } stats;
171 };
172 
173 } // namespace gem5
174 
175 #endif // __REGISTER_FILE_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::RegisterFile
Definition: register_file.hh:56
gem5::RegisterFile::MarkRegBusyScbEvent::process
void process()
Definition: register_file.cc:183
gem5::RegisterFile::busy
std::vector< bool > busy
Definition: register_file.hh:150
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
gem5::RegisterFile::enqRegBusyEvent
virtual void enqRegBusyEvent(uint32_t regIdx, uint64_t delay)
Definition: register_file.cc:113
gem5::RegisterFile::MarkRegFreeScbEvent::process
void process()
Definition: register_file.cc:176
gem5::RegisterFile::enqRegFreeEvent
virtual void enqRegFreeEvent(uint32_t regIdx, uint64_t delay)
Definition: register_file.cc:104
gem5::Wavefront
Definition: wavefront.hh:60
misc.hh
gem5::RegisterFile::RegisterFileStats::RegisterFileStats
RegisterFileStats(statistics::Group *parent)
Definition: register_file.cc:193
gem5::RegisterFile::MarkRegFreeScbEvent::MarkRegFreeScbEvent
MarkRegFreeScbEvent(RegisterFile *_rf, int _regIdx)
Definition: register_file.hh:87
gem5::RegisterFile::RegisterFileStats
Definition: register_file.hh:155
gem5::RegisterFile::canScheduleReadOperands
virtual bool canScheduleReadOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:123
gem5::RegisterFile::stats
gem5::RegisterFile::RegisterFileStats stats
gem5::RegisterFile::dispatchInstruction
virtual void dispatchInstruction(GPUDynInstPtr ii)
Definition: register_file.cc:189
gem5::RegisterFile::markReg
virtual void markReg(int regIdx, bool value)
Definition: register_file.cc:96
gem5::RegisterFile::RegisterEvent::RegisterEvent
RegisterEvent(RegisterFile *_rf, int _regIdx)
Definition: register_file.hh:79
std::vector< bool >
gem5::RegisterFile::RegisterFileStats::registerWrites
statistics::Scalar registerWrites
Definition: register_file.hh:162
gem5::RegisterFile::waveExecuteInst
virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:168
gem5::RegisterFile::canScheduleWriteOperands
virtual bool canScheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:134
gem5::Event::setFlags
void setFlags(Flags _flags)
Definition: eventq.hh:328
gem5::RegisterFile::RegisterEvent::rf
RegisterFile * rf
Definition: register_file.hh:75
gem5::EventBase::AutoDelete
static const FlagsType AutoDelete
Definition: eventq.hh:107
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::RegisterFile::regBusy
virtual bool regBusy(int idx) const
Definition: register_file.cc:90
gem5::RegisterFile::RegisterFileStats::registerReads
statistics::Scalar registerReads
Definition: register_file.hh:160
gem5::RegisterFile::RegisterEvent
Definition: register_file.hh:72
sim_object.hh
gem5::Event
Definition: eventq.hh:251
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::RegisterFile::MarkRegBusyScbEvent
Definition: register_file.hh:93
gem5::RegisterFile::_numRegs
int _numRegs
Definition: register_file.hh:153
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::RegisterFile::RegisterFile
RegisterFile(const RegisterFileParams &p)
Definition: register_file.cc:49
gem5::RegisterFile::exec
virtual void exec()
Definition: register_file.cc:163
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::RegisterFile::RegisterEvent::regIdx
int regIdx
Definition: register_file.hh:76
gem5::RegisterFile::scheduleWriteOperands
virtual void scheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:140
gem5::RegisterFile::numRegs
int numRegs() const
Definition: register_file.hh:62
gem5::RegisterFile::scheduleReadOperands
virtual void scheduleReadOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:129
gem5::RegisterFile::dump
virtual std::string dump() const
Definition: register_file.cc:70
types.hh
gem5::RegisterFile::canScheduleWriteOperandsFromLoad
virtual bool canScheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:145
gem5::RegisterFile::MarkRegBusyScbEvent::MarkRegBusyScbEvent
MarkRegBusyScbEvent(RegisterFile *_rf, int _regIdx)
Definition: register_file.hh:96
gem5::RegisterFile::operandReadComplete
virtual bool operandReadComplete(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:156
gem5::RegisterFile::scheduleWriteOperandsFromLoad
virtual void scheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:151
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::RegisterFile::setParent
virtual void setParent(ComputeUnit *_computeUnit)
Definition: register_file.cc:64
gem5::RegisterFile::computeUnit
ComputeUnit * computeUnit
Definition: register_file.hh:146
gem5::RegisterFile::simdId
int simdId
Definition: register_file.hh:147
gem5::RegisterFile::RegisterFileStats::sramWrites
statistics::Scalar sramWrites
Definition: register_file.hh:169
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::RegisterFile::MarkRegFreeScbEvent
Definition: register_file.hh:84
gem5::RegisterFile::RegisterFileStats::sramReads
statistics::Scalar sramReads
Definition: register_file.hh:167
gem5::RegisterFile::~RegisterFile
virtual ~RegisterFile()
Definition: register_file.cc:59
gem5::RegisterFile::operandsReady
virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const
Definition: register_file.cc:84

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