fetch_unit.hh

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/*
 * Copyright (c) 2014-2017 Advanced Micro Devices, Inc.
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 * this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright notice,
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#ifndef __FETCH_UNIT_HH__
#define __FETCH_UNIT_HH__
 
#include <cassert>
#include <cstdint>
#include <deque>
#include <map>
#include <utility>
#include <vector>
 
#include "arch/gpu_decoder.hh"
#include "base/types.hh"
#include "config/the_gpu_isa.hh"
#include "gpu-compute/scheduler.hh"
#include "mem/packet.hh"
#include "sim/eventq.hh"
 
namespace gem5
{
 
class ComputeUnit;
class Wavefront;
 
class FetchUnit
{
  public:
    FetchUnit(const ComputeUnitParams &p, ComputeUnit &cu);
    ~FetchUnit();
    void init();
    void exec();
    void bindWaveList(std::vector<Wavefront*> *list);
    void initiateFetch(Wavefront *wavefront);
    void fetch(PacketPtr pkt, Wavefront *wavefront);
    void processFetchReturn(PacketPtr pkt);
    void flushBuf(int wfSlotId);
    static uint32_t globalFetchUnitID;
 
  private:
    class FetchBufDesc
    {
      public:
        FetchBufDesc() : bufStart(nullptr), bufEnd(nullptr),
            readPtr(nullptr), fetchDepth(0), maxIbSize(0), maxFbSize(0),
            cacheLineSize(0), restartFromBranch(false), wavefront(nullptr),
            _decoder(nullptr)
        {
        }
 
        ~FetchBufDesc()
        {
            delete[] bufStart;
        }
 
        void allocateBuf(int fetch_depth, int cache_line_size, Wavefront *wf);
 
        int
        bufferedAndReservedLines() const
        {
            return bufferedLines() + reservedLines();
        }
 
        int bufferedLines() const { return bufferedPCs.size(); }
        int bufferedBytes() const { return bufferedLines() * cacheLineSize; }
        int reservedLines() const { return reservedPCs.size(); }
        bool hasFreeSpace() const { return !freeList.empty(); }
        void flushBuf();
        Addr nextFetchAddr();
 
        void reserveBuf(Addr vaddr);
 
        uint8_t*
        reservedBuf(Addr vaddr) const
        {
            auto reserved_pc = reservedPCs.find(vaddr);
            assert(reserved_pc != reservedPCs.end());
            assert(reserved_pc == reservedPCs.begin());
 
            return reserved_pc->second;
        }
 
        bool
        isReserved(Addr vaddr) const
        {
            auto reserved_pc = reservedPCs.find(vaddr);
            bool is_reserved = (reserved_pc != reservedPCs.end());
            return is_reserved;
        }
 
        void fetchDone(Addr vaddr);
 
        bool hasFetchDataToProcess() const;
 
        void decodeInsts();
 
        void checkWaveReleaseBuf();
 
        void
        decoder(TheGpuISA::Decoder *dec)
        {
            _decoder = dec;
        }
 
        bool
        pcBuffered(Addr pc) const
        {
            bool buffered = bufferedPCs.find(pc) != bufferedPCs.end()
                            && reservedPCs.find(pc) != reservedPCs.end();
 
            return buffered;
        }
 
        int fetchBytesRemaining() const;
 
      private:
        void decodeSplitInst();
 
        bool splitDecode() const;
 
        std::map<Addr, uint8_t*> bufferedPCs;
        std::map<Addr, uint8_t*> reservedPCs;
 
        std::deque<uint8_t*> freeList;
 
        uint8_t *bufStart;
        uint8_t *bufEnd;
        uint8_t *readPtr;
        // how many lines the fetch unit may buffer
        int fetchDepth;
        // maximum size (in number of insts) of the WF's IB
        int maxIbSize;
        // maximum size (in bytes) of this fetch buffer
        int maxFbSize;
        int cacheLineSize;
        int cacheLineBits;
        bool restartFromBranch;
        // wavefront whose IB is serviced by this fetch buffer
        Wavefront *wavefront;
        TheGpuISA::Decoder *_decoder;
    };
 
    class SystemHubEvent : public Event
    {
      FetchUnit *fetchUnit;
      PacketPtr reqPkt;
 
      public:
        SystemHubEvent(PacketPtr pkt, FetchUnit *fetch_unit)
            : fetchUnit(fetch_unit), reqPkt(pkt)
        {
            setFlags(Event::AutoDelete);
        }
 
        void process();
    };
 
    bool timingSim;
    ComputeUnit &computeUnit;
    TheGpuISA::Decoder decoder;
 
    // Fetch scheduler; Selects one wave from
    // the fetch queue for instruction fetching.
    // The selection is made according to
    // a scheduling policy
    Scheduler fetchScheduler;
 
    // Stores the list of waves that are
    // ready to be fetched this cycle
    std::vector<Wavefront*> fetchQueue;
 
    // Stores the fetch status of all waves dispatched to this SIMD.
    // TRUE implies the wave is ready to fetch and is already
    // moved to fetchQueue
    std::vector<std::pair<Wavefront*, bool>> fetchStatusQueue;
 
    // Pointer to list of waves dispatched on to this SIMD unit
    std::vector<Wavefront*> *waveList;
    // holds the fetch buffers. each wave has 1 entry.
    std::vector<FetchBufDesc> fetchBuf;
    int fetchDepth;
};
 
} // namespace gem5
 
#endif // __FETCH_UNIT_HH__