gem5  v22.0.0.1
fetch_unit.hh
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31 
32 #ifndef __FETCH_UNIT_HH__
33 #define __FETCH_UNIT_HH__
34 
35 #include <cassert>
36 #include <cstdint>
37 #include <deque>
38 #include <map>
39 #include <utility>
40 #include <vector>
41 
42 #include "arch/gpu_decoder.hh"
43 #include "base/types.hh"
44 #include "config/the_gpu_isa.hh"
45 #include "gpu-compute/scheduler.hh"
46 #include "mem/packet.hh"
47 #include "sim/eventq.hh"
48 
49 namespace gem5
50 {
51 
52 class ComputeUnit;
53 class Wavefront;
54 
55 class FetchUnit
56 {
57  public:
58  FetchUnit(const ComputeUnitParams &p, ComputeUnit &cu);
59  ~FetchUnit();
60  void init();
61  void exec();
63  void initiateFetch(Wavefront *wavefront);
64  void fetch(PacketPtr pkt, Wavefront *wavefront);
65  void processFetchReturn(PacketPtr pkt);
66  void flushBuf(int wfSlotId);
67  static uint32_t globalFetchUnitID;
68 
69  private:
75  {
76  public:
77  FetchBufDesc() : bufStart(nullptr), bufEnd(nullptr),
78  readPtr(nullptr), fetchDepth(0), maxIbSize(0), maxFbSize(0),
79  cacheLineSize(0), restartFromBranch(false), wavefront(nullptr),
80  _decoder(nullptr)
81  {
82  }
83 
85  {
86  delete[] bufStart;
87  }
88 
94  void allocateBuf(int fetch_depth, int cache_line_size, Wavefront *wf);
95 
96  int
98  {
99  return bufferedLines() + reservedLines();
100  }
101 
102  int bufferedLines() const { return bufferedPCs.size(); }
103  int bufferedBytes() const { return bufferedLines() * cacheLineSize; }
104  int reservedLines() const { return reservedPCs.size(); }
105  bool hasFreeSpace() const { return !freeList.empty(); }
106  void flushBuf();
108 
112  void reserveBuf(Addr vaddr);
113 
119  uint8_t*
121  {
122  auto reserved_pc = reservedPCs.find(vaddr);
123  assert(reserved_pc != reservedPCs.end());
124  assert(reserved_pc == reservedPCs.begin());
125 
126  return reserved_pc->second;
127  }
128 
133  bool
135  {
136  auto reserved_pc = reservedPCs.find(vaddr);
137  bool is_reserved = (reserved_pc != reservedPCs.end());
138  return is_reserved;
139  }
140 
141  void fetchDone(Addr vaddr);
142 
148  bool hasFetchDataToProcess() const;
149 
158  void decodeInsts();
159 
165  void checkWaveReleaseBuf();
166 
167  void
168  decoder(TheGpuISA::Decoder *dec)
169  {
170  _decoder = dec;
171  }
172 
173  bool
175  {
176  bool buffered = bufferedPCs.find(pc) != bufferedPCs.end()
177  && reservedPCs.find(pc) != reservedPCs.end();
178 
179  return buffered;
180  }
181 
186  int fetchBytesRemaining() const;
187 
188  private:
189  void decodeSplitInst();
190 
196  bool splitDecode() const;
197 
204  std::map<Addr, uint8_t*> bufferedPCs;
205  std::map<Addr, uint8_t*> reservedPCs;
206 
216 
221  uint8_t *bufStart;
222  uint8_t *bufEnd;
227  uint8_t *readPtr;
228  // how many lines the fetch unit may buffer
230  // maximum size (in number of insts) of the WF's IB
232  // maximum size (in bytes) of this fetch buffer
237  // wavefront whose IB is serviced by this fetch buffer
239  TheGpuISA::Decoder *_decoder;
240  };
241 
242  class SystemHubEvent : public Event
243  {
246 
247  public:
249  : fetchUnit(fetch_unit), reqPkt(pkt)
250  {
252  }
253 
254  void process();
255  };
256 
257  bool timingSim;
259  TheGpuISA::Decoder decoder;
260 
261  // Fetch scheduler; Selects one wave from
262  // the fetch queue for instruction fetching.
263  // The selection is made according to
264  // a scheduling policy
266 
267  // Stores the list of waves that are
268  // ready to be fetched this cycle
270 
271  // Stores the fetch status of all waves dispatched to this SIMD.
272  // TRUE implies the wave is ready to fetch and is already
273  // moved to fetchQueue
275 
276  // Pointer to list of waves dispatched on to this SIMD unit
278  // holds the fetch buffers. each wave has 1 entry.
287 };
288 
289 } // namespace gem5
290 
291 #endif // __FETCH_UNIT_HH__
gem5::FetchUnit::FetchBufDesc::_decoder
TheGpuISA::Decoder * _decoder
Definition: fetch_unit.hh:239
gem5::FetchUnit::SystemHubEvent::reqPkt
PacketPtr reqPkt
Definition: fetch_unit.hh:245
gem5::FetchUnit::SystemHubEvent::fetchUnit
FetchUnit * fetchUnit
Definition: fetch_unit.hh:244
gem5::FetchUnit::~FetchUnit
~FetchUnit()
Definition: fetch_unit.cc:58
gem5::FetchUnit::flushBuf
void flushBuf(int wfSlotId)
Definition: fetch_unit.cc:333
gem5::FetchUnit::FetchBufDesc::maxIbSize
int maxIbSize
Definition: fetch_unit.hh:231
gem5::FetchUnit::FetchBufDesc::cacheLineSize
int cacheLineSize
Definition: fetch_unit.hh:234
gem5::FetchUnit::FetchBufDesc::decoder
void decoder(TheGpuISA::Decoder *dec)
Definition: fetch_unit.hh:168
gem5::Wavefront
Definition: wavefront.hh:60
gem5::FetchUnit::FetchBufDesc::fetchDepth
int fetchDepth
Definition: fetch_unit.hh:229
gem5::FetchUnit::SystemHubEvent
Definition: fetch_unit.hh:242
gem5::FetchUnit::FetchBufDesc::bufferedLines
int bufferedLines() const
Definition: fetch_unit.hh:102
gem5::FetchUnit::FetchBufDesc::~FetchBufDesc
~FetchBufDesc()
Definition: fetch_unit.hh:84
gem5::FetchUnit::timingSim
bool timingSim
Definition: fetch_unit.hh:257
gem5::FetchUnit::FetchBufDesc::FetchBufDesc
FetchBufDesc()
Definition: fetch_unit.hh:77
sc_dt::list
static scfx_rep_node * list
Definition: scfx_rep.cc:368
gem5::FetchUnit::FetchBufDesc::splitDecode
bool splitDecode() const
check if the next instruction to be processed out of the fetch buffer is split across the end/beginni...
Definition: fetch_unit.cc:636
gem5::FetchUnit
Definition: fetch_unit.hh:55
gem5::FetchUnit::fetchDepth
int fetchDepth
number of cache lines we can fetch and buffer.
Definition: fetch_unit.hh:286
std::vector
STL vector class.
Definition: stl.hh:37
gem5::FetchUnit::fetchBuf
std::vector< FetchBufDesc > fetchBuf
Definition: fetch_unit.hh:279
gem5::FetchUnit::FetchBufDesc::pcBuffered
bool pcBuffered(Addr pc) const
Definition: fetch_unit.hh:174
gem5::FetchUnit::init
void init()
Definition: fetch_unit.cc:65
gem5::FetchUnit::FetchBufDesc::maxFbSize
int maxFbSize
Definition: fetch_unit.hh:233
gem5::FetchUnit::FetchBufDesc::hasFreeSpace
bool hasFreeSpace() const
Definition: fetch_unit.hh:105
gem5::Event::setFlags
void setFlags(Flags _flags)
Definition: eventq.hh:328
packet.hh
gem5::EventBase::AutoDelete
static const FlagsType AutoDelete
Definition: eventq.hh:107
gem5::FetchUnit::fetchQueue
std::vector< Wavefront * > fetchQueue
Definition: fetch_unit.hh:269
gem5::FetchUnit::FetchBufDesc::fetchDone
void fetchDone(Addr vaddr)
Definition: fetch_unit.cc:472
gem5::FetchUnit::FetchBufDesc::reservedBuf
uint8_t * reservedBuf(Addr vaddr) const
return a pointer to the raw fetch buffer data.
Definition: fetch_unit.hh:120
gem5::FetchUnit::FetchBufDesc::wavefront
Wavefront * wavefront
Definition: fetch_unit.hh:238
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::FetchUnit::decoder
TheGpuISA::Decoder decoder
Definition: fetch_unit.hh:259
gem5::FetchUnit::FetchBufDesc::readPtr
uint8_t * readPtr
pointer that points to the next chunk of inst data to be decoded.
Definition: fetch_unit.hh:227
gem5::FetchUnit::FetchBufDesc::nextFetchAddr
Addr nextFetchAddr()
Definition: fetch_unit.cc:392
gem5::FetchUnit::FetchBufDesc::flushBuf
void flushBuf()
Definition: fetch_unit.cc:370
gem5::FetchUnit::FetchBufDesc::bufferedAndReservedLines
int bufferedAndReservedLines() const
Definition: fetch_unit.hh:97
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Event
Definition: eventq.hh:251
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::FetchUnit::initiateFetch
void initiateFetch(Wavefront *wavefront)
Definition: fetch_unit.cc:136
gem5::FetchUnit::FetchBufDesc::decodeSplitInst
void decodeSplitInst()
Definition: fetch_unit.cc:598
gem5::FetchUnit::FetchBufDesc
fetch buffer descriptor.
Definition: fetch_unit.hh:74
gem5::FetchUnit::FetchBufDesc::bufEnd
uint8_t * bufEnd
Definition: fetch_unit.hh:222
gem5::FetchUnit::FetchUnit
FetchUnit(const ComputeUnitParams &p, ComputeUnit &cu)
Definition: fetch_unit.cc:52
gem5::FetchUnit::FetchBufDesc::fetchBytesRemaining
int fetchBytesRemaining() const
calculates the number of fetched bytes that have yet to be decoded.
Definition: fetch_unit.cc:648
gem5::FetchUnit::FetchBufDesc::decodeInsts
void decodeInsts()
each time the fetch stage is ticked, we check if there are any data in the fetch buffer that may be d...
Definition: fetch_unit.cc:560
gem5::FetchUnit::SystemHubEvent::process
void process()
Definition: fetch_unit.cc:669
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
scheduler.hh
gem5::FetchUnit::bindWaveList
void bindWaveList(std::vector< Wavefront * > *list)
Definition: fetch_unit.cc:339
gem5::FetchUnit::FetchBufDesc::isReserved
bool isReserved(Addr vaddr) const
returns true if there is an entry reserved for this address, and false otherwise
Definition: fetch_unit.hh:134
gem5::FetchUnit::FetchBufDesc::allocateBuf
void allocateBuf(int fetch_depth, int cache_line_size, Wavefront *wf)
allocate the fetch buffer space, and set the fetch depth (number of lines that may be buffered),...
Definition: fetch_unit.cc:346
gem5::FetchUnit::FetchBufDesc::bufStart
uint8_t * bufStart
raw instruction buffer.
Definition: fetch_unit.hh:221
gem5::FetchUnit::FetchBufDesc::reserveBuf
void reserveBuf(Addr vaddr)
reserve an entry in the fetch buffer for PC = vaddr,
Definition: fetch_unit.cc:447
gem5::FetchUnit::fetchScheduler
Scheduler fetchScheduler
Definition: fetch_unit.hh:265
gem5::FetchUnit::FetchBufDesc::checkWaveReleaseBuf
void checkWaveReleaseBuf()
checks if the wavefront can release any of its fetch buffer entries.
Definition: fetch_unit.cc:503
gem5::FetchUnit::SystemHubEvent::SystemHubEvent
SystemHubEvent(PacketPtr pkt, FetchUnit *fetch_unit)
Definition: fetch_unit.hh:248
types.hh
std::deque< uint8_t * >
gem5::FetchUnit::globalFetchUnitID
static uint32_t globalFetchUnitID
Definition: fetch_unit.hh:67
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::FetchUnit::FetchBufDesc::cacheLineBits
int cacheLineBits
Definition: fetch_unit.hh:235
gem5::FetchUnit::waveList
std::vector< Wavefront * > * waveList
Definition: fetch_unit.hh:277
gem5::FetchUnit::FetchBufDesc::restartFromBranch
bool restartFromBranch
Definition: fetch_unit.hh:236
gem5::Scheduler
Definition: scheduler.hh:44
gem5::FetchUnit::fetchStatusQueue
std::vector< std::pair< Wavefront *, bool > > fetchStatusQueue
Definition: fetch_unit.hh:274
gem5::FetchUnit::FetchBufDesc::bufferedBytes
int bufferedBytes() const
Definition: fetch_unit.hh:103
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::FetchUnit::FetchBufDesc::bufferedPCs
std::map< Addr, uint8_t * > bufferedPCs
the set of PCs (fetch addresses) that are currently buffered.
Definition: fetch_unit.hh:204
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::FetchUnit::computeUnit
ComputeUnit & computeUnit
Definition: fetch_unit.hh:258
gem5::FetchUnit::FetchBufDesc::reservedLines
int reservedLines() const
Definition: fetch_unit.hh:104
gem5::FetchUnit::exec
void exec()
Definition: fetch_unit.cc:84
gem5::FetchUnit::FetchBufDesc::hasFetchDataToProcess
bool hasFetchDataToProcess() const
checks if the buffer contains valid data.
Definition: fetch_unit.cc:497
gem5::FetchUnit::FetchBufDesc::reservedPCs
std::map< Addr, uint8_t * > reservedPCs
Definition: fetch_unit.hh:205
gem5::FetchUnit::FetchBufDesc::freeList
std::deque< uint8_t * > freeList
represents the fetch buffer free list.
Definition: fetch_unit.hh:215
gem5::FetchUnit::fetch
void fetch(PacketPtr pkt, Wavefront *wavefront)
Definition: fetch_unit.cc:230
gem5::FetchUnit::processFetchReturn
void processFetchReturn(PacketPtr pkt)
Definition: fetch_unit.cc:307
eventq.hh

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