gem5  v22.1.0.0
Public Member Functions | Public Attributes | Static Public Attributes | Private Member Functions | Private Attributes | List of all members
gem5::HSAQueueEntry Class Reference

#include <hsa_queue_entry.hh>

Public Member Functions

 HSAQueueEntry (std::string kernel_name, uint32_t queue_id, int dispatch_id, void *disp_pkt, AMDKernelCode *akc, Addr host_pkt_addr, Addr code_addr)
 
const std::string & kernelName () const
 
int wgSize (int dim) const
 
int gridSize (int dim) const
 
int numVectorRegs () const
 
int numScalarRegs () const
 
uint32_t queueId () const
 
int dispatchId () const
 
void * dispPktPtr ()
 
Addr hostDispPktAddr () const
 
Addr completionSignal () const
 
Addr codeAddr () const
 
Addr kernargAddr () const
 
int ldsSize () const
 
int privMemPerItem () const
 
int contextId () const
 
bool dispComplete () const
 
int wgId (int dim) const
 
void wgId (int dim, int val)
 
int globalWgId () const
 
void globalWgId (int val)
 
int numWg (int dim) const
 
void notifyWgCompleted ()
 
int numWgCompleted () const
 
int numWgTotal () const
 
void markWgDispatch ()
 
int numWgAtBarrier () const
 
bool vgprBitEnabled (int bit) const
 
bool sgprBitEnabled (int bit) const
 
int outstandingInvs ()
 
bool isInvStarted ()
 Whether invalidate has started or finished -1 is the initial value indicating inv has not started for the kernel. More...
 
void updateOutstandingInvs (int val)
 update the number of pending invalidate requests More...
 
void markInvDone ()
 Forcefully change the state to be inv done. More...
 
bool isInvDone () const
 Is invalidate done? More...
 
int outstandingWbs () const
 
void updateOutstandingWbs (int val)
 Update the number of pending writeback requests. More...
 

Public Attributes

Addr hostAMDQueueAddr
 Host-side addr of the amd_queue_t on which this task was queued. More...
 
_amd_queue_t amdQueue
 Keep a copy of the AMD HSA queue because we need info from some of its fields to initialize register state. More...
 

Static Public Attributes

static const int MAX_DIM = 3
 

Private Member Functions

void parseKernelCode (AMDKernelCode *akc)
 

Private Attributes

std::string kernName
 
std::array< int, MAX_DIM_wgSize
 
std::array< int, MAX_DIM_gridSize
 
int numVgprs
 
int numSgprs
 
uint32_t _queueId
 
int _dispatchId
 
void * dispPkt
 
Addr _hostDispPktAddr
 
Addr _completionSignal
 
Addr codeAddress
 
Addr kernargAddress
 
int _outstandingInvs
 Number of outstanding invs for the kernel. More...
 
int _outstandingWbs
 Number of outstanding wbs for the kernel values: 0: 1)initial value, flush has not started for the kernel 2)+1->0: all wb requests are finished, i.e., flush done ?: positive value, indicating the number of pending wb requests. More...
 
int _ldsSize
 
int _privMemPerItem
 
int _contextId
 
std::array< int, MAX_DIM_wgId
 
std::array< int, MAX_DIM_numWg
 
int _numWgTotal
 
int numWgArrivedAtBarrier
 
int _numWgCompleted
 
int _globalWgId
 
bool dispatchComplete
 
std::bitset< NumVectorInitFieldsinitialVgprState
 
std::bitset< NumScalarInitFieldsinitialSgprState
 

Detailed Description

Definition at line 59 of file hsa_queue_entry.hh.

Constructor & Destructor Documentation

◆ HSAQueueEntry()

gem5::HSAQueueEntry::HSAQueueEntry ( std::string  kernel_name,
uint32_t  queue_id,
int  dispatch_id,
void *  disp_pkt,
AMDKernelCode akc,
Addr  host_pkt_addr,
Addr  code_addr 
)
inline

Definition at line 62 of file hsa_queue_entry.hh.

Member Function Documentation

◆ codeAddr()

Addr gem5::HSAQueueEntry::codeAddr ( ) const
inline

◆ completionSignal()

Addr gem5::HSAQueueEntry::completionSignal ( ) const
inline

◆ contextId()

int gem5::HSAQueueEntry::contextId ( ) const
inline

Definition at line 210 of file hsa_queue_entry.hh.

◆ dispatchId()

int gem5::HSAQueueEntry::dispatchId ( ) const
inline

◆ dispComplete()

bool gem5::HSAQueueEntry::dispComplete ( ) const
inline

Definition at line 216 of file hsa_queue_entry.hh.

Referenced by gem5::Shader::dispatchWorkgroups().

◆ dispPktPtr()

void* gem5::HSAQueueEntry::dispPktPtr ( )
inline

Definition at line 172 of file hsa_queue_entry.hh.

◆ globalWgId() [1/2]

int gem5::HSAQueueEntry::globalWgId ( ) const
inline

◆ globalWgId() [2/2]

void gem5::HSAQueueEntry::globalWgId ( int  val)
inline

Definition at line 242 of file hsa_queue_entry.hh.

References gem5::X86ISA::val.

◆ gridSize()

int gem5::HSAQueueEntry::gridSize ( int  dim) const
inline

◆ hostDispPktAddr()

Addr gem5::HSAQueueEntry::hostDispPktAddr ( ) const
inline

Definition at line 178 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState().

◆ isInvDone()

bool gem5::HSAQueueEntry::isInvDone ( ) const
inline

Is invalidate done?

Definition at line 367 of file hsa_queue_entry.hh.

Referenced by gem5::ComputeUnit::dispWorkgroup().

◆ isInvStarted()

bool gem5::HSAQueueEntry::isInvStarted ( )
inline

Whether invalidate has started or finished -1 is the initial value indicating inv has not started for the kernel.

Definition at line 337 of file hsa_queue_entry.hh.

Referenced by gem5::Shader::prepareInvalidate().

◆ kernargAddr()

Addr gem5::HSAQueueEntry::kernargAddr ( ) const
inline

Definition at line 196 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState().

◆ kernelName()

const std::string& gem5::HSAQueueEntry::kernelName ( ) const
inline

Definition at line 128 of file hsa_queue_entry.hh.

Referenced by gem5::GPUDispatcher::dispatch().

◆ ldsSize()

int gem5::HSAQueueEntry::ldsSize ( ) const
inline

◆ markInvDone()

void gem5::HSAQueueEntry::markInvDone ( )
inline

Forcefully change the state to be inv done.

Definition at line 358 of file hsa_queue_entry.hh.

◆ markWgDispatch()

void gem5::HSAQueueEntry::markWgDispatch ( )
inline

Definition at line 273 of file hsa_queue_entry.hh.

Referenced by gem5::Shader::dispatchWorkgroups().

◆ notifyWgCompleted()

void gem5::HSAQueueEntry::notifyWgCompleted ( )
inline

Definition at line 255 of file hsa_queue_entry.hh.

◆ numScalarRegs()

int gem5::HSAQueueEntry::numScalarRegs ( ) const
inline

◆ numVectorRegs()

int gem5::HSAQueueEntry::numVectorRegs ( ) const
inline

◆ numWg()

int gem5::HSAQueueEntry::numWg ( int  dim) const
inline

Definition at line 248 of file hsa_queue_entry.hh.

Referenced by gem5::ComputeUnit::startWavefront().

◆ numWgAtBarrier()

int gem5::HSAQueueEntry::numWgAtBarrier ( ) const
inline

Definition at line 294 of file hsa_queue_entry.hh.

◆ numWgCompleted()

int gem5::HSAQueueEntry::numWgCompleted ( ) const
inline

Definition at line 261 of file hsa_queue_entry.hh.

◆ numWgTotal()

int gem5::HSAQueueEntry::numWgTotal ( ) const
inline

Definition at line 267 of file hsa_queue_entry.hh.

◆ outstandingInvs()

int gem5::HSAQueueEntry::outstandingInvs ( )
inline

Definition at line 327 of file hsa_queue_entry.hh.

Referenced by gem5::Shader::prepareInvalidate().

◆ outstandingWbs()

int gem5::HSAQueueEntry::outstandingWbs ( ) const
inline

Definition at line 374 of file hsa_queue_entry.hh.

◆ parseKernelCode()

void gem5::HSAQueueEntry::parseKernelCode ( AMDKernelCode akc)
inlineprivate

◆ privMemPerItem()

int gem5::HSAQueueEntry::privMemPerItem ( ) const
inline

◆ queueId()

uint32_t gem5::HSAQueueEntry::queueId ( ) const
inline

◆ sgprBitEnabled()

bool gem5::HSAQueueEntry::sgprBitEnabled ( int  bit) const
inline

Definition at line 304 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState().

◆ updateOutstandingInvs()

void gem5::HSAQueueEntry::updateOutstandingInvs ( int  val)
inline

update the number of pending invalidate requests

val: negative to decrement, positive to increment

Definition at line 348 of file hsa_queue_entry.hh.

References gem5::X86ISA::val.

◆ updateOutstandingWbs()

void gem5::HSAQueueEntry::updateOutstandingWbs ( int  val)
inline

Update the number of pending writeback requests.

val: negative to decrement, positive to increment

Definition at line 385 of file hsa_queue_entry.hh.

References gem5::X86ISA::val.

◆ vgprBitEnabled()

bool gem5::HSAQueueEntry::vgprBitEnabled ( int  bit) const
inline

Definition at line 299 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState().

◆ wgId() [1/2]

int gem5::HSAQueueEntry::wgId ( int  dim) const
inline

◆ wgId() [2/2]

void gem5::HSAQueueEntry::wgId ( int  dim,
int  val 
)
inline

Definition at line 229 of file hsa_queue_entry.hh.

References gem5::X86ISA::val.

◆ wgSize()

int gem5::HSAQueueEntry::wgSize ( int  dim) const
inline

Member Data Documentation

◆ _completionSignal

Addr gem5::HSAQueueEntry::_completionSignal
private

Definition at line 454 of file hsa_queue_entry.hh.

◆ _contextId

int gem5::HSAQueueEntry::_contextId
private

Definition at line 478 of file hsa_queue_entry.hh.

◆ _dispatchId

int gem5::HSAQueueEntry::_dispatchId
private

Definition at line 448 of file hsa_queue_entry.hh.

◆ _globalWgId

int gem5::HSAQueueEntry::_globalWgId
private

Definition at line 485 of file hsa_queue_entry.hh.

◆ _gridSize

std::array<int, MAX_DIM> gem5::HSAQueueEntry::_gridSize
private

Definition at line 441 of file hsa_queue_entry.hh.

◆ _hostDispPktAddr

Addr gem5::HSAQueueEntry::_hostDispPktAddr
private

Definition at line 452 of file hsa_queue_entry.hh.

◆ _ldsSize

int gem5::HSAQueueEntry::_ldsSize
private

Definition at line 476 of file hsa_queue_entry.hh.

◆ _numWg

std::array<int, MAX_DIM> gem5::HSAQueueEntry::_numWg
private

Definition at line 480 of file hsa_queue_entry.hh.

◆ _numWgCompleted

int gem5::HSAQueueEntry::_numWgCompleted
private

Definition at line 484 of file hsa_queue_entry.hh.

◆ _numWgTotal

int gem5::HSAQueueEntry::_numWgTotal
private

Definition at line 481 of file hsa_queue_entry.hh.

◆ _outstandingInvs

int gem5::HSAQueueEntry::_outstandingInvs
private

Number of outstanding invs for the kernel.

values: -1: initial value, invalidate has not started for the kernel 0: 1)-1->0, about to start (a transient state, added in the same cycle) 2)+1->0, all inv requests are finished, i.e., invalidate done ?: positive value, indicating the number of pending inv requests

Definition at line 467 of file hsa_queue_entry.hh.

◆ _outstandingWbs

int gem5::HSAQueueEntry::_outstandingWbs
private

Number of outstanding wbs for the kernel values: 0: 1)initial value, flush has not started for the kernel 2)+1->0: all wb requests are finished, i.e., flush done ?: positive value, indicating the number of pending wb requests.

Definition at line 475 of file hsa_queue_entry.hh.

◆ _privMemPerItem

int gem5::HSAQueueEntry::_privMemPerItem
private

Definition at line 477 of file hsa_queue_entry.hh.

◆ _queueId

uint32_t gem5::HSAQueueEntry::_queueId
private

Definition at line 447 of file hsa_queue_entry.hh.

◆ _wgId

std::array<int, MAX_DIM> gem5::HSAQueueEntry::_wgId
private

Definition at line 479 of file hsa_queue_entry.hh.

◆ _wgSize

std::array<int, MAX_DIM> gem5::HSAQueueEntry::_wgSize
private

Definition at line 439 of file hsa_queue_entry.hh.

◆ amdQueue

_amd_queue_t gem5::HSAQueueEntry::amdQueue

Keep a copy of the AMD HSA queue because we need info from some of its fields to initialize register state.

Definition at line 320 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState(), gem5::GPUCommandProcessor::MQDDmaEvent(), gem5::GPUCommandProcessor::ReadDispIdOffsetDmaEvent(), and gem5::GPUCommandProcessor::WaitScratchDmaEvent().

◆ codeAddress

Addr gem5::HSAQueueEntry::codeAddress
private

Definition at line 456 of file hsa_queue_entry.hh.

◆ dispatchComplete

bool gem5::HSAQueueEntry::dispatchComplete
private

Definition at line 486 of file hsa_queue_entry.hh.

◆ dispPkt

void* gem5::HSAQueueEntry::dispPkt
private

Definition at line 450 of file hsa_queue_entry.hh.

◆ hostAMDQueueAddr

Addr gem5::HSAQueueEntry::hostAMDQueueAddr

Host-side addr of the amd_queue_t on which this task was queued.

Definition at line 313 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState(), gem5::GPUCommandProcessor::ReadDispIdOffsetDmaEvent(), and gem5::GPUCommandProcessor::WaitScratchDmaEvent().

◆ initialSgprState

std::bitset<NumScalarInitFields> gem5::HSAQueueEntry::initialSgprState
private

Definition at line 489 of file hsa_queue_entry.hh.

◆ initialVgprState

std::bitset<NumVectorInitFields> gem5::HSAQueueEntry::initialVgprState
private

Definition at line 488 of file hsa_queue_entry.hh.

◆ kernargAddress

Addr gem5::HSAQueueEntry::kernargAddress
private

Definition at line 458 of file hsa_queue_entry.hh.

◆ kernName

std::string gem5::HSAQueueEntry::kernName
private

Definition at line 437 of file hsa_queue_entry.hh.

◆ MAX_DIM

const int gem5::HSAQueueEntry::MAX_DIM = 3
static

◆ numSgprs

int gem5::HSAQueueEntry::numSgprs
private

Definition at line 445 of file hsa_queue_entry.hh.

◆ numVgprs

int gem5::HSAQueueEntry::numVgprs
private

Definition at line 443 of file hsa_queue_entry.hh.

◆ numWgArrivedAtBarrier

int gem5::HSAQueueEntry::numWgArrivedAtBarrier
private

Definition at line 482 of file hsa_queue_entry.hh.


The documentation for this class was generated from the following file:

Generated on Wed Dec 21 2022 10:23:24 for gem5 by doxygen 1.9.1