gem5 v24.0.0.0
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Public Member Functions | Public Attributes | Static Public Attributes | Private Member Functions | Private Attributes | List of all members
gem5::HSAQueueEntry Class Reference

#include <hsa_queue_entry.hh>

Public Member Functions

 HSAQueueEntry (std::string kernel_name, uint32_t queue_id, int dispatch_id, void *disp_pkt, AMDKernelCode *akc, Addr host_pkt_addr, Addr code_addr, GfxVersion gfx_version)
 
const GfxVersion & gfxVersion () const
 
const std::string & kernelName () const
 
int wgSize (int dim) const
 
int gridSize (int dim) const
 
int numVectorRegs () const
 
int numScalarRegs () const
 
uint32_t queueId () const
 
int dispatchId () const
 
void * dispPktPtr ()
 
Addr hostDispPktAddr () const
 
Addr completionSignal () const
 
Addr codeAddr () const
 
Addr kernargAddr () const
 
int ldsSize () const
 
int privMemPerItem () const
 
int contextId () const
 
bool dispComplete () const
 
int wgId (int dim) const
 
void wgId (int dim, int val)
 
int globalWgId () const
 
void globalWgId (int val)
 
int numWg (int dim) const
 
void notifyWgCompleted ()
 
int numWgCompleted () const
 
int numWgTotal () const
 
void markWgDispatch ()
 
int numWgAtBarrier () const
 
bool vgprBitEnabled (int bit) const
 
bool sgprBitEnabled (int bit) const
 
int outstandingInvs ()
 
bool isInvStarted ()
 Whether invalidate has started or finished -1 is the initial value indicating inv has not started for the kernel.
 
void updateOutstandingInvs (int val)
 update the number of pending invalidate requests
 
void markInvDone ()
 Forcefully change the state to be inv done.
 
bool isInvDone () const
 Is invalidate done?
 
int outstandingWbs () const
 
void updateOutstandingWbs (int val)
 Update the number of pending writeback requests.
 
unsigned accumOffset () const
 

Public Attributes

Addr hostAMDQueueAddr
 Host-side addr of the amd_queue_t on which this task was queued.
 
_amd_queue_t amdQueue
 Keep a copy of the AMD HSA queue because we need info from some of its fields to initialize register state.
 

Static Public Attributes

static const int MAX_DIM = 3
 

Private Member Functions

void parseKernelCode (AMDKernelCode *akc)
 

Private Attributes

GfxVersion _gfxVersion
 
std::string kernName
 
std::array< int, MAX_DIM > _wgSize
 
std::array< int, MAX_DIM > _gridSize
 
int numVgprs
 
int numSgprs
 
uint32_t _queueId
 
int _dispatchId
 
void * dispPkt
 
Addr _hostDispPktAddr
 
Addr _completionSignal
 
Addr codeAddress
 
Addr kernargAddress
 
int _outstandingInvs
 Number of outstanding invs for the kernel.
 
int _outstandingWbs
 Number of outstanding wbs for the kernel values: 0: 1)initial value, flush has not started for the kernel 2)+1->0: all wb requests are finished, i.e., flush done ?: positive value, indicating the number of pending wb requests.
 
int _ldsSize
 
int _privMemPerItem
 
int _contextId
 
std::array< int, MAX_DIM > _wgId
 
std::array< int, MAX_DIM > _numWg
 
int _numWgTotal
 
int numWgArrivedAtBarrier
 
int _numWgCompleted
 
int _globalWgId
 
bool dispatchComplete
 
std::bitset< NumVectorInitFields > initialVgprState
 
std::bitset< NumScalarInitFields > initialSgprState
 
unsigned _accumOffset
 

Detailed Description

Definition at line 60 of file hsa_queue_entry.hh.

Constructor & Destructor Documentation

◆ HSAQueueEntry()

gem5::HSAQueueEntry::HSAQueueEntry ( std::string kernel_name,
uint32_t queue_id,
int dispatch_id,
void * disp_pkt,
AMDKernelCode * akc,
Addr host_pkt_addr,
Addr code_addr,
GfxVersion gfx_version )
inline

Definition at line 63 of file hsa_queue_entry.hh.

Member Function Documentation

◆ accumOffset()

unsigned gem5::HSAQueueEntry::accumOffset ( ) const
inline

Definition at line 405 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState().

◆ codeAddr()

Addr gem5::HSAQueueEntry::codeAddr ( ) const
inline

Definition at line 203 of file hsa_queue_entry.hh.

Referenced by gem5::GPUCommandProcessor::dispatchKernelObject(), and gem5::ComputeUnit::startWavefront().

◆ completionSignal()

Addr gem5::HSAQueueEntry::completionSignal ( ) const
inline

Definition at line 197 of file hsa_queue_entry.hh.

Referenced by gem5::GPUCommandProcessor::dispatchKernelObject(), and gem5::GPUCommandProcessor::submitAgentDispatchPkt().

◆ contextId()

int gem5::HSAQueueEntry::contextId ( ) const
inline

Definition at line 223 of file hsa_queue_entry.hh.

◆ dispatchId()

int gem5::HSAQueueEntry::dispatchId ( ) const
inline

Definition at line 179 of file hsa_queue_entry.hh.

Referenced by gem5::GPUDispatcher::dispatch(), gem5::ComputeUnit::dispWorkgroup(), gem5::Wavefront::initRegState(), gem5::Shader::prepareInvalidate(), and gem5::ComputeUnit::startWavefront().

◆ dispComplete()

bool gem5::HSAQueueEntry::dispComplete ( ) const
inline

Definition at line 229 of file hsa_queue_entry.hh.

Referenced by gem5::Shader::dispatchWorkgroups().

◆ dispPktPtr()

void * gem5::HSAQueueEntry::dispPktPtr ( )
inline

Definition at line 185 of file hsa_queue_entry.hh.

Referenced by gem5::GPUCommandProcessor::dispatchKernelObject().

◆ gfxVersion()

const GfxVersion & gem5::HSAQueueEntry::gfxVersion ( ) const
inline

Definition at line 135 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState().

◆ globalWgId() [1/2]

int gem5::HSAQueueEntry::globalWgId ( ) const
inline

Definition at line 249 of file hsa_queue_entry.hh.

Referenced by gem5::Shader::dispatchWorkgroups(), gem5::ComputeUnit::dispWorkgroup(), and gem5::ComputeUnit::startWavefront().

◆ globalWgId() [2/2]

void gem5::HSAQueueEntry::globalWgId ( int val)
inline

Definition at line 255 of file hsa_queue_entry.hh.

References gem5::X86ISA::val.

◆ gridSize()

int gem5::HSAQueueEntry::gridSize ( int dim) const
inline

Definition at line 154 of file hsa_queue_entry.hh.

Referenced by gem5::ComputeUnit::fillKernelState(), and gem5::ComputeUnit::hasDispResources().

◆ hostDispPktAddr()

Addr gem5::HSAQueueEntry::hostDispPktAddr ( ) const
inline

Definition at line 191 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState().

◆ isInvDone()

bool gem5::HSAQueueEntry::isInvDone ( ) const
inline

Is invalidate done?

Definition at line 380 of file hsa_queue_entry.hh.

Referenced by gem5::ComputeUnit::dispWorkgroup().

◆ isInvStarted()

bool gem5::HSAQueueEntry::isInvStarted ( )
inline

Whether invalidate has started or finished -1 is the initial value indicating inv has not started for the kernel.

Definition at line 350 of file hsa_queue_entry.hh.

Referenced by gem5::Shader::prepareInvalidate().

◆ kernargAddr()

Addr gem5::HSAQueueEntry::kernargAddr ( ) const
inline

Definition at line 209 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState().

◆ kernelName()

const std::string & gem5::HSAQueueEntry::kernelName ( ) const
inline

Definition at line 141 of file hsa_queue_entry.hh.

Referenced by gem5::GPUDispatcher::dispatch().

◆ ldsSize()

int gem5::HSAQueueEntry::ldsSize ( ) const
inline

Definition at line 215 of file hsa_queue_entry.hh.

Referenced by gem5::ComputeUnit::dispWorkgroup(), and gem5::ComputeUnit::hasDispResources().

◆ markInvDone()

void gem5::HSAQueueEntry::markInvDone ( )
inline

Forcefully change the state to be inv done.

Definition at line 371 of file hsa_queue_entry.hh.

◆ markWgDispatch()

void gem5::HSAQueueEntry::markWgDispatch ( )
inline

Definition at line 286 of file hsa_queue_entry.hh.

Referenced by gem5::Shader::dispatchWorkgroups().

◆ notifyWgCompleted()

void gem5::HSAQueueEntry::notifyWgCompleted ( )
inline

Definition at line 268 of file hsa_queue_entry.hh.

◆ numScalarRegs()

int gem5::HSAQueueEntry::numScalarRegs ( ) const
inline

Definition at line 167 of file hsa_queue_entry.hh.

Referenced by gem5::GPUCommandProcessor::dispatchKernelObject(), gem5::ComputeUnit::dispWorkgroup(), gem5::ComputeUnit::fillKernelState(), and gem5::ComputeUnit::hasDispResources().

◆ numVectorRegs()

int gem5::HSAQueueEntry::numVectorRegs ( ) const
inline

Definition at line 161 of file hsa_queue_entry.hh.

Referenced by gem5::GPUCommandProcessor::dispatchKernelObject(), gem5::ComputeUnit::dispWorkgroup(), gem5::ComputeUnit::fillKernelState(), and gem5::ComputeUnit::hasDispResources().

◆ numWg()

int gem5::HSAQueueEntry::numWg ( int dim) const
inline

Definition at line 261 of file hsa_queue_entry.hh.

Referenced by gem5::ComputeUnit::startWavefront().

◆ numWgAtBarrier()

int gem5::HSAQueueEntry::numWgAtBarrier ( ) const
inline

Definition at line 307 of file hsa_queue_entry.hh.

◆ numWgCompleted()

int gem5::HSAQueueEntry::numWgCompleted ( ) const
inline

Definition at line 274 of file hsa_queue_entry.hh.

◆ numWgTotal()

int gem5::HSAQueueEntry::numWgTotal ( ) const
inline

Definition at line 280 of file hsa_queue_entry.hh.

◆ outstandingInvs()

int gem5::HSAQueueEntry::outstandingInvs ( )
inline

Definition at line 340 of file hsa_queue_entry.hh.

Referenced by gem5::Shader::prepareInvalidate().

◆ outstandingWbs()

int gem5::HSAQueueEntry::outstandingWbs ( ) const
inline

Definition at line 387 of file hsa_queue_entry.hh.

◆ parseKernelCode()

void gem5::HSAQueueEntry::parseKernelCode ( AMDKernelCode * akc)
inlineprivate

set the enable bits for the initial SGPR state

set the enable bits for the initial VGPR state. the workitem Id in the X dimension is always initialized.

Definition at line 412 of file hsa_queue_entry.hh.

References gem5::DispatchId, gem5::DispatchPtr, gem5::GEM5_PACKED::enable_private_segment, gem5::GEM5_PACKED::enable_sgpr_dispatch_id, gem5::GEM5_PACKED::enable_sgpr_dispatch_ptr, gem5::GEM5_PACKED::enable_sgpr_flat_scratch_init, gem5::GEM5_PACKED::enable_sgpr_kernarg_segment_ptr, gem5::GEM5_PACKED::enable_sgpr_private_segment_buffer, gem5::GEM5_PACKED::enable_sgpr_private_segment_size, gem5::GEM5_PACKED::enable_sgpr_queue_ptr, gem5::GEM5_PACKED::enable_sgpr_workgroup_id_x, gem5::GEM5_PACKED::enable_sgpr_workgroup_id_y, gem5::GEM5_PACKED::enable_sgpr_workgroup_id_z, gem5::GEM5_PACKED::enable_sgpr_workgroup_info, gem5::GEM5_PACKED::enable_vgpr_workitem_id, gem5::FlatScratchInit, gem5::KernargSegPtr, gem5::PrivateSegBuf, gem5::PrivateSegSize, gem5::PrivSegWaveByteOffset, gem5::QueuePtr, gem5::WorkgroupIdX, gem5::WorkgroupIdY, gem5::WorkgroupIdZ, gem5::WorkgroupInfo, gem5::WorkitemIdX, gem5::WorkitemIdY, and gem5::WorkitemIdZ.

◆ privMemPerItem()

int gem5::HSAQueueEntry::privMemPerItem ( ) const
inline

Definition at line 220 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState(), and gem5::GPUCommandProcessor::MQDDmaEvent().

◆ queueId()

uint32_t gem5::HSAQueueEntry::queueId ( ) const
inline

Definition at line 173 of file hsa_queue_entry.hh.

Referenced by gem5::GPUCommandProcessor::dispatchKernelObject(), gem5::GPUCommandProcessor::initABI(), gem5::GPUCommandProcessor::MQDDmaEvent(), and gem5::GPUCommandProcessor::ReadDispIdOffsetDmaEvent().

◆ sgprBitEnabled()

bool gem5::HSAQueueEntry::sgprBitEnabled ( int bit) const
inline

Definition at line 317 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState().

◆ updateOutstandingInvs()

void gem5::HSAQueueEntry::updateOutstandingInvs ( int val)
inline

update the number of pending invalidate requests

val: negative to decrement, positive to increment

Definition at line 361 of file hsa_queue_entry.hh.

References gem5::X86ISA::val.

◆ updateOutstandingWbs()

void gem5::HSAQueueEntry::updateOutstandingWbs ( int val)
inline

Update the number of pending writeback requests.

val: negative to decrement, positive to increment

Definition at line 398 of file hsa_queue_entry.hh.

References gem5::X86ISA::val.

◆ vgprBitEnabled()

bool gem5::HSAQueueEntry::vgprBitEnabled ( int bit) const
inline

Definition at line 312 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState().

◆ wgId() [1/2]

int gem5::HSAQueueEntry::wgId ( int dim) const
inline

Definition at line 235 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::computeActualWgSz(), and gem5::ComputeUnit::hasDispResources().

◆ wgId() [2/2]

void gem5::HSAQueueEntry::wgId ( int dim,
int val )
inline

Definition at line 242 of file hsa_queue_entry.hh.

References gem5::X86ISA::val.

◆ wgSize()

int gem5::HSAQueueEntry::wgSize ( int dim) const
inline

Definition at line 147 of file hsa_queue_entry.hh.

Referenced by gem5::ComputeUnit::fillKernelState(), and gem5::ComputeUnit::hasDispResources().

Member Data Documentation

◆ _accumOffset

unsigned gem5::HSAQueueEntry::_accumOffset
private

Definition at line 506 of file hsa_queue_entry.hh.

◆ _completionSignal

Addr gem5::HSAQueueEntry::_completionSignal
private

Definition at line 469 of file hsa_queue_entry.hh.

◆ _contextId

int gem5::HSAQueueEntry::_contextId
private

Definition at line 493 of file hsa_queue_entry.hh.

◆ _dispatchId

int gem5::HSAQueueEntry::_dispatchId
private

Definition at line 463 of file hsa_queue_entry.hh.

◆ _gfxVersion

GfxVersion gem5::HSAQueueEntry::_gfxVersion
private

Definition at line 450 of file hsa_queue_entry.hh.

◆ _globalWgId

int gem5::HSAQueueEntry::_globalWgId
private

Definition at line 500 of file hsa_queue_entry.hh.

◆ _gridSize

std::array<int, MAX_DIM> gem5::HSAQueueEntry::_gridSize
private

Definition at line 456 of file hsa_queue_entry.hh.

◆ _hostDispPktAddr

Addr gem5::HSAQueueEntry::_hostDispPktAddr
private

Definition at line 467 of file hsa_queue_entry.hh.

◆ _ldsSize

int gem5::HSAQueueEntry::_ldsSize
private

Definition at line 491 of file hsa_queue_entry.hh.

◆ _numWg

std::array<int, MAX_DIM> gem5::HSAQueueEntry::_numWg
private

Definition at line 495 of file hsa_queue_entry.hh.

◆ _numWgCompleted

int gem5::HSAQueueEntry::_numWgCompleted
private

Definition at line 499 of file hsa_queue_entry.hh.

◆ _numWgTotal

int gem5::HSAQueueEntry::_numWgTotal
private

Definition at line 496 of file hsa_queue_entry.hh.

◆ _outstandingInvs

int gem5::HSAQueueEntry::_outstandingInvs
private

Number of outstanding invs for the kernel.

values: -1: initial value, invalidate has not started for the kernel 0: 1)-1->0, about to start (a transient state, added in the same cycle) 2)+1->0, all inv requests are finished, i.e., invalidate done ?: positive value, indicating the number of pending inv requests

Definition at line 482 of file hsa_queue_entry.hh.

◆ _outstandingWbs

int gem5::HSAQueueEntry::_outstandingWbs
private

Number of outstanding wbs for the kernel values: 0: 1)initial value, flush has not started for the kernel 2)+1->0: all wb requests are finished, i.e., flush done ?: positive value, indicating the number of pending wb requests.

Definition at line 490 of file hsa_queue_entry.hh.

◆ _privMemPerItem

int gem5::HSAQueueEntry::_privMemPerItem
private

Definition at line 492 of file hsa_queue_entry.hh.

◆ _queueId

uint32_t gem5::HSAQueueEntry::_queueId
private

Definition at line 462 of file hsa_queue_entry.hh.

◆ _wgId

std::array<int, MAX_DIM> gem5::HSAQueueEntry::_wgId
private

Definition at line 494 of file hsa_queue_entry.hh.

◆ _wgSize

std::array<int, MAX_DIM> gem5::HSAQueueEntry::_wgSize
private

Definition at line 454 of file hsa_queue_entry.hh.

◆ amdQueue

_amd_queue_t gem5::HSAQueueEntry::amdQueue

Keep a copy of the AMD HSA queue because we need info from some of its fields to initialize register state.

Definition at line 333 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState(), gem5::GPUCommandProcessor::MQDDmaEvent(), gem5::GPUCommandProcessor::ReadDispIdOffsetDmaEvent(), and gem5::GPUCommandProcessor::WaitScratchDmaEvent().

◆ codeAddress

Addr gem5::HSAQueueEntry::codeAddress
private

Definition at line 471 of file hsa_queue_entry.hh.

◆ dispatchComplete

bool gem5::HSAQueueEntry::dispatchComplete
private

Definition at line 501 of file hsa_queue_entry.hh.

◆ dispPkt

void* gem5::HSAQueueEntry::dispPkt
private

Definition at line 465 of file hsa_queue_entry.hh.

◆ hostAMDQueueAddr

Addr gem5::HSAQueueEntry::hostAMDQueueAddr

Host-side addr of the amd_queue_t on which this task was queued.

Definition at line 326 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState(), gem5::GPUCommandProcessor::ReadDispIdOffsetDmaEvent(), and gem5::GPUCommandProcessor::WaitScratchDmaEvent().

◆ initialSgprState

std::bitset<NumScalarInitFields> gem5::HSAQueueEntry::initialSgprState
private

Definition at line 504 of file hsa_queue_entry.hh.

◆ initialVgprState

std::bitset<NumVectorInitFields> gem5::HSAQueueEntry::initialVgprState
private

Definition at line 503 of file hsa_queue_entry.hh.

◆ kernargAddress

Addr gem5::HSAQueueEntry::kernargAddress
private

Definition at line 473 of file hsa_queue_entry.hh.

◆ kernName

std::string gem5::HSAQueueEntry::kernName
private

Definition at line 452 of file hsa_queue_entry.hh.

◆ MAX_DIM

const int gem5::HSAQueueEntry::MAX_DIM = 3
static

Definition at line 336 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::computeActualWgSz(), and gem5::ComputeUnit::hasDispResources().

◆ numSgprs

int gem5::HSAQueueEntry::numSgprs
private

Definition at line 460 of file hsa_queue_entry.hh.

◆ numVgprs

int gem5::HSAQueueEntry::numVgprs
private

Definition at line 458 of file hsa_queue_entry.hh.

◆ numWgArrivedAtBarrier

int gem5::HSAQueueEntry::numWgArrivedAtBarrier
private

Definition at line 497 of file hsa_queue_entry.hh.

The documentation for this class was generated from the following file:
Generated on Tue Jun 18 2024 16:24:12 for gem5 by doxygen 1.11.0