_status | gem5::BaseSimpleCPU | protected |
activateContext(ThreadID thread_num) override | gem5::TimingSimpleCPU | |
activeThreads | gem5::BaseSimpleCPU | |
advanceInst(const Fault &fault) | gem5::TimingSimpleCPU | |
advancePC(const Fault &fault) | gem5::BaseSimpleCPU | |
amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) | gem5::BaseSimpleCPU | inlinevirtual |
BaseSimpleCPU(const BaseSimpleCPUParams ¶ms) | gem5::BaseSimpleCPU | |
branchPred | gem5::BaseSimpleCPU | protected |
buildPacket(const RequestPtr &req, bool read) | gem5::TimingSimpleCPU | private |
buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read) | gem5::TimingSimpleCPU | private |
checker | gem5::BaseSimpleCPU | |
checkForInterrupts() | gem5::BaseSimpleCPU | |
checkPcEventQueue() | gem5::BaseSimpleCPU | protected |
completeDataAccess(PacketPtr pkt) | gem5::TimingSimpleCPU | |
completeIfetch(PacketPtr) | gem5::TimingSimpleCPU | |
countInst() | gem5::BaseSimpleCPU | |
curMacroStaticInst | gem5::BaseSimpleCPU | |
curStaticInst | gem5::BaseSimpleCPU | |
curThread | gem5::BaseSimpleCPU | protected |
dcache_pkt | gem5::TimingSimpleCPU | private |
dcachePort | gem5::TimingSimpleCPU | private |
DcacheRetry enum value | gem5::BaseSimpleCPU | protected |
DcacheWaitResponse enum value | gem5::BaseSimpleCPU | protected |
DcacheWaitSwitch enum value | gem5::BaseSimpleCPU | protected |
drain() override | gem5::TimingSimpleCPU | |
drainResume() override | gem5::TimingSimpleCPU | |
DTBWaitResponse enum value | gem5::BaseSimpleCPU | protected |
Faulting enum value | gem5::BaseSimpleCPU | protected |
fetch() | gem5::TimingSimpleCPU | |
fetchEvent | gem5::TimingSimpleCPU | private |
fetchTranslation | gem5::TimingSimpleCPU | private |
finishTranslation(WholeTranslationState *state) | gem5::TimingSimpleCPU | |
getDataPort() override | gem5::TimingSimpleCPU | inlineprotected |
getInstPort() override | gem5::TimingSimpleCPU | inlineprotected |
haltContext(ThreadID thread_num) override | gem5::BaseSimpleCPU | |
handleReadPacket(PacketPtr pkt) | gem5::TimingSimpleCPU | private |
handleWritePacket() | gem5::TimingSimpleCPU | private |
htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause) override | gem5::TimingSimpleCPU | |
icachePort | gem5::TimingSimpleCPU | private |
IcacheRetry enum value | gem5::BaseSimpleCPU | protected |
IcacheWaitResponse enum value | gem5::BaseSimpleCPU | protected |
IcacheWaitSwitch enum value | gem5::BaseSimpleCPU | protected |
Idle enum value | gem5::BaseSimpleCPU | protected |
ifetch_pkt | gem5::TimingSimpleCPU | private |
init() override | gem5::TimingSimpleCPU | |
initiateHtmCmd(Request::Flags flags) override | gem5::TimingSimpleCPU | virtual |
initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override | gem5::TimingSimpleCPU | virtual |
initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override | gem5::TimingSimpleCPU | virtual |
isCpuDrained() const | gem5::TimingSimpleCPU | inlineprivate |
isSquashed() const | gem5::TimingSimpleCPU | inline |
ITBWaitResponse enum value | gem5::BaseSimpleCPU | protected |
postExecute() | gem5::BaseSimpleCPU | |
preExecute() | gem5::BaseSimpleCPU | |
preExecuteTempPC | gem5::BaseSimpleCPU | protected |
previousCycle | gem5::TimingSimpleCPU | private |
printAddr(Addr a) | gem5::TimingSimpleCPU | |
readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) | gem5::BaseSimpleCPU | inlinevirtual |
resetStats() override | gem5::BaseSimpleCPU | |
Running enum value | gem5::BaseSimpleCPU | protected |
sendData(const RequestPtr &req, uint8_t *data, uint64_t *res, bool read) | gem5::TimingSimpleCPU | private |
sendFetch(const Fault &fault, const RequestPtr &req, ThreadContext *tc) | gem5::TimingSimpleCPU | |
sendSplitData(const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read) | gem5::TimingSimpleCPU | private |
serializeThread(CheckpointOut &cp, ThreadID tid) const override | gem5::BaseSimpleCPU | |
serviceInstCountEvents() | gem5::BaseSimpleCPU | |
setupFetchRequest(const RequestPtr &req) | gem5::BaseSimpleCPU | |
Status enum name | gem5::BaseSimpleCPU | protected |
suspendContext(ThreadID thread_num) override | gem5::TimingSimpleCPU | |
swapActiveThread() | gem5::BaseSimpleCPU | protected |
switchOut() override | gem5::TimingSimpleCPU | |
takeOverFrom(BaseCPU *oldCPU) override | gem5::TimingSimpleCPU | |
threadInfo | gem5::BaseSimpleCPU | |
threadSnoop(PacketPtr pkt, ThreadID sender) | gem5::TimingSimpleCPU | private |
TimingSimpleCPU(const TimingSimpleCPUParams ¶ms) | gem5::TimingSimpleCPU | |
totalInsts() const override | gem5::BaseSimpleCPU | |
totalOps() const override | gem5::BaseSimpleCPU | |
traceData | gem5::BaseSimpleCPU | |
traceFault() | gem5::BaseSimpleCPU | protected |
translationFault(const Fault &fault) | gem5::TimingSimpleCPU | private |
tryCompleteDrain() | gem5::TimingSimpleCPU | private |
unserializeThread(CheckpointIn &cp, ThreadID tid) override | gem5::BaseSimpleCPU | |
updateCycleCounts() | gem5::TimingSimpleCPU | private |
verifyMemoryMode() const override | gem5::TimingSimpleCPU | |
wakeup(ThreadID tid) override | gem5::BaseSimpleCPU | |
writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) override | gem5::TimingSimpleCPU | virtual |
zeroReg | gem5::BaseSimpleCPU | protected |
~BaseSimpleCPU() | gem5::BaseSimpleCPU | virtual |
~TimingSimpleCPU() | gem5::TimingSimpleCPU | virtual |