| _cacheLineSize | gem5::BaseCPU | protected |
| _cpuId | gem5::BaseCPU | protected |
| _dataRequestorId | gem5::BaseCPU | protected |
| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _instRequestorId | gem5::BaseCPU | protected |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| _pid | gem5::BaseCPU | protected |
| _socketId | gem5::BaseCPU | protected |
| _status | gem5::BaseSimpleCPU | protected |
| _switchedOut | gem5::BaseCPU | protected |
| _taskId | gem5::BaseCPU | protected |
| activateContext(ThreadID thread_num) override | gem5::TimingSimpleCPU | virtual |
| activeThreads | gem5::BaseSimpleCPU | |
| addressMonitor | gem5::BaseCPU | private |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| advanceInst(const Fault &fault) | gem5::TimingSimpleCPU | |
| advancePC(const Fault &fault) | gem5::BaseSimpleCPU | |
| amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) | gem5::BaseSimpleCPU | inlinevirtual |
| armMonitor(ThreadID tid, Addr address) | gem5::BaseCPU | |
| BaseCPU(const Params ¶ms, bool is_checker=false) | gem5::BaseCPU | |
| BaseSimpleCPU(const BaseSimpleCPUParams ¶ms) | gem5::BaseSimpleCPU | |
| baseStats | gem5::BaseCPU | |
| branchPred | gem5::BaseSimpleCPU | protected |
| buildPacket(const RequestPtr &req, bool read) | gem5::TimingSimpleCPU | private |
| buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read) | gem5::TimingSimpleCPU | private |
| cacheLineSize() const | gem5::BaseCPU | inline |
| checker | gem5::BaseSimpleCPU | |
| checkForInterrupts() | gem5::BaseSimpleCPU | |
| checkInterrupts(ThreadID tid) const | gem5::BaseCPU | inline |
| checkPcEventQueue() | gem5::BaseSimpleCPU | protected |
| clearInterrupt(ThreadID tid, int int_num, int index) | gem5::BaseCPU | inline |
| clearInterrupts(ThreadID tid) | gem5::BaseCPU | inline |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| completeDataAccess(PacketPtr pkt) | gem5::TimingSimpleCPU | |
| completeIfetch(PacketPtr) | gem5::TimingSimpleCPU | |
| contextToThread(ContextID cid) | gem5::BaseCPU | inline |
| countInst() | gem5::BaseSimpleCPU | |
| CPU_STATE_ON enum value | gem5::BaseCPU | protected |
| CPU_STATE_SLEEP enum value | gem5::BaseCPU | protected |
| CPU_STATE_WAKEUP enum value | gem5::BaseCPU | protected |
| cpuId() const | gem5::BaseCPU | inline |
| cpuList | gem5::BaseCPU | privatestatic |
| CPUState enum name | gem5::BaseCPU | protected |
| curCycle() const | gem5::Clocked | inline |
| curMacroStaticInst | gem5::BaseSimpleCPU | |
| currentFunctionEnd | gem5::BaseCPU | private |
| currentFunctionStart | gem5::BaseCPU | private |
| currentSection() | gem5::Serializable | static |
| curStaticInst | gem5::BaseSimpleCPU | |
| curThread | gem5::BaseSimpleCPU | protected |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| dataRequestorId() const | gem5::BaseCPU | inline |
| dcache_pkt | gem5::TimingSimpleCPU | private |
| dcachePort | gem5::TimingSimpleCPU | private |
| DcacheRetry enum value | gem5::BaseSimpleCPU | protected |
| DcacheWaitResponse enum value | gem5::BaseSimpleCPU | protected |
| DcacheWaitSwitch enum value | gem5::BaseSimpleCPU | protected |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| deschedulePowerGatingEvent() | gem5::BaseCPU | |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| drain() override | gem5::TimingSimpleCPU | virtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() override | gem5::TimingSimpleCPU | virtual |
| drainState() const | gem5::Drainable | inline |
| DTBWaitResponse enum value | gem5::BaseSimpleCPU | protected |
| enableFunctionTrace() | gem5::BaseCPU | private |
| enterPwrGating() | gem5::BaseCPU | protected |
| enterPwrGatingEvent | gem5::BaseCPU | protected |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| Faulting enum value | gem5::BaseSimpleCPU | protected |
| fetch() | gem5::TimingSimpleCPU | |
| fetchEvent | gem5::TimingSimpleCPU | private |
| fetchTranslation | gem5::TimingSimpleCPU | private |
| find(const char *name) | gem5::SimObject | static |
| findContext(ThreadContext *tc) | gem5::BaseCPU | |
| finishTranslation(WholeTranslationState *state) | gem5::TimingSimpleCPU | |
| flushTLBs() | gem5::BaseCPU | |
| frequency() const | gem5::Clocked | inline |
| functionEntryTick | gem5::BaseCPU | private |
| functionTraceStream | gem5::BaseCPU | private |
| functionTracingEnabled | gem5::BaseCPU | private |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getContext(int tn) | gem5::BaseCPU | inlinevirtual |
| getCpuAddrMonitor(ThreadID tid) | gem5::BaseCPU | inline |
| getCurrentInstCount(ThreadID tid) | gem5::BaseCPU | |
| getDataPort() override | gem5::TimingSimpleCPU | inlineprotectedvirtual |
| getInstPort() override | gem5::TimingSimpleCPU | inlineprotectedvirtual |
| getInterruptController(ThreadID tid) | gem5::BaseCPU | inline |
| getPid() const | gem5::BaseCPU | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::BaseCPU | virtual |
| getProbeManager() | gem5::SimObject | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| getTracer() | gem5::BaseCPU | inline |
| globalStats | gem5::BaseCPU | protectedstatic |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| haltContext(ThreadID thread_num) override | gem5::BaseSimpleCPU | virtual |
| handleReadPacket(PacketPtr pkt) | gem5::TimingSimpleCPU | private |
| handleWritePacket() | gem5::TimingSimpleCPU | private |
| htmSendAbortSignal(HtmFailureFaultCause) override | gem5::TimingSimpleCPU | virtual |
| icachePort | gem5::TimingSimpleCPU | private |
| IcacheRetry enum value | gem5::BaseSimpleCPU | protected |
| IcacheWaitResponse enum value | gem5::BaseSimpleCPU | protected |
| IcacheWaitSwitch enum value | gem5::BaseSimpleCPU | protected |
| Idle enum value | gem5::BaseSimpleCPU | protected |
| ifetch_pkt | gem5::TimingSimpleCPU | private |
| init() override | gem5::TimingSimpleCPU | virtual |
| initiateHtmCmd(Request::Flags flags) override | gem5::TimingSimpleCPU | virtual |
| initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override | gem5::TimingSimpleCPU | virtual |
| initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override | gem5::TimingSimpleCPU | virtual |
| initState() | gem5::SimObject | virtual |
| instCnt | gem5::BaseCPU | protected |
| instCount() | gem5::BaseCPU | inline |
| instRequestorId() const | gem5::BaseCPU | inline |
| interrupts | gem5::BaseCPU | protected |
| invldPid | gem5::BaseCPU | static |
| isCpuDrained() const | gem5::TimingSimpleCPU | inlineprivate |
| isSquashed() const | gem5::TimingSimpleCPU | inline |
| ITBWaitResponse enum value | gem5::BaseSimpleCPU | protected |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| mwait(ThreadID tid, PacketPtr pkt) | gem5::BaseCPU | |
| mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu) | gem5::BaseCPU | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| notifyFork() | gem5::Drainable | inlinevirtual |
| numContexts() | gem5::BaseCPU | inline |
| numSimulatedCPUs() | gem5::BaseCPU | inlinestatic |
| numSimulatedInsts() | gem5::BaseCPU | inlinestatic |
| numSimulatedOps() | gem5::BaseCPU | inlinestatic |
| numThreads | gem5::BaseCPU | |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| PARAMS(BaseCPU) | gem5::BaseCPU | |
| Params typedef | gem5::ClockedObject | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| pmuProbePoint(const char *name) | gem5::BaseCPU | protected |
| postExecute() | gem5::BaseSimpleCPU | |
| postInterrupt(ThreadID tid, int int_num, int index) | gem5::BaseCPU | |
| powerGatingOnIdle | gem5::BaseCPU | protected |
| powerState | gem5::ClockedObject | |
| ppActiveCycles | gem5::BaseCPU | protected |
| ppAllCycles | gem5::BaseCPU | protected |
| ppRetiredBranches | gem5::BaseCPU | protected |
| ppRetiredInsts | gem5::BaseCPU | protected |
| ppRetiredInstsPC | gem5::BaseCPU | protected |
| ppRetiredLoads | gem5::BaseCPU | protected |
| ppRetiredStores | gem5::BaseCPU | protected |
| ppSleeping | gem5::BaseCPU | protected |
| preDumpStats() | gem5::statistics::Group | virtual |
| preExecute() | gem5::BaseSimpleCPU | |
| previousCycle | gem5::TimingSimpleCPU | private |
| previousState | gem5::BaseCPU | protected |
| printAddr(Addr a) | gem5::TimingSimpleCPU | |
| probeInstCommit(const StaticInstPtr &inst, Addr pc) | gem5::BaseCPU | virtual |
| probeManager | gem5::SimObject | private |
| pwrGatingLatency | gem5::BaseCPU | protected |
| readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) | gem5::BaseSimpleCPU | inlinevirtual |
| registerThreadContexts() | gem5::BaseCPU | |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() override | gem5::BaseCPU | virtual |
| regStats() override | gem5::BaseCPU | virtual |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() override | gem5::BaseSimpleCPU | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| Running enum value | gem5::BaseSimpleCPU | protected |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| scheduleInstStop(ThreadID tid, Counter insts, const char *cause) | gem5::BaseCPU | |
| schedulePowerGatingEvent() | gem5::BaseCPU | |
| sendData(const RequestPtr &req, uint8_t *data, uint64_t *res, bool read) | gem5::TimingSimpleCPU | private |
| sendFetch(const Fault &fault, const RequestPtr &req, ThreadContext *tc) | gem5::TimingSimpleCPU | |
| sendSplitData(const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read) | gem5::TimingSimpleCPU | private |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::BaseCPU | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| serializeThread(CheckpointOut &cp, ThreadID tid) const override | gem5::BaseSimpleCPU | virtual |
| serviceInstCountEvents() | gem5::BaseSimpleCPU | |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setPid(uint32_t pid) | gem5::BaseCPU | inline |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| setupFetchRequest(const RequestPtr &req) | gem5::BaseSimpleCPU | |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| socketId() const | gem5::BaseCPU | inline |
| startup() override | gem5::BaseCPU | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::statistics::Group | private |
| Status enum name | gem5::BaseSimpleCPU | protected |
| suspendContext(ThreadID thread_num) override | gem5::TimingSimpleCPU | virtual |
| swapActiveThread() | gem5::BaseSimpleCPU | protected |
| switchedOut() const | gem5::BaseCPU | inline |
| switchOut() override | gem5::TimingSimpleCPU | virtual |
| syscallRetryLatency | gem5::BaseCPU | |
| system | gem5::BaseCPU | |
| takeOverFrom(BaseCPU *oldCPU) override | gem5::TimingSimpleCPU | virtual |
| taskId() const | gem5::BaseCPU | inline |
| taskId(uint32_t id) | gem5::BaseCPU | inline |
| threadContexts | gem5::BaseCPU | protected |
| threadInfo | gem5::BaseSimpleCPU | |
| threadSnoop(PacketPtr pkt, ThreadID sender) | gem5::TimingSimpleCPU | private |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| TimingSimpleCPU(const TimingSimpleCPUParams ¶ms) | gem5::TimingSimpleCPU | |
| totalInsts() const override | gem5::BaseSimpleCPU | virtual |
| totalOps() const override | gem5::BaseSimpleCPU | virtual |
| traceData | gem5::BaseSimpleCPU | |
| traceFault() | gem5::BaseSimpleCPU | protected |
| traceFunctions(Addr pc) | gem5::BaseCPU | inline |
| traceFunctionsInternal(Addr pc) | gem5::BaseCPU | private |
| tracer | gem5::BaseCPU | protected |
| translationFault(const Fault &fault) | gem5::TimingSimpleCPU | private |
| tryCompleteDrain() | gem5::TimingSimpleCPU | private |
| unserialize(CheckpointIn &cp) override | gem5::BaseCPU | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| unserializeThread(CheckpointIn &cp, ThreadID tid) override | gem5::BaseSimpleCPU | virtual |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| updateCycleCounters(CPUState state) | gem5::BaseCPU | inlineprotected |
| updateCycleCounts() | gem5::TimingSimpleCPU | private |
| verifyMemoryMode() const override | gem5::TimingSimpleCPU | virtual |
| voltage() const | gem5::Clocked | inline |
| wakeup(ThreadID tid) override | gem5::BaseSimpleCPU | virtual |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| workItemBegin() | gem5::BaseCPU | inline |
| workItemEnd() | gem5::BaseCPU | inline |
| writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) override | gem5::TimingSimpleCPU | virtual |
| zeroReg | gem5::BaseSimpleCPU | protected |
| ~BaseCPU() | gem5::BaseCPU | virtual |
| ~BaseSimpleCPU() | gem5::BaseSimpleCPU | virtual |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |
| ~TimingSimpleCPU() | gem5::TimingSimpleCPU | virtual |