gem5  v21.2.1.1
gem5::TimingSimpleCPU Member List

This is the complete list of members for gem5::TimingSimpleCPU, including all inherited members.

_statusgem5::BaseSimpleCPUprotected
activateContext(ThreadID thread_num) overridegem5::TimingSimpleCPU
activeThreadsgem5::BaseSimpleCPU
advanceInst(const Fault &fault)gem5::TimingSimpleCPU
advancePC(const Fault &fault)gem5::BaseSimpleCPU
amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)gem5::BaseSimpleCPUinlinevirtual
BaseSimpleCPU(const BaseSimpleCPUParams &params)gem5::BaseSimpleCPU
branchPredgem5::BaseSimpleCPUprotected
buildPacket(const RequestPtr &req, bool read)gem5::TimingSimpleCPUprivate
buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read)gem5::TimingSimpleCPUprivate
checkergem5::BaseSimpleCPU
checkForInterrupts()gem5::BaseSimpleCPU
checkPcEventQueue()gem5::BaseSimpleCPUprotected
completeDataAccess(PacketPtr pkt)gem5::TimingSimpleCPU
completeIfetch(PacketPtr)gem5::TimingSimpleCPU
countInst()gem5::BaseSimpleCPU
curMacroStaticInstgem5::BaseSimpleCPU
curStaticInstgem5::BaseSimpleCPU
curThreadgem5::BaseSimpleCPUprotected
dcache_pktgem5::TimingSimpleCPUprivate
dcachePortgem5::TimingSimpleCPUprivate
DcacheRetry enum valuegem5::BaseSimpleCPUprotected
DcacheWaitResponse enum valuegem5::BaseSimpleCPUprotected
DcacheWaitSwitch enum valuegem5::BaseSimpleCPUprotected
drain() overridegem5::TimingSimpleCPU
drainResume() overridegem5::TimingSimpleCPU
DTBWaitResponse enum valuegem5::BaseSimpleCPUprotected
Faulting enum valuegem5::BaseSimpleCPUprotected
fetch()gem5::TimingSimpleCPU
fetchEventgem5::TimingSimpleCPUprivate
fetchTranslationgem5::TimingSimpleCPUprivate
finishTranslation(WholeTranslationState *state)gem5::TimingSimpleCPU
getDataPort() overridegem5::TimingSimpleCPUinlineprotected
getInstPort() overridegem5::TimingSimpleCPUinlineprotected
haltContext(ThreadID thread_num) overridegem5::BaseSimpleCPU
handleReadPacket(PacketPtr pkt)gem5::TimingSimpleCPUprivate
handleWritePacket()gem5::TimingSimpleCPUprivate
htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause) overridegem5::TimingSimpleCPU
icachePortgem5::TimingSimpleCPUprivate
IcacheRetry enum valuegem5::BaseSimpleCPUprotected
IcacheWaitResponse enum valuegem5::BaseSimpleCPUprotected
IcacheWaitSwitch enum valuegem5::BaseSimpleCPUprotected
Idle enum valuegem5::BaseSimpleCPUprotected
ifetch_pktgem5::TimingSimpleCPUprivate
init() overridegem5::TimingSimpleCPU
initiateHtmCmd(Request::Flags flags) overridegem5::TimingSimpleCPUvirtual
initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) overridegem5::TimingSimpleCPUvirtual
initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) overridegem5::TimingSimpleCPUvirtual
isCpuDrained() constgem5::TimingSimpleCPUinlineprivate
isSquashed() constgem5::TimingSimpleCPUinline
ITBWaitResponse enum valuegem5::BaseSimpleCPUprotected
postExecute()gem5::BaseSimpleCPU
preExecute()gem5::BaseSimpleCPU
preExecuteTempPCgem5::BaseSimpleCPUprotected
previousCyclegem5::TimingSimpleCPUprivate
printAddr(Addr a)gem5::TimingSimpleCPU
readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())gem5::BaseSimpleCPUinlinevirtual
resetStats() overridegem5::BaseSimpleCPU
Running enum valuegem5::BaseSimpleCPUprotected
sendData(const RequestPtr &req, uint8_t *data, uint64_t *res, bool read)gem5::TimingSimpleCPUprivate
sendFetch(const Fault &fault, const RequestPtr &req, ThreadContext *tc)gem5::TimingSimpleCPU
sendSplitData(const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read)gem5::TimingSimpleCPUprivate
serializeThread(CheckpointOut &cp, ThreadID tid) const overridegem5::BaseSimpleCPU
serviceInstCountEvents()gem5::BaseSimpleCPU
setupFetchRequest(const RequestPtr &req)gem5::BaseSimpleCPU
Status enum namegem5::BaseSimpleCPUprotected
suspendContext(ThreadID thread_num) overridegem5::TimingSimpleCPU
swapActiveThread()gem5::BaseSimpleCPUprotected
switchOut() overridegem5::TimingSimpleCPU
takeOverFrom(BaseCPU *oldCPU) overridegem5::TimingSimpleCPU
threadInfogem5::BaseSimpleCPU
threadSnoop(PacketPtr pkt, ThreadID sender)gem5::TimingSimpleCPUprivate
TimingSimpleCPU(const TimingSimpleCPUParams &params)gem5::TimingSimpleCPU
totalInsts() const overridegem5::BaseSimpleCPU
totalOps() const overridegem5::BaseSimpleCPU
traceDatagem5::BaseSimpleCPU
traceFault()gem5::BaseSimpleCPUprotected
translationFault(const Fault &fault)gem5::TimingSimpleCPUprivate
tryCompleteDrain()gem5::TimingSimpleCPUprivate
unserializeThread(CheckpointIn &cp, ThreadID tid) overridegem5::BaseSimpleCPU
updateCycleCounts()gem5::TimingSimpleCPUprivate
verifyMemoryMode() const overridegem5::TimingSimpleCPU
wakeup(ThreadID tid) overridegem5::BaseSimpleCPU
writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) overridegem5::TimingSimpleCPUvirtual
zeroReggem5::BaseSimpleCPUprotected
~BaseSimpleCPU()gem5::BaseSimpleCPUvirtual
~TimingSimpleCPU()gem5::TimingSimpleCPUvirtual

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