#include <timing.hh>

Inheritance diagram for gem5::TimingSimpleCPU:

Classes
class	DcachePort

class	FetchTranslation

class	IcachePort

struct	IprEvent

class	SplitFragmentSenderState

class	SplitMainSenderState

class	TimingCPUPort
	A TimingCPUPort overrides the default behaviour of the recvTiming and recvRetry and implements events for the scheduling of handling of incoming packets in the following cycle. More...

Public Member Functions
	TimingSimpleCPU (const BaseTimingSimpleCPUParams &params)

virtual	~TimingSimpleCPU ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected.

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.

void	drainResume () override
	Resume execution after a successful drain.

void	switchOut () override
	Prepare for another CPU to take over execution.

void	takeOverFrom (BaseCPU *oldCPU) override
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

void	verifyMemoryMode () const override
	Verify that the system is in a memory mode supported by the CPU.

void	activateContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now active.

void	suspendContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now suspended.

Fault	initiateMemRead (Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override

Fault	writeMem (uint8_t data, unsigned size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable=std::vector< bool >()) override

Fault	initiateMemAMO (Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override

void	fetch ()

void	sendFetch (const Fault &fault, const RequestPtr &req, ThreadContext *tc)

void	completeIfetch (PacketPtr)

void	completeDataAccess (PacketPtr pkt)

void	advanceInst (const Fault &fault)

bool	isSquashed () const
	This function is used by the page table walker to determine if it could translate the a pending request or if the underlying request has been squashed.

void	printAddr (Addr a)
	Print state of address in memory system via PrintReq (for debugging).

void	finishTranslation (WholeTranslationState *state)
	Finish a DTB translation.

Fault	initiateMemMgmtCmd (Request::Flags flags) override
	hardware transactional memory & TLBI operations

void	htmSendAbortSignal (ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause) override
	This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away.

Public Member Functions inherited from gem5::BaseSimpleCPU
	BaseSimpleCPU (const BaseSimpleCPUParams &params)

virtual	~BaseSimpleCPU ()

void	wakeup (ThreadID tid) override

void	checkForInterrupts ()

void	setupFetchRequest (const RequestPtr &req)

void	serviceInstCountEvents ()

void	preExecute ()

void	postExecute ()

void	advancePC (const Fault &fault)

void	haltContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now halted.

void	resetStats () override
	Callback to reset stats.

virtual Fault	readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())

virtual Fault	amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)

void	countInst ()

void	countFetchInst ()

void	countCommitInst ()

Counter	totalInsts () const override

Counter	totalOps () const override

void	serializeThread (CheckpointOut &cp, ThreadID tid) const override
	Serialize a single thread.

void	unserializeThread (CheckpointIn &cp, ThreadID tid) override
	Unserialize one thread.

Public Member Functions inherited from gem5::BaseCPU
int	cpuId () const
	Reads this CPU's ID.

uint32_t	socketId () const
	Reads this CPU's Socket ID.

RequestorID	dataRequestorId () const
	Reads this CPU's unique data requestor ID.

RequestorID	instRequestorId () const
	Reads this CPU's unique instruction requestor ID.

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU.

uint32_t	taskId () const
	Get cpu task id.

void	taskId (uint32_t id)
	Set cpu task id.

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadID tid) const

trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer.

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num.

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it.

unsigned	numContexts ()
	Get the number of thread contexts available.

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID.

	PARAMS (BaseCPU)

	BaseCPU (const Params &params, bool is_checker=false)

virtual	~BaseCPU ()

void	startup () override
	startup() is the final initialization call before simulation.

void	regStats () override
	Callback to set stat parameters.

void	regProbePoints () override
	Register probe points for this object.

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

virtual void	setReset (bool state)
	Set the reset of the CPU to be either asserted or deasserted.

void	flushTLBs ()
	Flush all TLBs in the CPU.

bool	switchedOut () const
	Determine if the CPU is switched out.

Addr	cacheLineSize () const
	Get the cache line size of the system.

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream.

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint.

void	scheduleInstStop (ThreadID tid, Counter insts, std::string cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions.

void	scheduleSimpointsInstStop (std::vector< Counter > inst_starts)
	Schedule simpoint events using the scheduleInstStop function.

void	scheduleInstStopAnyThread (Counter max_insts)
	Schedule an exit event when any threads in the core reach the max_insts instructions using the scheduleInstStop function.

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU.

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseMMU mmu)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction.

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint.

virtual void	regProbeListeners ()
	Register probe listeners for this object.

ProbeManager *	getProbeManager ()
	Get the probe manager for this object.

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue.

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.

virtual void	notifyFork ()
	Notify a child process of a fork.

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group.

virtual	~Group ()

virtual void	preDumpStats ()
	Callback before stats are dumped.

void	addStat (statistics::Info *info)
	Register a stat with this group.

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block.

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick.

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle.

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge.

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future.

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Protected Member Functions
Port &	getDataPort () override
	Return a reference to the data port.

Port &	getInstPort () override
	Return a reference to the instruction port.

Protected Member Functions inherited from gem5::BaseSimpleCPU
void	checkPcEventQueue ()

void	swapActiveThread ()

void	traceFault ()
	Handler used when encountering a fault; its purpose is to tear down the InstRecord.

Protected Member Functions inherited from gem5::BaseCPU
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression

void	enterPwrGating ()

probing::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object.

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

void	signalDrainDone () const
	Signal that an object is drained.

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters.

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance.

void	resetClock () const
	Reset the object's clock using the current global tick value.

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed.

Private Member Functions
void	threadSnoop (PacketPtr pkt, ThreadID sender)

void	sendData (const RequestPtr &req, uint8_t data, uint64_t res, bool read)

void	sendSplitData (const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read)

void	translationFault (const Fault &fault)

PacketPtr	buildPacket (const RequestPtr &req, bool read)

void	buildSplitPacket (PacketPtr &pkt1, PacketPtr &pkt2, const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read)

bool	handleReadPacket (PacketPtr pkt)

bool	handleWritePacket ()

void	updateCycleCounts ()

bool	isCpuDrained () const
	Check if a system is in a drained state.

bool	tryCompleteDrain ()
	Try to complete a drain request.

Private Attributes
FetchTranslation	fetchTranslation

IcachePort	icachePort

DcachePort	dcachePort

PacketPtr	ifetch_pkt

PacketPtr	dcache_pkt

Cycles	previousCycle

EventFunctionWrapper	fetchEvent

Additional Inherited Members
Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject.

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Static Public Member Functions inherited from gem5::BaseCPU
static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Public Attributes inherited from gem5::BaseSimpleCPU
trace::InstRecord *	traceData

CheckerCPU *	checker

std::vector< SimpleExecContext * >	threadInfo

std::list< ThreadID >	activeThreads

StaticInstPtr	curStaticInst
	Current instruction.

StaticInstPtr	curMacroStaticInst

Public Attributes inherited from gem5::BaseCPU
ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS).

System *	system

gem5::BaseCPU::BaseCPUStats	baseStats

Cycles	syscallRetryLatency

std::vector< std::unique_ptr< FetchCPUStats > >	fetchStats

std::vector< std::unique_ptr< ExecuteCPUStats > >	executeStats

std::vector< std::unique_ptr< CommitCPUStats > >	commitStats

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Static Public Attributes inherited from gem5::BaseCPU
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid.

Protected Types inherited from gem5::BaseSimpleCPU
enum	Status { Idle , Running , Faulting , ITBWaitResponse , IcacheRetry , IcacheWaitResponse , IcacheWaitSwitch , DTBWaitResponse , DcacheRetry , DcacheWaitResponse , DcacheWaitSwitch }

Protected Types inherited from gem5::BaseCPU
enum	CPUState { CPU_STATE_ON , CPU_STATE_SLEEP , CPU_STATE_WAKEUP }

Protected Attributes inherited from gem5::BaseSimpleCPU
ThreadID	curThread

branch_prediction::BPredUnit *	branchPred

Status	_status

std::unique_ptr< PCStateBase >	preExecuteTempPC

Protected Attributes inherited from gem5::BaseCPU
Tick	instCnt
	Instruction count used for SPARC misc register.

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system.

RequestorID	_instRequestorId
	instruction side request id that must be placed in all requests

RequestorID	_dataRequestorId
	data side request id that must be placed in all requests

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5.

uint32_t	_pid
	The current OS process ID that is executing on this processor.

bool	_switchedOut
	Is the CPU switched out or active?

const Addr	_cacheLineSize
	Cache the cache line size that we get from the system.

SignalSinkPort< bool >	modelResetPort

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

probing::PMUUPtr	ppRetiredInsts
	Instruction commit probe point.

probing::PMUUPtr	ppRetiredInstsPC

probing::PMUUPtr	ppRetiredLoads
	Retired load instructions.

probing::PMUUPtr	ppRetiredStores
	Retired store instructions.

probing::PMUUPtr	ppRetiredBranches
	Retired branches (any type)

probing::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended.

probing::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active.

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets.

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Static Protected Attributes inherited from gem5::BaseCPU
static std::unique_ptr< GlobalStats >	globalStats
	Pointer to the global stat structure.

Detailed Description

Definition at line 53 of file timing.hh.

Constructor & Destructor Documentation

◆ TimingSimpleCPU()

gem5::TimingSimpleCPU::TimingSimpleCPU ( const BaseTimingSimpleCPUParams & params )

Definition at line 76 of file timing.cc.

References fetch().

◆ ~TimingSimpleCPU()

gem5::TimingSimpleCPU::~TimingSimpleCPU ( )

virtual

Definition at line 86 of file timing.cc.

Member Function Documentation

◆ activateContext()

void gem5::TimingSimpleCPU::activateContext ( ThreadID thread_num )

overridevirtual

Notify the CPU that the indicated context is now active.

Reimplemented from gem5::BaseCPU.

Definition at line 208 of file timing.cc.

References gem5::BaseSimpleCPU::_status, gem5::BaseCPU::activateContext(), gem5::BaseSimpleCPU::activeThreads, gem5::Clocked::clockEdge(), DPRINTF, fetchEvent, gem5::BaseSimpleCPU::Idle, gem5::BaseCPU::numThreads, gem5::BaseSimpleCPU::Running, gem5::EventManager::schedule(), gem5::Event::scheduled(), and gem5::BaseSimpleCPU::threadInfo.

◆ advanceInst()

void gem5::TimingSimpleCPU::advanceInst ( const Fault & fault )

◆ buildPacket()

PacketPtr gem5::TimingSimpleCPU::buildPacket	(	const RequestPtr &	req,
		bool	read )

private

Definition at line 413 of file timing.cc.

References gem5::Packet::createRead(), and gem5::Packet::createWrite().

Referenced by buildSplitPacket(), and sendData().

◆ buildSplitPacket()

void gem5::TimingSimpleCPU::buildSplitPacket	(	PacketPtr &	pkt1,
		PacketPtr &	pkt2,
		const RequestPtr &	req1,
		const RequestPtr &	req2,
		const RequestPtr &	req,
		uint8_t *	data,
		bool	read )

private

Definition at line 419 of file timing.cc.

References buildPacket(), gem5::Packet::cmd, data, gem5::Packet::dataDynamic(), gem5::Packet::dataStatic(), gem5::Request::NO_ACCESS, gem5::MemCmd::responseCommand(), and gem5::Packet::senderState.

Referenced by sendSplitData().

◆ completeDataAccess()

void gem5::TimingSimpleCPU::completeDataAccess ( PacketPtr pkt )

Definition at line 943 of file timing.cc.

Referenced by gem5::TimingSimpleCPU::DcachePort::DTickEvent::process(), sendData(), and sendSplitData().

◆ completeIfetch()

void gem5::TimingSimpleCPU::completeIfetch ( PacketPtr pkt )

Definition at line 819 of file timing.cc.

Referenced by fetch(), and gem5::TimingSimpleCPU::IcachePort::ITickEvent::process().

◆ drain()

DrainState gem5::TimingSimpleCPU::drain ( )

overridevirtual

Provide a default implementation of the drain interface for objects that don't need draining.

Reimplemented from gem5::SimObject.

Definition at line 91 of file timing.cc.

References gem5::BaseSimpleCPU::_status, gem5::BaseSimpleCPU::activeThreads, gem5::Clocked::clockEdge(), gem5::BaseCPU::deschedulePowerGatingEvent(), DPRINTF, gem5::Drained, gem5::Draining, fetchEvent, gem5::BaseSimpleCPU::Idle, isCpuDrained(), gem5::BaseSimpleCPU::Running, gem5::EventManager::schedule(), gem5::Event::scheduled(), and gem5::BaseCPU::switchedOut().

◆ drainResume()

void gem5::TimingSimpleCPU::drainResume ( )

overridevirtual

Resume execution after a successful drain.

Reimplemented from gem5::Drainable.

Definition at line 118 of file timing.cc.

References gem5::BaseSimpleCPU::_status, gem5::ThreadContext::Active, gem5::BaseSimpleCPU::activeThreads, DPRINTF, fetchEvent, gem5::BaseSimpleCPU::Idle, gem5::Clocked::nextCycle(), gem5::BaseCPU::numThreads, gem5::BaseSimpleCPU::Running, gem5::EventManager::schedule(), gem5::Event::scheduled(), gem5::BaseCPU::schedulePowerGatingEvent(), gem5::BaseCPU::switchedOut(), gem5::BaseCPU::threadContexts, gem5::BaseSimpleCPU::threadInfo, and verifyMemoryMode().

◆ fetch()

void gem5::TimingSimpleCPU::fetch ( )

Definition at line 677 of file timing.cc.

Referenced by advanceInst(), and TimingSimpleCPU().

◆ finishTranslation()

void gem5::TimingSimpleCPU::finishTranslation ( WholeTranslationState * state )

Finish a DTB translation.

Parameters

state The DTB translation state.

Definition at line 651 of file timing.cc.

References gem5::BaseSimpleCPU::_status, gem5::NoFault, gem5::BaseMMU::Read, gem5::BaseSimpleCPU::Running, sendData(), sendSplitData(), state, and translationFault().

◆ getDataPort()

Port & gem5::TimingSimpleCPU::getDataPort ( )

inlineoverrideprotectedvirtual

Return a reference to the data port.

Implements gem5::BaseCPU.

Definition at line 269 of file timing.hh.

References dcachePort.

◆ getInstPort()

Port & gem5::TimingSimpleCPU::getInstPort ( )

inlineoverrideprotectedvirtual

Return a reference to the instruction port.

Implements gem5::BaseCPU.

Definition at line 272 of file timing.hh.

References icachePort.

◆ handleReadPacket()

bool gem5::TimingSimpleCPU::handleReadPacket ( PacketPtr pkt )

private

◆ handleWritePacket()

bool gem5::TimingSimpleCPU::handleWritePacket ( )

private

Definition at line 503 of file timing.cc.

References gem5::BaseSimpleCPU::_status, gem5::Clocked::clockEdge(), gem5::BaseSimpleCPU::curThread, dcache_pkt, dcachePort, gem5::BaseSimpleCPU::DcacheRetry, gem5::BaseSimpleCPU::DcacheWaitResponse, gem5::SimpleThread::getTC(), gem5::Packet::req, gem5::RequestPort::sendTimingReq(), gem5::SimpleExecContext::thread, and gem5::BaseSimpleCPU::threadInfo.

Referenced by gem5::TimingSimpleCPU::DcachePort::recvReqRetry(), sendData(), and sendSplitData().

◆ htmSendAbortSignal()

void gem5::TimingSimpleCPU::htmSendAbortSignal	(	ThreadID	tid,
		uint64_t	htm_uid,
		HtmFailureFaultCause	cause )

overridevirtual

This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away.

This is called in the transaction's very last breath in the core. Afterwards, the core throws away its speculative state and resumes execution at the point the transaction started, i.e. reverses time. When instruction execution resumes, the core expects the memory subsystem to be in a stable, i.e. pre-speculative, state as well.

Reimplemented from gem5::BaseCPU.

Definition at line 1285 of file timing.cc.

References gem5::X86ISA::addr, gem5::SimpleThread::contextId(), data, gem5::BaseCPU::dataRequestorId(), flags, gem5::Request::HTM_ABORT, gem5::PCStateBase::instAddr(), gem5::SimpleExecContext::numInst, gem5::MipsISA::pc, gem5::SimpleThread::pcState(), gem5::Request::PHYSICAL, gem5::PowerISA::rc, sendData(), gem5::trace::InstRecord::setMem(), gem5::Request::STRICT_ORDER, gem5::BaseCPU::taskId(), gem5::SimpleExecContext::thread, gem5::BaseSimpleCPU::threadInfo, and gem5::BaseSimpleCPU::traceData.

◆ init()

void gem5::TimingSimpleCPU::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::BaseCPU.

Definition at line 64 of file timing.cc.

References gem5::BaseCPU::init().

◆ initiateMemAMO()

Fault gem5::TimingSimpleCPU::initiateMemAMO	(	Addr	addr,
		unsigned	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op )

overridevirtual

◆ initiateMemMgmtCmd()

Fault gem5::TimingSimpleCPU::initiateMemMgmtCmd ( Request::Flags flags )

overridevirtual

hardware transactional memory & TLBI operations

Implements gem5::BaseSimpleCPU.

Definition at line 1235 of file timing.cc.

References gem5::X86ISA::addr, gem5::SimpleThread::contextId(), gem5::BaseSimpleCPU::curThread, data, gem5::BaseCPU::dataRequestorId(), DPRINTF, flags, gem5::SimpleExecContext::getHtmTransactionUid(), gem5::PCStateBase::instAddr(), gem5::NoFault, gem5::SimpleExecContext::numInst, panic, gem5::MipsISA::pc, gem5::SimpleThread::pcState(), gem5::PowerISA::rc, sendData(), gem5::trace::InstRecord::setMem(), gem5::BaseCPU::taskId(), gem5::SimpleExecContext::thread, gem5::BaseSimpleCPU::threadInfo, and gem5::BaseSimpleCPU::traceData.

◆ initiateMemRead()

Fault gem5::TimingSimpleCPU::initiateMemRead	(	Addr	addr,
		unsigned	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = std::vector<bool>() )

overridevirtual

◆ isCpuDrained()

bool gem5::TimingSimpleCPU::isCpuDrained ( ) const

inlineprivate

Check if a system is in a drained state.

We need to drain if:

We are in the middle of a microcode sequence as some CPUs (e.g., HW accelerated CPUs) can't be started in the middle of a gem5 microcode sequence.
Stay at PC is true.
A fetch event is scheduled. Normally this would never be the case with microPC() == 0, but right after a context is activated it can happen.

Definition at line 362 of file timing.hh.

References gem5::BaseSimpleCPU::curThread, fetchEvent, gem5::PCStateBase::microPC(), gem5::SimpleThread::pcState(), gem5::Event::scheduled(), gem5::SimpleExecContext::stayAtPC, gem5::SimpleExecContext::thread, and gem5::BaseSimpleCPU::threadInfo.

Referenced by drain(), and tryCompleteDrain().

◆ isSquashed()

bool gem5::TimingSimpleCPU::isSquashed ( ) const

inline

This function is used by the page table walker to determine if it could translate the a pending request or if the underlying request has been squashed.

This always returns false for the simple timing CPU as it never executes any instructions speculatively. @ return Is the current instruction squashed?

Definition at line 313 of file timing.hh.

◆ printAddr()

void gem5::TimingSimpleCPU::printAddr ( Addr a )

Print state of address in memory system via PrintReq (for debugging).

Definition at line 1229 of file timing.cc.

References gem5::ArmISA::a, dcachePort, and gem5::RequestPort::printAddr().

◆ sendData()

void gem5::TimingSimpleCPU::sendData	(	const RequestPtr &	req,
		uint8_t *	data,
		uint64_t *	res,
		bool	read )

private

◆ sendFetch()

void gem5::TimingSimpleCPU::sendFetch	(	const Fault &	fault,
		const RequestPtr &	req,
		ThreadContext *	tc )

◆ sendSplitData()

void gem5::TimingSimpleCPU::sendSplitData	(	const RequestPtr &	req1,
		const RequestPtr &	req2,
		const RequestPtr &	req,
		uint8_t *	data,
		bool	read )

private

Definition at line 346 of file timing.cc.

References buildSplitPacket(), gem5::TimingSimpleCPU::SplitFragmentSenderState::clearFromParent(), completeDataAccess(), gem5::BaseSimpleCPU::curThread, data, dcache_pkt, gem5::SimpleExecContext::getHtmTransactionUid(), handleReadPacket(), handleWritePacket(), gem5::SimpleExecContext::inHtmTransactionalState(), gem5::Packet::makeResponse(), gem5::Request::NO_ACCESS, gem5::Packet::senderState, gem5::Packet::setHtmTransactional(), and gem5::BaseSimpleCPU::threadInfo.

Referenced by finishTranslation().

◆ suspendContext()

void gem5::TimingSimpleCPU::suspendContext ( ThreadID thread_num )

overridevirtual

Notify the CPU that the indicated context is now suspended.

Check if possible to enter a lower power state

Reimplemented from gem5::BaseCPU.

Definition at line 232 of file timing.cc.

References gem5::BaseSimpleCPU::_status, gem5::BaseSimpleCPU::activeThreads, gem5::BaseSimpleCPU::curThread, gem5::EventManager::deschedule(), DPRINTF, fetchEvent, gem5::BaseSimpleCPU::Idle, gem5::BaseCPU::numThreads, gem5::BaseSimpleCPU::Running, gem5::Event::scheduled(), gem5::BaseCPU::suspendContext(), and gem5::BaseSimpleCPU::threadInfo.

◆ switchOut()

void gem5::TimingSimpleCPU::switchOut ( )

overridevirtual

Prepare for another CPU to take over execution.

When this method exits, all internal state should have been flushed. After the method returns, the simulator calls takeOverFrom() on the new CPU with this CPU as its parameter.

Reimplemented from gem5::BaseCPU.

Definition at line 169 of file timing.cc.

References gem5::BaseSimpleCPU::_status, gem5::BaseCPU::CPU_STATE_ON, gem5::BaseSimpleCPU::curThread, fetchEvent, gem5::BaseSimpleCPU::Idle, gem5::SimpleExecContext::inHtmTransactionalState(), gem5::PCStateBase::microPC(), gem5::SimpleThread::pcState(), gem5::BaseSimpleCPU::Running, gem5::Event::scheduled(), gem5::SimpleExecContext::stayAtPC, gem5::BaseCPU::switchOut(), gem5::SimpleExecContext::thread, gem5::BaseSimpleCPU::threadInfo, gem5::BaseCPU::updateCycleCounters(), and updateCycleCounts().

◆ takeOverFrom()

void gem5::TimingSimpleCPU::takeOverFrom ( BaseCPU * cpu )

overridevirtual

Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

A CPU model implementing this method is expected to initialize its state from the old CPU and connect its memory (unless they are already connected) to the memories connected to the old CPU.

Parameters

cpu	CPU to initialize read state from.

Reimplemented from gem5::BaseCPU.

Definition at line 191 of file timing.cc.

References gem5::Clocked::curCycle(), previousCycle, and gem5::BaseCPU::takeOverFrom().

◆ threadSnoop()

void gem5::TimingSimpleCPU::threadSnoop	(	PacketPtr	pkt,
		ThreadID	sender )

private

Definition at line 637 of file timing.cc.

References gem5::TimingSimpleCPU::DcachePort::cacheBlockMask, dcachePort, gem5::BaseCPU::getCpuAddrMonitor(), gem5::BaseCPU::numThreads, gem5::BaseSimpleCPU::threadInfo, and gem5::BaseSimpleCPU::wakeup().

Referenced by sendData().

◆ translationFault()

void gem5::TimingSimpleCPU::translationFault ( const Fault & fault )

private

Definition at line 396 of file timing.cc.

References advanceInst(), gem5::BaseCPU::CPU_STATE_ON, gem5::NoFault, gem5::BaseSimpleCPU::postExecute(), gem5::BaseSimpleCPU::traceData, gem5::BaseSimpleCPU::traceFault(), gem5::BaseCPU::updateCycleCounters(), and updateCycleCounts().

Referenced by finishTranslation().

◆ tryCompleteDrain()

bool gem5::TimingSimpleCPU::tryCompleteDrain ( )

private

Try to complete a drain request.

Returns: true if the CPU is drained, false otherwise.

Definition at line 153 of file timing.cc.

References DPRINTF, gem5::Draining, gem5::Drainable::drainState(), isCpuDrained(), and gem5::Drainable::signalDrainDone().

Referenced by advanceInst().

◆ updateCycleCounts()

void gem5::TimingSimpleCPU::updateCycleCounts ( )

private

Definition at line 1080 of file timing.cc.

References gem5::BaseCPU::baseStats, gem5::Clocked::curCycle(), gem5::BaseCPU::BaseCPUStats::numCycles, and previousCycle.

Referenced by completeDataAccess(), completeIfetch(), fetch(), sendFetch(), switchOut(), and translationFault().

◆ verifyMemoryMode()

void gem5::TimingSimpleCPU::verifyMemoryMode ( ) const

overridevirtual

Verify that the system is in a memory mode supported by the CPU.

Implementations are expected to query the system for the current memory mode and ensure that it is what the CPU model expects. If the check fails, the implementation should terminate the simulation using fatal().

Reimplemented from gem5::BaseCPU.

Definition at line 199 of file timing.cc.

References fatal, and gem5::X86ISA::system.

Referenced by drainResume().

◆ writeMem()

Fault gem5::TimingSimpleCPU::writeMem	(	uint8_t *	data,
		unsigned	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable = std::vector<bool>() )

overridevirtual

Member Data Documentation

◆ dcache_pkt

PacketPtr gem5::TimingSimpleCPU::dcache_pkt

private

Definition at line 262 of file timing.hh.

Referenced by handleReadPacket(), handleWritePacket(), gem5::TimingSimpleCPU::DcachePort::recvReqRetry(), sendData(), and sendSplitData().

◆ dcachePort

DcachePort gem5::TimingSimpleCPU::dcachePort

private

Definition at line 259 of file timing.hh.

Referenced by getDataPort(), handleReadPacket(), handleWritePacket(), printAddr(), sendData(), and threadSnoop().

◆ fetchEvent

EventFunctionWrapper gem5::TimingSimpleCPU::fetchEvent

private

Definition at line 335 of file timing.hh.

Referenced by activateContext(), advanceInst(), drain(), drainResume(), isCpuDrained(), suspendContext(), and switchOut().

◆ fetchTranslation

FetchTranslation gem5::TimingSimpleCPU::fetchTranslation

private

Definition at line 135 of file timing.hh.

Referenced by fetch().

◆ icachePort

IcachePort gem5::TimingSimpleCPU::icachePort

private

Definition at line 258 of file timing.hh.

Referenced by getInstPort(), and sendFetch().

◆ ifetch_pkt

PacketPtr gem5::TimingSimpleCPU::ifetch_pkt

private

Definition at line 261 of file timing.hh.

Referenced by gem5::TimingSimpleCPU::IcachePort::recvReqRetry(), and sendFetch().

◆ previousCycle

Cycles gem5::TimingSimpleCPU::previousCycle

private

Definition at line 264 of file timing.hh.

Referenced by takeOverFrom(), and updateCycleCounts().

The documentation for this class was generated from the following files:

cpu/simple/timing.hh
cpu/simple/timing.cc

Classes

Public Member Functions

Protected Member Functions

Private Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ TimingSimpleCPU()

◆ ~TimingSimpleCPU()

Member Function Documentation

◆ activateContext()

◆ advanceInst()

◆ buildPacket()

◆ buildSplitPacket()

◆ completeDataAccess()

◆ completeIfetch()

◆ drain()

◆ drainResume()

◆ fetch()

◆ finishTranslation()

◆ getDataPort()

◆ getInstPort()

◆ handleReadPacket()

◆ handleWritePacket()

◆ htmSendAbortSignal()

◆ init()

◆ initiateMemAMO()

◆ initiateMemMgmtCmd()

◆ initiateMemRead()

◆ isCpuDrained()

◆ isSquashed()

◆ printAddr()

◆ sendData()

◆ sendFetch()

◆ sendSplitData()

◆ suspendContext()

◆ switchOut()

◆ takeOverFrom()

◆ threadSnoop()

◆ translationFault()

◆ tryCompleteDrain()

◆ updateCycleCounts()

◆ verifyMemoryMode()

◆ writeMem()

Member Data Documentation

◆ dcache_pkt

◆ dcachePort

◆ fetchEvent

◆ fetchTranslation

◆ icachePort

◆ ifetch_pkt

◆ previousCycle