gem5  v22.0.0.1
Classes | Public Member Functions | Protected Member Functions | Private Member Functions | Private Attributes | List of all members
gem5::TimingSimpleCPU Class Reference

#include <timing.hh>

Inheritance diagram for gem5::TimingSimpleCPU:
gem5::BaseSimpleCPU

Classes

class  DcachePort
 
class  FetchTranslation
 
class  IcachePort
 
struct  IprEvent
 
class  SplitFragmentSenderState
 
class  SplitMainSenderState
 
class  TimingCPUPort
 A TimingCPUPort overrides the default behaviour of the recvTiming and recvRetry and implements events for the scheduling of handling of incoming packets in the following cycle. More...
 

Public Member Functions

 TimingSimpleCPU (const BaseTimingSimpleCPUParams &params)
 
virtual ~TimingSimpleCPU ()
 
void init () override
 
DrainState drain () override
 
void drainResume () override
 
void switchOut () override
 
void takeOverFrom (BaseCPU *oldCPU) override
 
void verifyMemoryMode () const override
 
void activateContext (ThreadID thread_num) override
 
void suspendContext (ThreadID thread_num) override
 
Fault initiateMemRead (Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override
 
Fault writeMem (uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) override
 
Fault initiateMemAMO (Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 
void fetch ()
 
void sendFetch (const Fault &fault, const RequestPtr &req, ThreadContext *tc)
 
void completeIfetch (PacketPtr)
 
void completeDataAccess (PacketPtr pkt)
 
void advanceInst (const Fault &fault)
 
bool isSquashed () const
 This function is used by the page table walker to determine if it could translate the a pending request or if the underlying request has been squashed. More...
 
void printAddr (Addr a)
 Print state of address in memory system via PrintReq (for debugging). More...
 
void finishTranslation (WholeTranslationState *state)
 Finish a DTB translation. More...
 
Fault initiateMemMgmtCmd (Request::Flags flags) override
 hardware transactional memory & TLBI operations More...
 
void htmSendAbortSignal (ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause) override
 
- Public Member Functions inherited from gem5::BaseSimpleCPU
 BaseSimpleCPU (const BaseSimpleCPUParams &params)
 
virtual ~BaseSimpleCPU ()
 
void wakeup (ThreadID tid) override
 
void checkForInterrupts ()
 
void setupFetchRequest (const RequestPtr &req)
 
void serviceInstCountEvents ()
 
void preExecute ()
 
void postExecute ()
 
void advancePC (const Fault &fault)
 
void haltContext (ThreadID thread_num) override
 
void resetStats () override
 
virtual Fault readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
 
virtual Fault amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
 
void countInst ()
 
Counter totalInsts () const override
 
Counter totalOps () const override
 
void serializeThread (CheckpointOut &cp, ThreadID tid) const override
 
void unserializeThread (CheckpointIn &cp, ThreadID tid) override
 

Protected Member Functions

PortgetDataPort () override
 Return a reference to the data port. More...
 
PortgetInstPort () override
 Return a reference to the instruction port. More...
 
- Protected Member Functions inherited from gem5::BaseSimpleCPU
void checkPcEventQueue ()
 
void swapActiveThread ()
 
void traceFault ()
 Handler used when encountering a fault; its purpose is to tear down the InstRecord. More...
 

Private Member Functions

void threadSnoop (PacketPtr pkt, ThreadID sender)
 
void sendData (const RequestPtr &req, uint8_t *data, uint64_t *res, bool read)
 
void sendSplitData (const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read)
 
void translationFault (const Fault &fault)
 
PacketPtr buildPacket (const RequestPtr &req, bool read)
 
void buildSplitPacket (PacketPtr &pkt1, PacketPtr &pkt2, const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read)
 
bool handleReadPacket (PacketPtr pkt)
 
bool handleWritePacket ()
 
void updateCycleCounts ()
 
bool isCpuDrained () const
 Check if a system is in a drained state. More...
 
bool tryCompleteDrain ()
 Try to complete a drain request. More...
 

Private Attributes

FetchTranslation fetchTranslation
 
IcachePort icachePort
 
DcachePort dcachePort
 
PacketPtr ifetch_pkt
 
PacketPtr dcache_pkt
 
Cycles previousCycle
 
EventFunctionWrapper fetchEvent
 

Additional Inherited Members

- Public Attributes inherited from gem5::BaseSimpleCPU
Trace::InstRecordtraceData
 
CheckerCPUchecker
 
std::vector< SimpleExecContext * > threadInfo
 
std::list< ThreadIDactiveThreads
 
StaticInstPtr curStaticInst
 Current instruction. More...
 
StaticInstPtr curMacroStaticInst
 
- Protected Types inherited from gem5::BaseSimpleCPU
enum  Status {
  Idle, Running, Faulting, ITBWaitResponse,
  IcacheRetry, IcacheWaitResponse, IcacheWaitSwitch, DTBWaitResponse,
  DcacheRetry, DcacheWaitResponse, DcacheWaitSwitch
}
 
- Protected Attributes inherited from gem5::BaseSimpleCPU
ThreadID curThread
 
branch_prediction::BPredUnitbranchPred
 
Status _status
 
std::unique_ptr< PCStateBasepreExecuteTempPC
 

Detailed Description

Definition at line 53 of file timing.hh.

Constructor & Destructor Documentation

◆ TimingSimpleCPU()

gem5::TimingSimpleCPU::TimingSimpleCPU ( const BaseTimingSimpleCPUParams &  params)

Definition at line 77 of file timing.cc.

References fetch().

◆ ~TimingSimpleCPU()

gem5::TimingSimpleCPU::~TimingSimpleCPU ( )
virtual

Definition at line 87 of file timing.cc.

Member Function Documentation

◆ activateContext()

void gem5::TimingSimpleCPU::activateContext ( ThreadID  thread_num)
override

◆ advanceInst()

void gem5::TimingSimpleCPU::advanceInst ( const Fault fault)

◆ buildPacket()

PacketPtr gem5::TimingSimpleCPU::buildPacket ( const RequestPtr req,
bool  read 
)
private

Definition at line 414 of file timing.cc.

References gem5::Packet::createRead(), and gem5::Packet::createWrite().

Referenced by buildSplitPacket(), and sendData().

◆ buildSplitPacket()

void gem5::TimingSimpleCPU::buildSplitPacket ( PacketPtr pkt1,
PacketPtr pkt2,
const RequestPtr req1,
const RequestPtr req2,
const RequestPtr req,
uint8_t *  data,
bool  read 
)
private

◆ completeDataAccess()

void gem5::TimingSimpleCPU::completeDataAccess ( PacketPtr  pkt)

Definition at line 944 of file timing.cc.

References gem5::BaseSimpleCPU::_status, advanceInst(), gem5::TimingSimpleCPU::SplitFragmentSenderState::bigPkt, gem5::StaticInst::completeAcc(), gem5::BaseSimpleCPU::countInst(), gem5::BaseSimpleCPU::curStaticInst, gem5::BaseSimpleCPU::curThread, gem5::BaseSimpleCPU::DcacheWaitResponse, DPRINTF, gem5::BaseSimpleCPU::DTBWaitResponse, gem5::FAIL_REMOTE, gem5::FAIL_SELF, gem5::Packet::getAddrRange(), gem5::Packet::getHtmTransactionFailedInCacheRC(), gem5::SimpleExecContext::getHtmTransactionUid(), gem5::Packet::getHtmTransactionUid(), gem5::htmFailureToStr(), gem5::Packet::htmTransactionFailedInCache(), gem5::SimpleThread::htmTransactionStops, gem5::SimpleExecContext::inHtmTransactionalState(), gem5::Packet::isError(), gem5::StaticInst::isHtmStop(), gem5::Packet::isHtmTransactional(), gem5::Packet::isWrite(), gem5::MEMORY, gem5::Request::NO_ACCESS, gem5::NoFault, gem5::TimingSimpleCPU::SplitMainSenderState::outstanding, panic, panic_if, gem5::BaseSimpleCPU::postExecute(), gem5::Packet::print(), gem5::Packet::req, gem5::BaseSimpleCPU::Running, gem5::Packet::senderState, gem5::Packet::setHtmTransactional(), gem5::Packet::setHtmTransactionFailedInCache(), gem5::SIZE, gem5::SimpleExecContext::thread, gem5::BaseSimpleCPU::threadInfo, gem5::AddrRange::to_string(), gem5::BaseSimpleCPU::traceData, gem5::BaseSimpleCPU::traceFault(), and updateCycleCounts().

Referenced by gem5::TimingSimpleCPU::DcachePort::DTickEvent::process(), sendData(), and sendSplitData().

◆ completeIfetch()

void gem5::TimingSimpleCPU::completeIfetch ( PacketPtr  pkt)

◆ drain()

DrainState gem5::TimingSimpleCPU::drain ( )
override

◆ drainResume()

void gem5::TimingSimpleCPU::drainResume ( )
override

◆ fetch()

void gem5::TimingSimpleCPU::fetch ( )

◆ finishTranslation()

void gem5::TimingSimpleCPU::finishTranslation ( WholeTranslationState state)

Finish a DTB translation.

Parameters
stateThe DTB translation state.

Definition at line 652 of file timing.cc.

References gem5::BaseSimpleCPU::_status, gem5::NoFault, gem5::BaseMMU::Read, gem5::BaseSimpleCPU::Running, sendData(), sendSplitData(), state, and translationFault().

◆ getDataPort()

Port& gem5::TimingSimpleCPU::getDataPort ( )
inlineoverrideprotected

Return a reference to the data port.

Definition at line 269 of file timing.hh.

References dcachePort.

◆ getInstPort()

Port& gem5::TimingSimpleCPU::getInstPort ( )
inlineoverrideprotected

Return a reference to the instruction port.

Definition at line 272 of file timing.hh.

References icachePort.

◆ handleReadPacket()

bool gem5::TimingSimpleCPU::handleReadPacket ( PacketPtr  pkt)
private

◆ handleWritePacket()

bool gem5::TimingSimpleCPU::handleWritePacket ( )
private

◆ htmSendAbortSignal()

void gem5::TimingSimpleCPU::htmSendAbortSignal ( ThreadID  tid,
uint64_t  htm_uid,
HtmFailureFaultCause  cause 
)
override

◆ init()

void gem5::TimingSimpleCPU::init ( )
override

Definition at line 65 of file timing.cc.

References gem5::statistics::init.

◆ initiateMemAMO()

Fault gem5::TimingSimpleCPU::initiateMemAMO ( Addr  addr,
unsigned  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
overridevirtual

◆ initiateMemMgmtCmd()

Fault gem5::TimingSimpleCPU::initiateMemMgmtCmd ( Request::Flags  flags)
overridevirtual

◆ initiateMemRead()

Fault gem5::TimingSimpleCPU::initiateMemRead ( Addr  addr,
unsigned  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable = std::vector<bool>() 
)
overridevirtual

◆ isCpuDrained()

bool gem5::TimingSimpleCPU::isCpuDrained ( ) const
inlineprivate

Check if a system is in a drained state.

We need to drain if:

  • We are in the middle of a microcode sequence as some CPUs (e.g., HW accelerated CPUs) can't be started in the middle of a gem5 microcode sequence.

  • Stay at PC is true.

  • A fetch event is scheduled. Normally this would never be the case with microPC() == 0, but right after a context is activated it can happen.

Definition at line 362 of file timing.hh.

References gem5::BaseSimpleCPU::curThread, fetchEvent, gem5::PCStateBase::microPC(), gem5::SimpleThread::pcState(), gem5::Event::scheduled(), gem5::SimpleExecContext::stayAtPC, gem5::SimpleExecContext::thread, and gem5::BaseSimpleCPU::threadInfo.

Referenced by drain(), and tryCompleteDrain().

◆ isSquashed()

bool gem5::TimingSimpleCPU::isSquashed ( ) const
inline

This function is used by the page table walker to determine if it could translate the a pending request or if the underlying request has been squashed.

This always returns false for the simple timing CPU as it never executes any instructions speculatively. @ return Is the current instruction squashed?

Definition at line 313 of file timing.hh.

◆ printAddr()

void gem5::TimingSimpleCPU::printAddr ( Addr  a)

Print state of address in memory system via PrintReq (for debugging).

Definition at line 1230 of file timing.cc.

References gem5::ArmISA::a, dcachePort, and gem5::RequestPort::printAddr().

◆ sendData()

void gem5::TimingSimpleCPU::sendData ( const RequestPtr req,
uint8_t *  data,
uint64_t *  res,
bool  read 
)
private

◆ sendFetch()

void gem5::TimingSimpleCPU::sendFetch ( const Fault fault,
const RequestPtr req,
ThreadContext tc 
)

◆ sendSplitData()

void gem5::TimingSimpleCPU::sendSplitData ( const RequestPtr req1,
const RequestPtr req2,
const RequestPtr req,
uint8_t *  data,
bool  read 
)
private

◆ suspendContext()

void gem5::TimingSimpleCPU::suspendContext ( ThreadID  thread_num)
override

◆ switchOut()

void gem5::TimingSimpleCPU::switchOut ( )
override

◆ takeOverFrom()

void gem5::TimingSimpleCPU::takeOverFrom ( BaseCPU *  oldCPU)
override

Definition at line 192 of file timing.cc.

References previousCycle, and gem5::takeOverFrom().

◆ threadSnoop()

void gem5::TimingSimpleCPU::threadSnoop ( PacketPtr  pkt,
ThreadID  sender 
)
private

◆ translationFault()

void gem5::TimingSimpleCPU::translationFault ( const Fault fault)
private

◆ tryCompleteDrain()

bool gem5::TimingSimpleCPU::tryCompleteDrain ( )
private

Try to complete a drain request.

Returns
true if the CPU is drained, false otherwise.

Definition at line 154 of file timing.cc.

References DPRINTF, gem5::Draining, and isCpuDrained().

Referenced by advanceInst().

◆ updateCycleCounts()

void gem5::TimingSimpleCPU::updateCycleCounts ( )
private

Definition at line 1081 of file timing.cc.

References previousCycle.

Referenced by completeDataAccess(), completeIfetch(), fetch(), sendFetch(), switchOut(), and translationFault().

◆ verifyMemoryMode()

void gem5::TimingSimpleCPU::verifyMemoryMode ( ) const
override

Definition at line 200 of file timing.cc.

References fatal, and gem5::X86ISA::system.

Referenced by drainResume().

◆ writeMem()

Fault gem5::TimingSimpleCPU::writeMem ( uint8_t *  data,
unsigned  size,
Addr  addr,
Request::Flags  flags,
uint64_t *  res,
const std::vector< bool > &  byte_enable = std::vector<bool>() 
)
overridevirtual

Member Data Documentation

◆ dcache_pkt

PacketPtr gem5::TimingSimpleCPU::dcache_pkt
private

◆ dcachePort

DcachePort gem5::TimingSimpleCPU::dcachePort
private

◆ fetchEvent

EventFunctionWrapper gem5::TimingSimpleCPU::fetchEvent
private

◆ fetchTranslation

FetchTranslation gem5::TimingSimpleCPU::fetchTranslation
private

Definition at line 135 of file timing.hh.

Referenced by fetch().

◆ icachePort

IcachePort gem5::TimingSimpleCPU::icachePort
private

Definition at line 258 of file timing.hh.

Referenced by getInstPort(), and sendFetch().

◆ ifetch_pkt

PacketPtr gem5::TimingSimpleCPU::ifetch_pkt
private

Definition at line 261 of file timing.hh.

Referenced by gem5::TimingSimpleCPU::IcachePort::recvReqRetry(), and sendFetch().

◆ previousCycle

Cycles gem5::TimingSimpleCPU::previousCycle
private

Definition at line 264 of file timing.hh.

Referenced by takeOverFrom(), and updateCycleCounts().


The documentation for this class was generated from the following files:

Generated on Sat Jun 18 2022 08:13:27 for gem5 by doxygen 1.8.17