gem5  v21.1.0.2
tarmac_record.cc
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37 
39 
40 #include <memory>
41 
43 #include "tarmac_tracer.hh"
44 
45 namespace gem5
46 {
47 
48 using namespace ArmISA;
49 
50 namespace Trace {
51 
52 // TARMAC Instruction Record static variables
53 uint64_t TarmacTracerRecord::TraceInstEntry::instCount = 0;
54 
55 std::string
57 {
58  switch (isetstate) {
59  case TarmacBaseRecord::ISET_ARM:
60  return "A";
61  case TarmacBaseRecord::ISET_THUMB:
62  return "T";
63  case TarmacBaseRecord::ISET_A64:
64  return "O";
65  default:
66  return "Unsupported";
67  }
68 }
69 
70 std::string
72 {
73  switch (opMode) {
74  case MODE_EL0T:
75  return "EL0t";
76  case MODE_EL1T:
77  return "EL1t";
78  case MODE_EL1H:
79  return "EL1h";
80  case MODE_EL2T:
81  return "EL2t";
82  case MODE_EL2H:
83  return "EL2h";
84  case MODE_EL3T:
85  return "EL3t";
86  case MODE_EL3H:
87  return "EL3h";
88  case MODE_USER:
89  return "usr";
90  case MODE_FIQ:
91  return "fiq";
92  case MODE_IRQ:
93  return "irq";
94  case MODE_SVC:
95  return "svc";
96  case MODE_MON:
97  return "mon";
98  case MODE_ABORT:
99  return "abt";
100  case MODE_HYP:
101  return "hyp";
102  case MODE_UNDEFINED:
103  return "und";
104  case MODE_SYSTEM:
105  return "sys";
106  default:
107  return "Unsupported";
108  }
109 }
110 
111 // TarmacTracerRecord ctor
112 TarmacTracerRecord::TarmacTracerRecord(Tick _when, ThreadContext *_thread,
113  const StaticInstPtr _staticInst,
114  PCState _pc,
115  TarmacTracer& _tracer,
116  const StaticInstPtr _macroStaticInst)
117  : TarmacBaseRecord(_when, _thread, _staticInst,
118  _pc, _macroStaticInst),
119  tracer(_tracer)
120 {
121 }
122 
124  const TarmacContext& tarmCtx,
125  bool predicate)
126  : InstEntry(tarmCtx.thread, tarmCtx.pc, tarmCtx.staticInst, predicate)
127 {
128  secureMode = isSecure(tarmCtx.thread);
129 
130  auto arm_inst = static_cast<const ArmStaticInst*>(
131  tarmCtx.staticInst.get()
132  );
133 
134  // Get the instruction size as a number of bits:
135  // (multiply byte size by 8)
136  instSize = (arm_inst->instSize() << 3);
137 
138  // Mask the opcode using the instruction size: the
139  // opcode field will otherwise be 32 bit wide even
140  // for 16bit (Thumb) instruction.
141  opcode = arm_inst->encoding();
142 
143  // Update the instruction count: number of executed
144  // instructions.
145  instCount++;
146 }
147 
149  const TarmacContext& tarmCtx,
150  uint8_t _size, Addr _addr, uint64_t _data)
151  : MemEntry(_size, _addr, _data),
152  loadAccess(tarmCtx.staticInst->isLoad())
153 {
154 }
155 
157  const TarmacContext& tarmCtx,
158  const RegId& reg)
159  : RegEntry(tarmCtx.pc),
160  regValid(false),
161  regClass(reg.classValue()),
162  regRel(reg.index())
163 {
164 }
165 
166 void
168  const TarmacContext& tarmCtx
169 )
170 {
171  // Fill the register entry data, according to register
172  // class.
173  switch (regClass) {
174  case CCRegClass:
175  updateCC(tarmCtx, regRel);
176  break;
177  case FloatRegClass:
178  updateFloat(tarmCtx, regRel);
179  break;
180  case IntRegClass:
181  updateInt(tarmCtx, regRel);
182  break;
183  case MiscRegClass:
184  updateMisc(tarmCtx, regRel);
185  break;
186  case VecRegClass:
187  updateVec(tarmCtx, regRel);
188  break;
189  case VecPredRegClass:
190  updatePred(tarmCtx, regRel);
191  break;
192  default:
193  // If unsupported format, do nothing: non updating
194  // the register will prevent it to be printed.
195  break;
196  }
197 }
198 
199 void
201  const TarmacContext& tarmCtx,
202  RegIndex regRelIdx
203 )
204 {
205  auto thread = tarmCtx.thread;
206 
207  regValid = true;
208  regName = miscRegName[regRelIdx];
209  values[Lo] = thread->readMiscRegNoEffect(regRelIdx);
210 
211  // If it is the CPSR:
212  // update the value of the CPSR register and add
213  // the CC flags on top of the value
214  if (regRelIdx == MISCREG_CPSR) {
216  cpsr.nz = thread->readCCReg(CCREG_NZ);
217  cpsr.c = thread->readCCReg(CCREG_C);
218  cpsr.v = thread->readCCReg(CCREG_V);
219  cpsr.ge = thread->readCCReg(CCREG_GE);
220 
221  // update the entry value
222  values[Lo] = cpsr;
223  }
224 }
225 
226 void
228  const TarmacContext& tarmCtx,
229  RegIndex regRelIdx
230 )
231 {
232  auto thread = tarmCtx.thread;
233 
234  regValid = true;
235  regName = ccRegName[regRelIdx];
236  values[Lo] = thread->readCCReg(regRelIdx);
237 }
238 
239 void
241  const TarmacContext& tarmCtx,
242  RegIndex regRelIdx
243 )
244 {
245  auto thread = tarmCtx.thread;
246 
247  regValid = true;
248  regName = "f" + std::to_string(regRelIdx);
249  values[Lo] = bitsToFloat32(thread->readFloatReg(regRelIdx));
250 }
251 
252 void
254  const TarmacContext& tarmCtx,
255  RegIndex regRelIdx
256 )
257 {
258  auto thread = tarmCtx.thread;
259 
260  // Reading operating mode from CPSR.
261  // This is needed when printing the register name in case
262  // of banked register (e.g. lr_svc)
264  OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode;
265 
266  std::string reg_suffix;
267  if (mode != MODE_USER) {
268  reg_suffix = "_" + opModeToStr(mode);
269  }
270 
271  regValid = true;
272  switch (regRelIdx) {
273  case PCReg:
274  regName = "pc";
275  break;
276  case StackPointerReg:
277  regName = "sp" + reg_suffix ;
278  break;
279  case FramePointerReg:
280  regName = "fp" + reg_suffix;
281  break;
282  case ReturnAddressReg:
283  regName = "lr" + reg_suffix;
284  break;
285  default:
286  regName = "r" + std::to_string(regRelIdx);
287  break;
288  }
289  values[Lo] = thread->readIntReg(regRelIdx);
290 }
291 
292 void
294  const TarmacContext& tarmCtx)
295 {
296  // Generate an instruction entry in the record and
297  // add it to the Instruction Queue
298  queue.push_back(
299  std::make_unique<TraceInstEntry>(tarmCtx, predicate)
300  );
301 }
302 
303 void
305  const TarmacContext& tarmCtx)
306 {
307  // Generate a memory entry in the record if the record
308  // implies a valid memory access, and add it to the
309  // Memory Queue
310  if (getMemValid()) {
311  queue.push_back(
312  std::make_unique<TraceMemEntry>(tarmCtx,
313  static_cast<uint8_t>(getSize()),
314  getAddr(), getIntData())
315  );
316  }
317 }
318 
319 void
321  const TarmacContext& tarmCtx)
322 {
323  // Generate an entry for every ARM register being
324  // written by the current instruction
325  for (auto reg = 0; reg < staticInst->numDestRegs(); ++reg) {
326 
327  RegId reg_id = staticInst->destRegIdx(reg);
328 
329  // Creating a single register change entry
330  auto single_reg = genRegister<TraceRegEntry>(tarmCtx, reg_id);
331 
332  // Copying the entry and adding it to the "list"
333  // of entries to be dumped to trace.
334  queue.push_back(std::make_unique<TraceRegEntry>(single_reg));
335  }
336 
337  // Gem5 is treating CPSR flags as separate registers (CC registers),
338  // in contrast with Tarmac specification: we need to merge the gem5 CC
339  // entries altogether with the CPSR register and produce a single entry.
340  mergeCCEntry<TraceRegEntry>(queue, tarmCtx);
341 }
342 
343 void
345 {
346  // Generate and print all the record's entries.
347  auto &instQueue = tracer.instQueue;
348  auto &memQueue = tracer.memQueue;
349  auto &regQueue = tracer.regQueue;
350 
351  const TarmacContext tarmCtx(
352  thread,
354  pc
355  );
356 
357  if (!staticInst->isMicroop()) {
358  // Current instruction is NOT a micro-instruction:
359  // Generate Tarmac entries and dump them immediately
360 
361  // Generate Tarmac entries and add them to the respective
362  // queues.
363  addInstEntry(instQueue, tarmCtx);
364  addMemEntry(memQueue, tarmCtx);
365  addRegEntry(regQueue, tarmCtx);
366 
367  // Flush (print) any queued entry.
368  flushQueues(instQueue, memQueue, regQueue);
369 
370  } else {
371  // Current instruction is a micro-instruction:
372  // save micro entries into dedicated queues and flush them
373  // into the tracefile only when the MACRO-instruction
374  // has completed.
375 
376  if (staticInst->isFirstMicroop()) {
377  addInstEntry(instQueue, tarmCtx);
378  }
379 
380  addRegEntry(regQueue, tarmCtx);
381  addMemEntry(memQueue, tarmCtx);
382 
383  if (staticInst->isLastMicroop()) {
384  // Flush (print) any queued entry.
385  flushQueues(instQueue, memQueue, regQueue);
386  }
387  }
388 }
389 
390 template<typename Queue>
391 void
393 {
394  std::ostream &outs = Trace::output();
395 
396  for (const auto &single_entry : queue) {
397  single_entry->print(outs);
398  }
399 
400  queue.clear();
401 }
402 
403 template<typename Queue, typename... Args>
404 void
405 TarmacTracerRecord::flushQueues(Queue& queue, Args & ... args)
406 {
407  flushQueues(queue);
408  flushQueues(args...);
409 }
410 
411 void
413  std::ostream& outs,
414  int verbosity,
415  const std::string &prefix) const
416 {
417  // Pad the opcode
418  std::string opcode_str = csprintf("%0*x", instSize >> 2, opcode);
419 
420  // Print the instruction record formatted according
421  // to the Tarmac specification
422  ccprintf(outs, "%s clk %s (%u) %08x %s %s %s_%s : %s\n",
423  curTick(), /* Tick time */
424  taken? "IT" : "IS", /* Instruction taken/skipped */
425  instCount, /* Instruction count */
426  addr, /* Instruction address */
427  opcode_str, /* Instruction opcode */
428  iSetStateToStr(isetstate), /* Instruction Set */
429  opModeToStr(mode), /* Exception level */
430  secureMode? "s" : "ns", /* Security */
431  disassemble); /* Instruction disass */
432 }
433 
434 void
436  std::ostream& outs,
437  int verbosity,
438  const std::string &prefix) const
439 {
440  // Print the memory record formatted according
441  // to the Tarmac specification
442  ccprintf(outs, "%s clk M%s%d %08x %0*x\n",
443  curTick(), /* Tick time */
444  loadAccess? "R" : "W", /* Access type */
445  size, /* Access size */
446  addr, /* Memory address */
447  size*2, /* Padding with access size */
448  data); /* Memory data */
449 }
450 
451 void
453  std::ostream& outs,
454  int verbosity,
455  const std::string &prefix) const
456 {
457  // Print the register record formatted according
458  // to the Tarmac specification
459  if (regValid)
460  ccprintf(outs, "%s clk R %s %08x\n",
461  curTick(), /* Tick time */
462  regName, /* Register name */
463  values[Lo]); /* Register value */
464 }
465 
466 } // namespace Trace
467 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::ArmISA::MODE_EL2H
@ MODE_EL2H
Definition: types.hh:278
gem5::ArmISA::FramePointerReg
const int FramePointerReg
Definition: int.hh:544
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::CCREG_C
@ CCREG_C
Definition: cc.hh:50
gem5::Trace::InstRecord::getAddr
Addr getAddr() const
Definition: insttracer.hh:241
gem5::Trace::iSetStateToStr
std::string iSetStateToStr(TarmacBaseRecord::ISetState isetstate)
Returns the string representation of the instruction set being currently run according to the Tarmac ...
Definition: tarmac_record.cc:56
gem5::bitsToFloat32
static float bitsToFloat32(uint32_t val)
Definition: types.hh:213
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::Trace::TarmacContext
This object type is encapsulating the informations needed by a Tarmac record to generate it's own ent...
Definition: tarmac_tracer.hh:62
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:284
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:208
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:282
gem5::Trace::TarmacTracerRecord::TraceInstEntry::TraceInstEntry
TraceInstEntry(const TarmacContext &tarmCtx, bool predicate)
Definition: tarmac_record.cc:123
gem5::ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ArmISA::MODE_EL2T
@ MODE_EL2T
Definition: types.hh:277
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::Trace::InstRecord::getSize
Addr getSize() const
Definition: insttracer.hh:242
gem5::ArmISA::MODE_EL1H
@ MODE_EL1H
Definition: types.hh:276
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:283
gem5::ArmISA::CCREG_NZ
@ CCREG_NZ
Definition: cc.hh:49
gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateCC
virtual void updateCC(const TarmacContext &tarmCtx, RegIndex regRelIdx)
Definition: tarmac_record.cc:227
gem5::Trace::TarmacBaseRecord
Definition: tarmac_base.hh:64
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::Trace::InstRecord::data
union gem5::Trace::InstRecord::@111 data
sc_dt::to_string
const std::string to_string(sc_enc enc)
Definition: sc_fxdefs.cc:91
gem5::Trace::TarmacTracerRecord::TraceInstEntry::secureMode
bool secureMode
True if instruction is executed in secure mode.
Definition: tarmac_record.hh:111
gem5::ArmISA::ccRegName
const char *const ccRegName[NUM_CCREGS]
Definition: cc.hh:58
gem5::Trace::TarmacBaseRecord::InstEntry::opcode
ArmISA::MachInst opcode
Definition: tarmac_base.hh:94
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::Trace::InstRecord::getIntData
uint64_t getIntData() const
Definition: insttracer.hh:246
gem5::Trace::InstRecord::thread
ThreadContext * thread
Definition: insttracer.hh:65
gem5::ArmISA::miscRegName
const char *const miscRegName[]
Definition: misc.hh:1172
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::ArmISA::ReturnAddressReg
const int ReturnAddressReg
Definition: int.hh:546
std::vector< InstPtr >
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::RefCountingPtr::get
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:227
gem5::sinic::regValid
bool regValid(Addr daddr)
Definition: sinicreg.hh:236
gem5::StaticInst::isFirstMicroop
bool isFirstMicroop() const
Definition: static_inst.hh:211
gem5::ArmISA::MODE_EL3H
@ MODE_EL3H
Definition: types.hh:280
gem5::Trace::TarmacTracer
Tarmac Tracer: this tracer generates a new Tarmac Record for every instruction being executed in gem5...
Definition: tarmac_tracer.hh:85
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateMisc
virtual void updateMisc(const TarmacContext &tarmCtx, RegIndex regRelIdx)
Register update functions.
Definition: tarmac_record.cc:200
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:237
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::MODE_EL3T
@ MODE_EL3T
Definition: types.hh:279
gem5::ArmISA::opcode
Bitfield< 24, 21 > opcode
Definition: types.hh:92
gem5::Trace::TarmacTracerRecord::TraceMemEntry::print
virtual void print(std::ostream &outs, int verbosity=0, const std::string &prefix="") const override
Definition: tarmac_record.cc:435
gem5::Trace::TarmacBaseRecord::ISetState
ISetState
ARM instruction set state.
Definition: tarmac_base.hh:77
gem5::ArmISA::MODE_EL1T
@ MODE_EL1T
Definition: types.hh:275
gem5::Trace::TarmacContext::staticInst
const StaticInstPtr staticInst
Definition: tarmac_tracer.hh:75
gem5::Trace::TarmacTracerRecord::tracer
TarmacTracer & tracer
Reference to tracer.
Definition: tarmac_record.hh:269
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Trace::TarmacBaseRecord::InstEntry
TARMAC instruction trace record.
Definition: tarmac_base.hh:84
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::Trace::TarmacTracerRecord::TraceRegEntry::TraceRegEntry
TraceRegEntry(const TarmacContext &tarmCtx, const RegId &reg)
Definition: tarmac_record.cc:156
gem5::Trace::TarmacTracer::regQueue
std::vector< RegPtr > regQueue
Definition: tarmac_tracer.hh:128
gem5::Trace::InstRecord::getMemValid
bool getMemValid() const
Definition: insttracer.hh:244
gem5::Trace::TarmacTracer::memQueue
std::vector< MemPtr > memQueue
Definition: tarmac_tracer.hh:127
gem5::Trace::InstRecord::pc
TheISA::PCState pc
Definition: insttracer.hh:69
gem5::Trace::TarmacTracerRecord::dump
virtual void dump() override
Definition: tarmac_record.cc:344
gem5::Trace::InstRecord::staticInst
StaticInstPtr staticInst
Definition: insttracer.hh:68
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Trace::TarmacBaseRecord::RegEntry
TARMAC register trace record.
Definition: tarmac_base.hh:101
gem5::Trace::TarmacTracerRecord::addInstEntry
virtual void addInstEntry(std::vector< InstPtr > &queue, const TarmacContext &ptr)
Generates an Entry for the executed instruction.
Definition: tarmac_record.cc:293
gem5::Trace::output
std::ostream & output()
Get the ostream from the current global logger.
Definition: trace.cc:79
gem5::Queue
A high-level queue interface, to be used by both the MSHR queue and the write buffer.
Definition: queue.hh:70
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::Trace::TarmacTracerRecord::addMemEntry
virtual void addMemEntry(std::vector< MemPtr > &queue, const TarmacContext &ptr)
Generates an Entry for every triggered memory access.
Definition: tarmac_record.cc:304
gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateInt
virtual void updateInt(const TarmacContext &tarmCtx, RegIndex regRelIdx)
Definition: tarmac_record.cc:253
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:210
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
gem5::ArmISA::CCREG_GE
@ CCREG_GE
Definition: cc.hh:52
gem5::ArmISA::StackPointerReg
const int StackPointerReg
Definition: int.hh:545
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
tarmac_record.hh
gem5::Trace::TarmacTracerRecord::TraceMemEntry::TraceMemEntry
TraceMemEntry(const TarmacContext &tarmCtx, uint8_t _size, Addr _addr, uint64_t _data)
Definition: tarmac_record.cc:148
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::Trace::InstRecord::size
Addr size
The size of the memory request.
Definition: insttracer.hh:84
tarmac_tracer.hh
gem5::ArmISA::MODE_EL0T
@ MODE_EL0T
Definition: types.hh:274
gem5::Trace::TarmacTracerRecord::addRegEntry
virtual void addRegEntry(std::vector< RegPtr > &queue, const TarmacContext &ptr)
Generate an Entry for every register being written.
Definition: tarmac_record.cc:320
gem5::Trace::InstRecord::predicate
bool predicate
is the predicate for execution this inst true or false (not execed)?
Definition: insttracer.hh:148
gem5::Trace::TarmacTracerRecord::TraceInstEntry::instCount
static uint64_t instCount
Number of instructions being traced.
Definition: tarmac_record.hh:108
gem5::Trace::TarmacTracerRecord::TraceRegEntry::print
virtual void print(std::ostream &outs, int verbosity=0, const std::string &prefix="") const override
Definition: tarmac_record.cc:452
static_inst.hh
gem5::Trace::TarmacBaseRecord::MemEntry
TARMAC memory access trace record (stores only).
Definition: tarmac_base.hh:121
gem5::Trace::InstRecord::addr
Addr addr
The address that was accessed.
Definition: insttracer.hh:83
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:289
gem5::StaticInst::numDestRegs
int8_t numDestRegs() const
Number of destination registers.
Definition: static_inst.hh:141
gem5::Trace::TarmacTracerRecord::flushQueues
void flushQueues(Queue &queue)
Flush queues to the trace output.
Definition: tarmac_record.cc:392
gem5::Trace::opModeToStr
std::string opModeToStr(OperatingMode opMode)
Returns the string representation of the ARM Operating Mode (CPSR.M[3:0] field) according to the Tarm...
Definition: tarmac_record.cc:71
gem5::Trace::TarmacContext::thread
ThreadContext * thread
Definition: tarmac_tracer.hh:74
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:286
gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateFloat
virtual void updateFloat(const TarmacContext &tarmCtx, RegIndex regRelIdx)
Definition: tarmac_record.cc:240
gem5::Trace::TarmacTracerRecord::TraceRegEntry::update
void update(const TarmacContext &tarmCtx)
This updates the register entry using the update table.
Definition: tarmac_record.cc:167
gem5::Trace::InstRecord::macroStaticInst
StaticInstPtr macroStaticInst
Definition: insttracer.hh:70
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Trace::TarmacTracerRecord::TraceInstEntry::instSize
uint8_t instSize
Instruction size: 16 for 16-bit Thumb Instruction 32 otherwise (ARM and BigThumb)
Definition: tarmac_record.hh:117
gem5::ArmISA::CCREG_V
@ CCREG_V
Definition: cc.hh:51
gem5::Trace::TarmacTracer::instQueue
std::vector< InstPtr > instQueue
Collection of heterogeneous printable entries: could be representing either instructions,...
Definition: tarmac_tracer.hh:126
gem5::ArmISA::PCReg
const int PCReg
Definition: int.hh:547
gem5::Trace::TarmacTracerRecord::TraceInstEntry::print
virtual void print(std::ostream &outs, int verbosity=0, const std::string &prefix="") const override
Definition: tarmac_record.cc:412
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73

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