gem5  v21.1.0.2
data64.cc
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37 
38 #include "arch/arm/insts/data64.hh"
39 
40 namespace gem5
41 {
42 
43 namespace ArmISA
44 {
45 
46 std::string
48  Addr pc, const loader::SymbolTable *symtab) const
49 {
50  std::stringstream ss;
51  printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
52  INTREG_ZERO, INTREG_ZERO, 0, LSL, imm);
53  return ss.str();
54 }
55 
56 std::string
58  Addr pc, const loader::SymbolTable *symtab) const
59 {
60  std::stringstream ss;
61  printMnemonic(ss, "", false);
63  ccprintf(ss, ", #%d", imm);
64  return ss.str();
65 }
66 
67 std::string
69  Addr pc, const loader::SymbolTable *symtab) const
70 {
71  std::stringstream ss;
72  printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
73  op2, INTREG_ZERO, shiftAmt, shiftType, 0);
74  return ss.str();
75 }
76 
77 std::string
79  Addr pc, const loader::SymbolTable *symtab) const
80 {
81  std::stringstream ss;
82  printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
83  op2, INTREG_ZERO, shiftAmt, LSL, 0);
84  return ss.str();
85 }
86 
87 std::string
89  Addr pc, const loader::SymbolTable *symtab) const
90 {
91  std::stringstream ss;
92  printMnemonic(ss, "", false);
94  ccprintf(ss, ", ");
95  printIntReg(ss, op1);
96  return ss.str();
97 }
98 
99 std::string
101  Addr pc, const loader::SymbolTable *symtab) const
102 {
103  std::stringstream ss;
104  printMnemonic(ss, "", false);
105  printIntReg(ss, dest);
106  ccprintf(ss, ", ");
107  printIntReg(ss, op1);
108  ccprintf(ss, ", #%d", imm);
109  return ss.str();
110 }
111 
112 std::string
114  Addr pc, const loader::SymbolTable *symtab) const
115 {
116  std::stringstream ss;
117  printMnemonic(ss, "", false);
118  printIntReg(ss, dest);
119  ccprintf(ss, ", ");
120  printIntReg(ss, op1);
121  ccprintf(ss, ", #%d, #%d", imm1, imm2);
122  return ss.str();
123 }
124 
125 std::string
127  Addr pc, const loader::SymbolTable *symtab) const
128 {
129  std::stringstream ss;
130  printMnemonic(ss, "", false);
131  printIntReg(ss, dest);
132  ccprintf(ss, ", ");
133  printIntReg(ss, op1);
134  ccprintf(ss, ", ");
135  printIntReg(ss, op2);
136  return ss.str();
137 }
138 
139 std::string
141  Addr pc, const loader::SymbolTable *symtab) const
142 {
143  std::stringstream ss;
144  printMnemonic(ss, "", false);
145  printIntReg(ss, dest);
146  ccprintf(ss, ", ");
147  printIntReg(ss, op1);
148  ccprintf(ss, ", ");
149  printIntReg(ss, op2);
150  ccprintf(ss, ", #%d", imm);
151  return ss.str();
152 }
153 
154 std::string
156  Addr pc, const loader::SymbolTable *symtab) const
157 {
158  std::stringstream ss;
159  printMnemonic(ss, "", false);
160  printIntReg(ss, dest);
161  ccprintf(ss, ", ");
162  printIntReg(ss, op1);
163  ccprintf(ss, ", ");
164  printIntReg(ss, op2);
165  ccprintf(ss, ", ");
166  printIntReg(ss, op3);
167  return ss.str();
168 }
169 
170 std::string
172  Addr pc, const loader::SymbolTable *symtab) const
173 {
174  std::stringstream ss;
175  printMnemonic(ss, "", false);
176  printIntReg(ss, op1);
177  ccprintf(ss, ", #%d, #%d", imm, defCc);
178  ccprintf(ss, ", ");
179  printCondition(ss, condCode, true);
180  return ss.str();
181 }
182 
183 std::string
185  Addr pc, const loader::SymbolTable *symtab) const
186 {
187  std::stringstream ss;
188  printMnemonic(ss, "", false);
189  printIntReg(ss, op1);
190  ccprintf(ss, ", ");
191  printIntReg(ss, op2);
192  ccprintf(ss, ", #%d", defCc);
193  ccprintf(ss, ", ");
194  printCondition(ss, condCode, true);
195  return ss.str();
196 }
197 
198 std::string
200  Addr pc, const loader::SymbolTable *symtab) const
201 {
202  std::stringstream ss;
203  printMnemonic(ss, "", false);
204  printIntReg(ss, dest);
205  ccprintf(ss, ", ");
206  printIntReg(ss, op1);
207  ccprintf(ss, ", ");
208  printIntReg(ss, op2);
209  ccprintf(ss, ", ");
210  printCondition(ss, condCode, true);
211  return ss.str();
212 }
213 
214 } // namespace ArmISA
215 } // namespace gem5
gem5::ArmISA::DataXSRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:68
gem5::ArmISA::DataX1RegOp::op1
IntRegIndex op1
Definition: data64.hh:123
gem5::ArmISA::DataX3RegOp::op3
IntRegIndex op3
Definition: data64.hh:202
gem5::ArmISA::DataXImmOp::op1
IntRegIndex op1
Definition: data64.hh:53
gem5::ArmISA::DataXERegOp::op1
IntRegIndex op1
Definition: data64.hh:104
gem5::ArmISA::DataX2RegOp::dest
IntRegIndex dest
Definition: data64.hh:170
gem5::ArmISA::DataX1RegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:100
gem5::ArmISA::DataX1RegOp::dest
IntRegIndex dest
Definition: data64.hh:123
gem5::ArmISA::DataXERegOp::shiftAmt
int32_t shiftAmt
Definition: data64.hh:106
gem5::ArmISA::DataX2RegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:126
gem5::ArmISA::DataX1RegImmOp::op1
IntRegIndex op1
Definition: data64.hh:137
gem5::ArmISA::DataXERegOp::dest
IntRegIndex dest
Definition: data64.hh:104
gem5::ArmISA::DataXImmOnlyOp::dest
IntRegIndex dest
Definition: data64.hh:69
gem5::ArmISA::DataX3RegOp::op2
IntRegIndex op2
Definition: data64.hh:202
gem5::ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:377
gem5::ArmISA::DataX2RegImmOp::op1
IntRegIndex op1
Definition: data64.hh:185
gem5::ArmISA::DataXCondSelOp::condCode
ConditionCode condCode
Definition: data64.hh:256
gem5::ArmISA::DataX2RegImmOp::imm
uint64_t imm
Definition: data64.hh:186
gem5::ArmISA::DataXCondCompImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:171
gem5::ArmISA::DataX3RegOp::op1
IntRegIndex op1
Definition: data64.hh:202
gem5::ArmISA::DataX2RegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:140
gem5::ArmISA::DataXCondSelOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:199
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::DataXImmOp::dest
IntRegIndex dest
Definition: data64.hh:53
gem5::ArmISA::DataX1Reg2ImmOp::dest
IntRegIndex dest
Definition: data64.hh:153
gem5::ArmISA::DataXImmOnlyOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:57
gem5::ArmISA::DataXCondCompImmOp::defCc
uint8_t defCc
Definition: data64.hh:221
gem5::ArmISA::DataX1Reg2ImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:113
gem5::ArmISA::DataX3RegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:155
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::DataX2RegOp::op2
IntRegIndex op2
Definition: data64.hh:170
gem5::ArmISA::ArmStaticInst::printCondition
void printCondition(std::ostream &os, unsigned code, bool noImplicit=false) const
Definition: static_inst.cc:417
gem5::ArmISA::DataXCondCompRegOp::op2
IntRegIndex op2
Definition: data64.hh:237
gem5::ArmISA::DataXSRegOp::shiftAmt
int32_t shiftAmt
Definition: data64.hh:86
gem5::ArmISA::DataXCondCompRegOp::op1
IntRegIndex op1
Definition: data64.hh:237
gem5::ArmISA::DataX1Reg2ImmOp::imm2
uint64_t imm2
Definition: data64.hh:154
gem5::ArmISA::DataXCondCompImmOp::op1
IntRegIndex op1
Definition: data64.hh:218
gem5::ArmISA::DataX1Reg2ImmOp::imm1
uint64_t imm1
Definition: data64.hh:154
gem5::ArmISA::DataXERegOp::op2
IntRegIndex op2
Definition: data64.hh:104
gem5::ArmISA::DataXSRegOp::shiftType
ArmShiftType shiftType
Definition: data64.hh:87
gem5::ArmISA::DataXImmOp::imm
uint64_t imm
Definition: data64.hh:54
gem5::ArmISA::DataX1Reg2ImmOp::op1
IntRegIndex op1
Definition: data64.hh:153
gem5::ArmISA::DataX3RegOp::dest
IntRegIndex dest
Definition: data64.hh:202
data64.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::DataXCondCompRegOp::condCode
ConditionCode condCode
Definition: data64.hh:238
gem5::ArmISA::DataX2RegImmOp::dest
IntRegIndex dest
Definition: data64.hh:185
gem5::ArmISA::DataXCondSelOp::op2
IntRegIndex op2
Definition: data64.hh:255
gem5::ArmISA::DataXCondSelOp::op1
IntRegIndex op1
Definition: data64.hh:255
gem5::ArmISA::ArmStaticInst::printDataInst
void printDataInst(std::ostream &os, bool withImm) const
gem5::ArmISA::DataXCondSelOp::dest
IntRegIndex dest
Definition: data64.hh:255
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::ArmISA::DataX1RegImmOp::imm
uint64_t imm
Definition: data64.hh:138
gem5::ArmISA::DataXSRegOp::dest
IntRegIndex dest
Definition: data64.hh:85
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::DataXERegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:78
gem5::ArmISA::DataX2RegImmOp::op2
IntRegIndex op2
Definition: data64.hh:185
gem5::ArmISA::DataXCondCompRegOp::defCc
uint8_t defCc
Definition: data64.hh:239
gem5::ArmISA::DataXSRegOp::op2
IntRegIndex op2
Definition: data64.hh:85
gem5::ArmISA::DataXCondCompImmOp::condCode
ConditionCode condCode
Definition: data64.hh:220
gem5::ArmISA::DataXImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:47
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::DataX1RegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:88
gem5::ArmISA::DataX1RegImmOp::dest
IntRegIndex dest
Definition: data64.hh:137
gem5::ArmISA::DataXImmOnlyOp::imm
uint64_t imm
Definition: data64.hh:70
gem5::ArmISA::DataXCondCompRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:184
gem5::ArmISA::DataX2RegOp::op1
IntRegIndex op1
Definition: data64.hh:170
gem5::ArmISA::DataXCondCompImmOp::imm
uint64_t imm
Definition: data64.hh:219
gem5::ArmISA::DataXSRegOp::op1
IntRegIndex op1
Definition: data64.hh:85

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