gem5  v21.1.0.2
data64.hh
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37 
38 #ifndef __ARCH_ARM_INSTS_DATA64_HH__
39 #define __ARCH_ARM_INSTS_DATA64_HH__
40 
42 #include "base/trace.hh"
43 
44 namespace gem5
45 {
46 
47 namespace ArmISA
48 {
49 
50 class DataXImmOp : public ArmStaticInst
51 {
52  protected:
53  IntRegIndex dest, op1;
54  uint64_t imm;
55 
56  DataXImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
57  IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) :
58  ArmStaticInst(mnem, _machInst, __opClass),
59  dest(_dest), op1(_op1), imm(_imm)
60  {}
61 
62  std::string generateDisassembly(
63  Addr pc, const loader::SymbolTable *symtab) const override;
64 };
65 
67 {
68  protected:
69  IntRegIndex dest;
70  uint64_t imm;
71 
72  DataXImmOnlyOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
73  IntRegIndex _dest, uint64_t _imm) :
74  ArmStaticInst(mnem, _machInst, __opClass),
75  dest(_dest), imm(_imm)
76  {}
77 
78  std::string generateDisassembly(
79  Addr pc, const loader::SymbolTable *symtab) const override;
80 };
81 
82 class DataXSRegOp : public ArmStaticInst
83 {
84  protected:
85  IntRegIndex dest, op1, op2;
86  int32_t shiftAmt;
87  ArmShiftType shiftType;
88 
89  DataXSRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
90  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
91  int32_t _shiftAmt, ArmShiftType _shiftType) :
92  ArmStaticInst(mnem, _machInst, __opClass),
93  dest(_dest), op1(_op1), op2(_op2),
94  shiftAmt(_shiftAmt), shiftType(_shiftType)
95  {}
96 
97  std::string generateDisassembly(
98  Addr pc, const loader::SymbolTable *symtab) const override;
99 };
100 
102 {
103  protected:
104  IntRegIndex dest, op1, op2;
106  int32_t shiftAmt;
107 
108  DataXERegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
109  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
110  ArmExtendType _extendType, int32_t _shiftAmt) :
111  ArmStaticInst(mnem, _machInst, __opClass),
112  dest(_dest), op1(_op1), op2(_op2),
113  extendType(_extendType), shiftAmt(_shiftAmt)
114  {}
115 
116  std::string generateDisassembly(
117  Addr pc, const loader::SymbolTable *symtab) const override;
118 };
119 
121 {
122  protected:
123  IntRegIndex dest, op1;
124 
125  DataX1RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
126  IntRegIndex _dest, IntRegIndex _op1) :
127  ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
128  {}
129 
130  std::string generateDisassembly(
131  Addr pc, const loader::SymbolTable *symtab) const override;
132 };
133 
135 {
136  protected:
137  IntRegIndex dest, op1;
138  uint64_t imm;
139 
140  DataX1RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
141  IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) :
142  ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1),
143  imm(_imm)
144  {}
145 
146  std::string generateDisassembly(
147  Addr pc, const loader::SymbolTable *symtab) const override;
148 };
149 
151 {
152  protected:
153  IntRegIndex dest, op1;
154  uint64_t imm1, imm2;
155 
156  DataX1Reg2ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
157  IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1,
158  uint64_t _imm2) :
159  ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1),
160  imm1(_imm1), imm2(_imm2)
161  {}
162 
163  std::string generateDisassembly(
164  Addr pc, const loader::SymbolTable *symtab) const override;
165 };
166 
168 {
169  protected:
170  IntRegIndex dest, op1, op2;
171 
172  DataX2RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
173  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
174  ArmStaticInst(mnem, _machInst, __opClass),
175  dest(_dest), op1(_op1), op2(_op2)
176  {}
177 
178  std::string generateDisassembly(
179  Addr pc, const loader::SymbolTable *symtab) const override;
180 };
181 
183 {
184  protected:
185  IntRegIndex dest, op1, op2;
186  uint64_t imm;
187 
188  DataX2RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
189  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
190  uint64_t _imm) :
191  ArmStaticInst(mnem, _machInst, __opClass),
192  dest(_dest), op1(_op1), op2(_op2), imm(_imm)
193  {}
194 
195  std::string generateDisassembly(
196  Addr pc, const loader::SymbolTable *symtab) const override;
197 };
198 
200 {
201  protected:
202  IntRegIndex dest, op1, op2, op3;
203 
204  DataX3RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
205  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
206  IntRegIndex _op3) :
207  ArmStaticInst(mnem, _machInst, __opClass),
208  dest(_dest), op1(_op1), op2(_op2), op3(_op3)
209  {}
210 
211  std::string generateDisassembly(
212  Addr pc, const loader::SymbolTable *symtab) const override;
213 };
214 
216 {
217  protected:
218  IntRegIndex op1;
219  uint64_t imm;
221  uint8_t defCc;
222 
223  DataXCondCompImmOp(const char *mnem, ExtMachInst _machInst,
224  OpClass __opClass, IntRegIndex _op1, uint64_t _imm,
225  ConditionCode _condCode, uint8_t _defCc) :
226  ArmStaticInst(mnem, _machInst, __opClass),
227  op1(_op1), imm(_imm), condCode(_condCode), defCc(_defCc)
228  {}
229 
230  std::string generateDisassembly(
231  Addr pc, const loader::SymbolTable *symtab) const override;
232 };
233 
235 {
236  protected:
237  IntRegIndex op1, op2;
239  uint8_t defCc;
240 
241  DataXCondCompRegOp(const char *mnem, ExtMachInst _machInst,
242  OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2,
243  ConditionCode _condCode, uint8_t _defCc) :
244  ArmStaticInst(mnem, _machInst, __opClass),
245  op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc)
246  {}
247 
248  std::string generateDisassembly(
249  Addr pc, const loader::SymbolTable *symtab) const override;
250 };
251 
253 {
254  protected:
255  IntRegIndex dest, op1, op2;
257 
258  DataXCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
259  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
260  ConditionCode _condCode) :
261  ArmStaticInst(mnem, _machInst, __opClass),
262  dest(_dest), op1(_op1), op2(_op2), condCode(_condCode)
263  {}
264 
265  std::string generateDisassembly(
266  Addr pc, const loader::SymbolTable *symtab) const override;
267 };
268 
269 } // namespace ArmISA
270 } // namespace gem5
271 
272 #endif //__ARCH_ARM_INSTS_PREDINST_HH__
gem5::ArmISA::DataXImmOp::DataXImmOp
DataXImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm)
Definition: data64.hh:56
gem5::ArmISA::DataXSRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:68
gem5::ArmISA::DataX1RegOp::op1
IntRegIndex op1
Definition: data64.hh:123
gem5::ArmISA::DataX3RegOp::op3
IntRegIndex op3
Definition: data64.hh:202
gem5::ArmISA::DataXImmOp::op1
IntRegIndex op1
Definition: data64.hh:53
gem5::ArmISA::DataXERegOp::op1
IntRegIndex op1
Definition: data64.hh:104
gem5::ArmISA::DataX2RegOp::dest
IntRegIndex dest
Definition: data64.hh:170
gem5::ArmISA::DataX1RegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:100
gem5::ArmISA::DataX1RegOp::dest
IntRegIndex dest
Definition: data64.hh:123
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::ArmISA::DataXERegOp::shiftAmt
int32_t shiftAmt
Definition: data64.hh:106
gem5::ArmISA::DataX2RegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:126
gem5::ArmISA::DataX1RegImmOp::op1
IntRegIndex op1
Definition: data64.hh:137
gem5::ArmISA::DataXCondCompImmOp::DataXCondCompImmOp
DataXCondCompImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1, uint64_t _imm, ConditionCode _condCode, uint8_t _defCc)
Definition: data64.hh:223
gem5::ArmISA::DataXERegOp::dest
IntRegIndex dest
Definition: data64.hh:104
gem5::ArmISA::DataXCondCompImmOp
Definition: data64.hh:215
gem5::ArmISA::DataXImmOnlyOp::dest
IntRegIndex dest
Definition: data64.hh:69
gem5::ArmISA::DataXCondCompRegOp::DataXCondCompRegOp
DataXCondCompRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode, uint8_t _defCc)
Definition: data64.hh:241
gem5::ArmISA::DataX3RegOp::op2
IntRegIndex op2
Definition: data64.hh:202
gem5::ArmISA::DataX1RegImmOp::DataX1RegImmOp
DataX1RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm)
Definition: data64.hh:140
gem5::ArmISA::DataX2RegImmOp::op1
IntRegIndex op1
Definition: data64.hh:185
gem5::ArmISA::DataXCondSelOp::condCode
ConditionCode condCode
Definition: data64.hh:256
gem5::ArmISA::DataXERegOp
Definition: data64.hh:101
gem5::ArmISA::DataX2RegOp::DataX2RegOp
DataX2RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2)
Definition: data64.hh:172
gem5::ArmISA::DataX2RegImmOp::imm
uint64_t imm
Definition: data64.hh:186
gem5::ArmISA::ArmExtendType
ArmExtendType
Definition: types.hh:215
gem5::ArmISA::DataXCondCompImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:171
gem5::ArmISA::DataX3RegOp::op1
IntRegIndex op1
Definition: data64.hh:202
gem5::ArmISA::DataX2RegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:140
gem5::ArmISA::DataXCondSelOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:199
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::DataXImmOp::dest
IntRegIndex dest
Definition: data64.hh:53
gem5::ArmISA::DataX1Reg2ImmOp::dest
IntRegIndex dest
Definition: data64.hh:153
gem5::ArmISA::DataXImmOnlyOp::DataXImmOnlyOp
DataXImmOnlyOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, uint64_t _imm)
Definition: data64.hh:72
gem5::ArmISA::DataXImmOnlyOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:57
gem5::ArmISA::DataXCondCompImmOp::defCc
uint8_t defCc
Definition: data64.hh:221
gem5::ArmISA::DataX1Reg2ImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:113
gem5::ArmISA::DataX3RegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:155
gem5::ArmISA::DataX2RegOp::op2
IntRegIndex op2
Definition: data64.hh:170
gem5::ArmISA::DataX1Reg2ImmOp
Definition: data64.hh:150
gem5::ArmISA::DataXSRegOp::DataXSRegOp
DataXSRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, int32_t _shiftAmt, ArmShiftType _shiftType)
Definition: data64.hh:89
gem5::ArmISA::DataXCondCompRegOp
Definition: data64.hh:234
gem5::ArmISA::DataXCondCompRegOp::op2
IntRegIndex op2
Definition: data64.hh:237
gem5::ArmISA::DataXSRegOp::shiftAmt
int32_t shiftAmt
Definition: data64.hh:86
gem5::ArmISA::DataX2RegImmOp::DataX2RegImmOp
DataX2RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm)
Definition: data64.hh:188
gem5::ArmISA::DataX3RegOp::DataX3RegOp
DataX3RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3)
Definition: data64.hh:204
gem5::ArmISA::DataXERegOp::extendType
ArmExtendType extendType
Definition: data64.hh:105
gem5::ArmISA::DataX3RegOp
Definition: data64.hh:199
gem5::ArmISA::DataXCondCompRegOp::op1
IntRegIndex op1
Definition: data64.hh:237
gem5::ArmISA::DataX1Reg2ImmOp::imm2
uint64_t imm2
Definition: data64.hh:154
gem5::ArmISA::DataXCondCompImmOp::op1
IntRegIndex op1
Definition: data64.hh:218
gem5::ArmISA::DataX2RegOp
Definition: data64.hh:167
gem5::ArmISA::DataXERegOp::DataXERegOp
DataXERegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ArmExtendType _extendType, int32_t _shiftAmt)
Definition: data64.hh:108
gem5::ArmISA::DataX1RegOp::DataX1RegOp
DataX1RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1)
Definition: data64.hh:125
gem5::ArmISA::DataX1Reg2ImmOp::imm1
uint64_t imm1
Definition: data64.hh:154
gem5::ArmISA::DataXERegOp::op2
IntRegIndex op2
Definition: data64.hh:104
gem5::ArmISA::DataXSRegOp::shiftType
ArmShiftType shiftType
Definition: data64.hh:87
gem5::ArmISA::DataXImmOp::imm
uint64_t imm
Definition: data64.hh:54
gem5::ArmISA::DataX1Reg2ImmOp::op1
IntRegIndex op1
Definition: data64.hh:153
gem5::ArmISA::DataX3RegOp::dest
IntRegIndex dest
Definition: data64.hh:202
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::DataXCondCompRegOp::condCode
ConditionCode condCode
Definition: data64.hh:238
gem5::ArmISA::DataXCondSelOp
Definition: data64.hh:252
gem5::ArmISA::DataX2RegImmOp::dest
IntRegIndex dest
Definition: data64.hh:185
gem5::ArmISA::DataX1Reg2ImmOp::DataX1Reg2ImmOp
DataX1Reg2ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, uint64_t _imm2)
Definition: data64.hh:156
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::DataXCondSelOp::op2
IntRegIndex op2
Definition: data64.hh:255
gem5::ArmISA::DataXCondSelOp::DataXCondSelOp
DataXCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode)
Definition: data64.hh:258
gem5::ArmISA::DataXCondSelOp::op1
IntRegIndex op1
Definition: data64.hh:255
gem5::ArmISA::DataXImmOp
Definition: data64.hh:50
gem5::ArmISA::DataXCondSelOp::dest
IntRegIndex dest
Definition: data64.hh:255
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:67
gem5::ArmISA::DataX1RegImmOp::imm
uint64_t imm
Definition: data64.hh:138
gem5::ArmISA::DataXSRegOp::dest
IntRegIndex dest
Definition: data64.hh:85
static_inst.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::DataXERegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:78
gem5::ArmISA::DataX2RegImmOp::op2
IntRegIndex op2
Definition: data64.hh:185
gem5::ArmISA::DataXCondCompRegOp::defCc
uint8_t defCc
Definition: data64.hh:239
gem5::ArmISA::DataXSRegOp::op2
IntRegIndex op2
Definition: data64.hh:85
gem5::ArmISA::DataXCondCompImmOp::condCode
ConditionCode condCode
Definition: data64.hh:220
gem5::ArmISA::DataX1RegImmOp
Definition: data64.hh:134
gem5::ArmISA::DataX2RegImmOp
Definition: data64.hh:182
trace.hh
gem5::ArmISA::DataXImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:47
gem5::ArmISA::DataXSRegOp
Definition: data64.hh:82
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::DataX1RegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:88
gem5::ArmISA::DataX1RegImmOp::dest
IntRegIndex dest
Definition: data64.hh:137
gem5::ArmISA::DataXImmOnlyOp::imm
uint64_t imm
Definition: data64.hh:70
gem5::ArmISA::DataXCondCompRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: data64.cc:184
gem5::ArmISA::DataX2RegOp::op1
IntRegIndex op1
Definition: data64.hh:170
gem5::ArmISA::DataXImmOnlyOp
Definition: data64.hh:66
gem5::ArmISA::DataX1RegOp
Definition: data64.hh:120
gem5::ArmISA::DataXCondCompImmOp::imm
uint64_t imm
Definition: data64.hh:219
gem5::ArmISA::DataXSRegOp::op1
IntRegIndex op1
Definition: data64.hh:85

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