gem5  v21.2.0.0
fetch2.hh
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37 
45 #ifndef __CPU_MINOR_FETCH2_HH__
46 #define __CPU_MINOR_FETCH2_HH__
47 
48 #include <vector>
49 
50 #include "base/named.hh"
51 #include "cpu/minor/buffers.hh"
52 #include "cpu/minor/cpu.hh"
53 #include "cpu/minor/pipe_data.hh"
54 #include "cpu/pred/bpred_unit.hh"
55 #include "params/MinorCPU.hh"
56 
57 namespace gem5
58 {
59 
61 namespace minor
62 {
63 
66 class Fetch2 : public Named
67 {
68  protected:
71 
74 
78 
81 
84 
87 
89  unsigned int outputWidth;
90 
94 
97 
98  public:
99  /* Public so that Pipeline can pass it to Fetch1 */
101 
102  protected:
106  {
108 
110  inputIndex(other.inputIndex),
111  havePC(other.havePC),
115  blocked(other.blocked)
116  {
117  set(pc, other.pc);
118  }
119 
122  unsigned int inputIndex = 0;
123 
124 
131  std::unique_ptr<PCStateBase> pc;
132 
136  bool havePC = false;
137 
141 
145 
151 
156 
158  bool blocked = false;
159  };
160 
163 
165  {
174  } stats;
175 
176  protected:
179  const ForwardLineData *getInput(ThreadID tid);
180 
182  void popInput(ThreadID tid);
183 
186  void dumpAllInput(ThreadID tid);
187 
190  void updateBranchPrediction(const BranchData &branch);
191 
195  void predictBranch(MinorDynInstPtr inst, BranchData &branch);
196 
200 
201  public:
202  Fetch2(const std::string &name,
203  MinorCPU &cpu_,
204  const MinorCPUParams &params,
206  Latch<BranchData>::Output branchInp_,
207  Latch<BranchData>::Input predictionOut_,
209  std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);
210 
211  public:
213  void evaluate();
214 
215  void minorTrace() const;
216 
217 
221  bool isDrained();
222 };
223 
224 } // namespace minor
225 } // namespace gem5
226 
227 #endif /* __CPU_MINOR_FETCH2_HH__ */
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
pipe_data.hh
gem5::minor::ForwardLineData
Line fetch data in the forward direction.
Definition: pipe_data.hh:187
gem5::minor::InstId::firstPredictionSeqNum
static const InstSeqNum firstPredictionSeqNum
Definition: dyn_inst.hh:82
gem5::minor::Fetch2::Fetch2ThreadInfo::pc
std::unique_ptr< PCStateBase > pc
Remembered program counter value.
Definition: fetch2.hh:131
gem5::minor::Fetch2::Fetch2ThreadInfo::lastStreamSeqNum
InstSeqNum lastStreamSeqNum
Stream sequence number of the last seen line used to identify changes of instruction stream.
Definition: fetch2.hh:140
gem5::minor::Fetch2::Fetch2ThreadInfo
Data members after this line are cycle-to-cycle state.
Definition: fetch2.hh:105
named.hh
gem5::minor::Fetch2::processMoreThanOneInput
bool processMoreThanOneInput
If true, more than one input word can be processed each cycle if there is room in the output to conta...
Definition: fetch2.hh:93
cpu.hh
minor
gem5::MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:85
gem5::minor::Fetch2::minorTrace
void minorTrace() const
Definition: fetch2.cc:634
std::vector
STL vector class.
Definition: stl.hh:37
gem5::minor::Fetch2::Fetch2Stats::loadInstructions
statistics::Scalar loadInstructions
Definition: fetch2.hh:171
gem5::minor::InstId::firstFetchSeqNum
static const InstSeqNum firstFetchSeqNum
Definition: dyn_inst.hh:84
gem5::minor::Fetch2::updateBranchPrediction
void updateBranchPrediction(const BranchData &branch)
Update local branch prediction structures from feedback from Execute.
Definition: fetch2.cc:130
gem5::minor::Fetch2
This stage receives lines of data from Fetch1, separates them into instructions and passes them to De...
Definition: fetch2.hh:66
gem5::minor::InstId::firstStreamSeqNum
static const InstSeqNum firstStreamSeqNum
First sequence numbers to use in initialisation of the pipeline and to be expected on the first line/...
Definition: dyn_inst.hh:81
gem5::minor::Fetch2::Fetch2ThreadInfo::inputIndex
unsigned int inputIndex
Index into an incompletely processed input line that instructions are to be extracted from.
Definition: fetch2.hh:122
gem5::minor::Fetch2::branchPredictor
branch_prediction::BPredUnit & branchPredictor
Branch predictor passed from Python configuration.
Definition: fetch2.hh:96
gem5::RefCountingPtr< MinorDynInst >
gem5::minor::Fetch2::inp
Latch< ForwardLineData >::Output inp
Input port carrying lines from Fetch1.
Definition: fetch2.hh:73
gem5::minor::InputBuffer
Like a Queue but with a restricted interface and a setTail function which, when the queue is empty,...
Definition: buffers.hh:572
gem5::minor::Fetch2::predictionOut
Latch< BranchData >::Input predictionOut
Output port carrying predictions back to Fetch1.
Definition: fetch2.hh:80
gem5::Named
Interface for things with names.
Definition: named.hh:38
gem5::minor::Latch::Output
Definition: buffers.hh:263
gem5::minor::Fetch2::getInput
const ForwardLineData * getInput(ThreadID tid)
Get a piece of data to work on from the inputBuffer, or 0 if there is no data.
Definition: fetch2.cc:98
gem5::minor::Fetch2::Fetch2Stats::vecInstructions
statistics::Scalar vecInstructions
Definition: fetch2.hh:170
gem5::minor::Fetch2::branchInp
Latch< BranchData >::Output branchInp
Input port carrying branches from Execute.
Definition: fetch2.hh:77
gem5::minor::Fetch2::Fetch2ThreadInfo::Fetch2ThreadInfo
Fetch2ThreadInfo()
Definition: fetch2.hh:107
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::minor::Latch::Input
Encapsulate wires on either input or output of the latch.
Definition: buffers.hh:252
gem5::minor::Fetch2::Fetch2ThreadInfo::predictionSeqNum
InstSeqNum predictionSeqNum
Fetch2 is the source of prediction sequence numbers.
Definition: fetch2.hh:155
gem5::minor::Fetch2::fetchInfo
std::vector< Fetch2ThreadInfo > fetchInfo
Definition: fetch2.hh:161
gem5::minor::BranchData
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
Definition: pipe_data.hh:66
gem5::minor::Fetch2::Fetch2Stats::intInstructions
statistics::Scalar intInstructions
Stats.
Definition: fetch2.hh:168
gem5::minor::Fetch2::Fetch2ThreadInfo::Fetch2ThreadInfo
Fetch2ThreadInfo(const Fetch2ThreadInfo &other)
Definition: fetch2.hh:109
gem5::minor::Fetch2::dumpAllInput
void dumpAllInput(ThreadID tid)
Dump the whole contents of the input buffer.
Definition: fetch2.cc:120
gem5::minor::Fetch2::threadPriority
ThreadID threadPriority
Definition: fetch2.hh:162
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::minor::Fetch2::evaluate
void evaluate()
Pass on input/buffer data to the output if you can.
Definition: fetch2.cc:240
gem5::minor::Fetch2::isDrained
bool isDrained()
Is this stage drained? For Fetch2, draining is initiated by Execute halting Fetch1 causing Fetch2 to ...
Definition: fetch2.cc:593
gem5::minor::Fetch2::inputBuffer
std::vector< InputBuffer< ForwardLineData > > inputBuffer
Definition: fetch2.hh:100
gem5::minor::Fetch2::popInput
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
Definition: fetch2.cc:109
gem5::minor::Fetch2::cpu
MinorCPU & cpu
Pointer back to the containing CPU.
Definition: fetch2.hh:70
gem5::minor::Fetch2::Fetch2Stats::amoInstructions
statistics::Scalar amoInstructions
Definition: fetch2.hh:173
gem5::minor::Fetch2::Fetch2Stats
Definition: fetch2.hh:164
gem5::minor::Fetch2::Fetch2Stats::Fetch2Stats
Fetch2Stats(MinorCPU *cpu)
Definition: fetch2.cc:604
bpred_unit.hh
gem5::minor::Fetch2::out
Latch< ForwardInstData >::Input out
Output port carrying instructions into Decode.
Definition: fetch2.hh:83
gem5::minor::Fetch2::Fetch2
Fetch2(const std::string &name, MinorCPU &cpu_, const MinorCPUParams &params, Latch< ForwardLineData >::Output inp_, Latch< BranchData >::Output branchInp_, Latch< BranchData >::Input predictionOut_, Latch< ForwardInstData >::Input out_, std::vector< InputBuffer< ForwardInstData >> &next_stage_input_buffer)
Definition: fetch2.cc:59
gem5::minor::Fetch2::Fetch2ThreadInfo::havePC
bool havePC
PC is currently valid.
Definition: fetch2.hh:136
gem5::branch_prediction::BPredUnit
Basically a wrapper class to hold both the branch predictor and the BTB.
Definition: bpred_unit.hh:68
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
buffers.hh
gem5::minor::Fetch2::Fetch2ThreadInfo::expectedStreamSeqNum
InstSeqNum expectedStreamSeqNum
Stream sequence number remembered from last time the predictionSeqNum changed.
Definition: fetch2.hh:150
gem5::minor::Fetch2::stats
gem5::minor::Fetch2::Fetch2Stats stats
gem5::minor::Fetch2::Fetch2ThreadInfo::fetchSeqNum
InstSeqNum fetchSeqNum
Fetch2 is the source of fetch sequence numbers.
Definition: fetch2.hh:144
gem5::minor::Fetch2::Fetch2Stats::fpInstructions
statistics::Scalar fpInstructions
Definition: fetch2.hh:169
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::minor::Fetch2::Fetch2Stats::storeInstructions
statistics::Scalar storeInstructions
Definition: fetch2.hh:172
gem5::minor::Fetch2::nextStageReserve
std::vector< InputBuffer< ForwardInstData > > & nextStageReserve
Interface to reserve space in the next stage.
Definition: fetch2.hh:86
gem5::minor::Fetch2::getScheduledThread
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to fetch from.
Definition: fetch2.cc:563
gem5::minor::Fetch2::Fetch2ThreadInfo::blocked
bool blocked
Blocked indication for report.
Definition: fetch2.hh:158
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::minor::Fetch2::outputWidth
unsigned int outputWidth
Width of output of this stage/input of next in instructions.
Definition: fetch2.hh:89
gem5::minor::Fetch2::predictBranch
void predictBranch(MinorDynInstPtr inst, BranchData &branch)
Predicts branches for the given instruction.
Definition: fetch2.cc:192

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