gem5  v21.1.0.2
fetch2.cc
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37 
38 #include "cpu/minor/fetch2.hh"
39 
40 #include <string>
41 
42 #include "arch/decoder.hh"
43 #include "base/logging.hh"
44 #include "base/trace.hh"
45 #include "cpu/minor/pipeline.hh"
46 #include "cpu/null_static_inst.hh"
47 #include "cpu/pred/bpred_unit.hh"
48 #include "debug/Branch.hh"
49 #include "debug/Fetch.hh"
50 #include "debug/MinorTrace.hh"
51 
52 namespace gem5
53 {
54 
56 namespace minor
57 {
58 
59 Fetch2::Fetch2(const std::string &name,
60  MinorCPU &cpu_,
61  const MinorCPUParams &params,
63  Latch<BranchData>::Output branchInp_,
64  Latch<BranchData>::Input predictionOut_,
66  std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer) :
67  Named(name),
68  cpu(cpu_),
69  inp(inp_),
70  branchInp(branchInp_),
71  predictionOut(predictionOut_),
72  out(out_),
73  nextStageReserve(next_stage_input_buffer),
74  outputWidth(params.decodeInputWidth),
75  processMoreThanOneInput(params.fetch2CycleInput),
76  branchPredictor(*params.branchPred),
77  fetchInfo(params.numThreads),
78  threadPriority(0), stats(&cpu_)
79 {
80  if (outputWidth < 1)
81  fatal("%s: decodeInputWidth must be >= 1 (%d)\n", name, outputWidth);
82 
83  if (params.fetch2InputBufferSize < 1) {
84  fatal("%s: fetch2InputBufferSize must be >= 1 (%d)\n", name,
85  params.fetch2InputBufferSize);
86  }
87 
88  /* Per-thread input buffers */
89  for (ThreadID tid = 0; tid < params.numThreads; tid++) {
90  inputBuffer.push_back(
92  name + ".inputBuffer" + std::to_string(tid), "lines",
93  params.fetch2InputBufferSize));
94  }
95 }
96 
97 const ForwardLineData *
99 {
100  /* Get a line from the inputBuffer to work with */
101  if (!inputBuffer[tid].empty()) {
102  return &(inputBuffer[tid].front());
103  } else {
104  return NULL;
105  }
106 }
107 
108 void
110 {
111  if (!inputBuffer[tid].empty()) {
112  inputBuffer[tid].front().freeLine();
113  inputBuffer[tid].pop();
114  }
115 
116  fetchInfo[tid].inputIndex = 0;
117 }
118 
119 void
121 {
122  DPRINTF(Fetch, "Dumping whole input buffer\n");
123  while (!inputBuffer[tid].empty())
124  popInput(tid);
125 
126  fetchInfo[tid].inputIndex = 0;
127 }
128 
129 void
131 {
132  MinorDynInstPtr inst = branch.inst;
133 
134  /* Don't even consider instructions we didn't try to predict or faults */
135  if (inst->isFault() || !inst->triedToPredict)
136  return;
137 
138  switch (branch.reason) {
140  /* No data to update */
141  break;
143  /* Never try to predict interrupts */
144  break;
146  /* Don't need to act on suspends */
147  break;
149  /* Don't need to act on fetch wakeup */
150  break;
152  /* Shouldn't happen. Fetch2 is the only source of
153  * BranchPredictions */
154  break;
156  /* Unpredicted branch or barrier */
157  DPRINTF(Branch, "Unpredicted branch seen inst: %s\n", *inst);
158  branchPredictor.squash(inst->id.fetchSeqNum,
159  branch.target, true, inst->id.threadId);
160  // Update after squashing to accomodate O3CPU
161  // using the branch prediction code.
162  branchPredictor.update(inst->id.fetchSeqNum,
163  inst->id.threadId);
164  break;
166  /* Predicted taken, was taken */
167  DPRINTF(Branch, "Branch predicted correctly inst: %s\n", *inst);
168  branchPredictor.update(inst->id.fetchSeqNum,
169  inst->id.threadId);
170  break;
172  /* Predicted taken, not taken */
173  DPRINTF(Branch, "Branch mis-predicted inst: %s\n", *inst);
174  branchPredictor.squash(inst->id.fetchSeqNum,
175  branch.target /* Not used */, false, inst->id.threadId);
176  // Update after squashing to accomodate O3CPU
177  // using the branch prediction code.
178  branchPredictor.update(inst->id.fetchSeqNum,
179  inst->id.threadId);
180  break;
182  /* Predicted taken, was taken but to a different target */
183  DPRINTF(Branch, "Branch mis-predicted target inst: %s target: %s\n",
184  *inst, branch.target);
185  branchPredictor.squash(inst->id.fetchSeqNum,
186  branch.target, true, inst->id.threadId);
187  break;
188  }
189 }
190 
191 void
193 {
194  Fetch2ThreadInfo &thread = fetchInfo[inst->id.threadId];
195  TheISA::PCState inst_pc = inst->pc;
196 
197  assert(!inst->predictedTaken);
198 
199  /* Skip non-control/sys call instructions */
200  if (inst->staticInst->isControl() ||
201  inst->staticInst->isSyscall())
202  {
203  /* Tried to predict */
204  inst->triedToPredict = true;
205 
206  DPRINTF(Branch, "Trying to predict for inst: %s\n", *inst);
207 
208  if (branchPredictor.predict(inst->staticInst,
209  inst->id.fetchSeqNum, inst_pc,
210  inst->id.threadId))
211  {
212  inst->predictedTaken = true;
213  inst->predictedTarget = inst_pc;
214  branch.target = inst_pc;
215  }
216  } else {
217  DPRINTF(Branch, "Not attempting prediction for inst: %s\n", *inst);
218  }
219 
220  /* If we predict taken, set branch and update sequence numbers */
221  if (inst->predictedTaken) {
222  /* Update the predictionSeqNum and remember the streamSeqNum that it
223  * was associated with */
224  thread.expectedStreamSeqNum = inst->id.streamSeqNum;
225 
227  inst->id.threadId,
228  inst->id.streamSeqNum, thread.predictionSeqNum + 1,
229  inst->predictedTarget, inst);
230 
231  /* Mark with a new prediction number by the stream number of the
232  * instruction causing the prediction */
233  thread.predictionSeqNum++;
234  branch = new_branch;
235 
236  DPRINTF(Branch, "Branch predicted taken inst: %s target: %s"
237  " new predictionSeqNum: %d\n",
238  *inst, inst->predictedTarget, thread.predictionSeqNum);
239  }
240 }
241 
242 void
244 {
245  /* Push input onto appropriate input buffer */
246  if (!inp.outputWire->isBubble())
247  inputBuffer[inp.outputWire->id.threadId].setTail(*inp.outputWire);
248 
249  ForwardInstData &insts_out = *out.inputWire;
250  BranchData prediction;
251  BranchData &branch_inp = *branchInp.outputWire;
252 
253  assert(insts_out.isBubble());
254 
255  /* React to branches from Execute to update local branch prediction
256  * structures */
257  updateBranchPrediction(branch_inp);
258 
259  /* If a branch arrives, don't try and do anything about it. Only
260  * react to your own predictions */
261  if (branch_inp.isStreamChange()) {
262  DPRINTF(Fetch, "Dumping all input as a stream changing branch"
263  " has arrived\n");
264  dumpAllInput(branch_inp.threadId);
265  fetchInfo[branch_inp.threadId].havePC = false;
266  }
267 
268  assert(insts_out.isBubble());
269  /* Even when blocked, clear out input lines with the wrong
270  * prediction sequence number */
271  for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
272  Fetch2ThreadInfo &thread = fetchInfo[tid];
273 
274  thread.blocked = !nextStageReserve[tid].canReserve();
275 
276  const ForwardLineData *line_in = getInput(tid);
277 
278  while (line_in &&
279  thread.expectedStreamSeqNum == line_in->id.streamSeqNum &&
280  thread.predictionSeqNum != line_in->id.predictionSeqNum)
281  {
282  DPRINTF(Fetch, "Discarding line %s"
283  " due to predictionSeqNum mismatch (expected: %d)\n",
284  line_in->id, thread.predictionSeqNum);
285 
286  popInput(tid);
287  fetchInfo[tid].havePC = false;
288 
290  DPRINTF(Fetch, "Wrapping\n");
291  line_in = getInput(tid);
292  } else {
293  line_in = NULL;
294  }
295  }
296  }
297 
299  DPRINTF(Fetch, "Scheduled Thread: %d\n", tid);
300 
301  assert(insts_out.isBubble());
302  if (tid != InvalidThreadID) {
303  Fetch2ThreadInfo &fetch_info = fetchInfo[tid];
304 
305  const ForwardLineData *line_in = getInput(tid);
306 
307  unsigned int output_index = 0;
308 
309  /* Pack instructions into the output while we can. This may involve
310  * using more than one input line. Note that lineWidth will be 0
311  * for faulting lines */
312  while (line_in &&
313  (line_in->isFault() ||
314  fetch_info.inputIndex < line_in->lineWidth) && /* More input */
315  output_index < outputWidth && /* More output to fill */
316  prediction.isBubble() /* No predicted branch */)
317  {
318  ThreadContext *thread = cpu.getContext(line_in->id.threadId);
319  TheISA::Decoder *decoder = thread->getDecoderPtr();
320 
321  /* Discard line due to prediction sequence number being wrong but
322  * without the streamSeqNum number having changed */
323  bool discard_line =
324  fetch_info.expectedStreamSeqNum == line_in->id.streamSeqNum &&
325  fetch_info.predictionSeqNum != line_in->id.predictionSeqNum;
326 
327  /* Set the PC if the stream changes. Setting havePC to false in
328  * a previous cycle handles all other change of flow of control
329  * issues */
330  bool set_pc = fetch_info.lastStreamSeqNum != line_in->id.streamSeqNum;
331 
332  if (!discard_line && (!fetch_info.havePC || set_pc)) {
333  /* Set the inputIndex to be the MachInst-aligned offset
334  * from lineBaseAddr of the new PC value */
335  fetch_info.inputIndex =
336  (line_in->pc.instAddr() & decoder->pcMask()) -
337  line_in->lineBaseAddr;
338  DPRINTF(Fetch, "Setting new PC value: %s inputIndex: 0x%x"
339  " lineBaseAddr: 0x%x lineWidth: 0x%x\n",
340  line_in->pc, fetch_info.inputIndex, line_in->lineBaseAddr,
341  line_in->lineWidth);
342  fetch_info.pc = line_in->pc;
343  fetch_info.havePC = true;
344  decoder->reset();
345  }
346 
347  /* The generated instruction. Leave as NULL if no instruction
348  * is to be packed into the output */
349  MinorDynInstPtr dyn_inst = NULL;
350 
351  if (discard_line) {
352  /* Rest of line was from an older prediction in the same
353  * stream */
354  DPRINTF(Fetch, "Discarding line %s (from inputIndex: %d)"
355  " due to predictionSeqNum mismatch (expected: %d)\n",
356  line_in->id, fetch_info.inputIndex,
357  fetch_info.predictionSeqNum);
358  } else if (line_in->isFault()) {
359  /* Pack a fault as a MinorDynInst with ->fault set */
360 
361  /* Make a new instruction and pick up the line, stream,
362  * prediction, thread ids from the incoming line */
363  dyn_inst = new MinorDynInst(nullStaticInstPtr, line_in->id);
364 
365  /* Fetch and prediction sequence numbers originate here */
366  dyn_inst->id.fetchSeqNum = fetch_info.fetchSeqNum;
367  dyn_inst->id.predictionSeqNum = fetch_info.predictionSeqNum;
368  /* To complete the set, test that exec sequence number has
369  * not been set */
370  assert(dyn_inst->id.execSeqNum == 0);
371 
372  dyn_inst->pc = fetch_info.pc;
373 
374  /* Pack a faulting instruction but allow other
375  * instructions to be generated. (Fetch2 makes no
376  * immediate judgement about streamSeqNum) */
377  dyn_inst->fault = line_in->fault;
378  DPRINTF(Fetch, "Fault being passed output_index: "
379  "%d: %s\n", output_index, dyn_inst->fault->name());
380  } else {
381  uint8_t *line = line_in->line;
382 
383  /* The instruction is wholly in the line, can just copy. */
384  memcpy(decoder->moreBytesPtr(), line + fetch_info.inputIndex,
385  decoder->moreBytesSize());
386 
387  if (!decoder->instReady()) {
388  decoder->moreBytes(fetch_info.pc,
389  line_in->lineBaseAddr + fetch_info.inputIndex);
390  DPRINTF(Fetch, "Offering MachInst to decoder addr: 0x%x\n",
391  line_in->lineBaseAddr + fetch_info.inputIndex);
392  }
393 
394  /* Maybe make the above a loop to accomodate ISAs with
395  * instructions longer than sizeof(MachInst) */
396 
397  if (decoder->instReady()) {
398  /* Note that the decoder can update the given PC.
399  * Remember not to assign it until *after* calling
400  * decode */
401  StaticInstPtr decoded_inst =
402  decoder->decode(fetch_info.pc);
403 
404  /* Make a new instruction and pick up the line, stream,
405  * prediction, thread ids from the incoming line */
406  dyn_inst = new MinorDynInst(decoded_inst, line_in->id);
407 
408  /* Fetch and prediction sequence numbers originate here */
409  dyn_inst->id.fetchSeqNum = fetch_info.fetchSeqNum;
410  dyn_inst->id.predictionSeqNum = fetch_info.predictionSeqNum;
411  /* To complete the set, test that exec sequence number
412  * has not been set */
413  assert(dyn_inst->id.execSeqNum == 0);
414 
415  dyn_inst->pc = fetch_info.pc;
416  DPRINTF(Fetch, "decoder inst %s\n", *dyn_inst);
417 
418  // Collect some basic inst class stats
419  if (decoded_inst->isLoad())
421  else if (decoded_inst->isStore())
423  else if (decoded_inst->isAtomic())
425  else if (decoded_inst->isVector())
427  else if (decoded_inst->isFloating())
429  else if (decoded_inst->isInteger())
431 
432  DPRINTF(Fetch, "Instruction extracted from line %s"
433  " lineWidth: %d output_index: %d inputIndex: %d"
434  " pc: %s inst: %s\n",
435  line_in->id,
436  line_in->lineWidth, output_index, fetch_info.inputIndex,
437  fetch_info.pc, *dyn_inst);
438 
439 #if THE_ISA == X86_ISA || THE_ISA == ARM_ISA
440  /* In SE mode, it's possible to branch to a microop when
441  * replaying faults such as page faults (or simply
442  * intra-microcode branches in X86). Unfortunately,
443  * as Minor has micro-op decomposition in a separate
444  * pipeline stage from instruction decomposition, the
445  * following advancePC (which may follow a branch with
446  * microPC() != 0) *must* see a fresh macroop. This
447  * kludge should be improved with an addition to PCState
448  * but I offer it in this form for the moment
449  *
450  * X86 can branch within microops so we need to deal with
451  * the case that, after a branch, the first un-advanced PC
452  * may be pointing to a microop other than 0. Once
453  * advanced, however, the microop number *must* be 0 */
454  fetch_info.pc.upc(0);
455  fetch_info.pc.nupc(1);
456 #endif
457 
458  /* Advance PC for the next instruction */
459  decoded_inst->advancePC(fetch_info.pc);
460 
461  /* Predict any branches and issue a branch if
462  * necessary */
463  predictBranch(dyn_inst, prediction);
464  } else {
465  DPRINTF(Fetch, "Inst not ready yet\n");
466  }
467 
468  /* Step on the pointer into the line if there's no
469  * complete instruction waiting */
470  if (decoder->needMoreBytes()) {
471  fetch_info.inputIndex += decoder->moreBytesSize();
472 
473  DPRINTF(Fetch, "Updated inputIndex value PC: %s"
474  " inputIndex: 0x%x lineBaseAddr: 0x%x lineWidth: 0x%x\n",
475  line_in->pc, fetch_info.inputIndex, line_in->lineBaseAddr,
476  line_in->lineWidth);
477  }
478  }
479 
480  if (dyn_inst) {
481  /* Step to next sequence number */
482  fetch_info.fetchSeqNum++;
483 
484  /* Correctly size the output before writing */
485  if (output_index == 0) {
486  insts_out.resize(outputWidth);
487  }
488  /* Pack the generated dynamic instruction into the output */
489  insts_out.insts[output_index] = dyn_inst;
490  output_index++;
491 
492  /* Output MinorTrace instruction info for
493  * pre-microop decomposition macroops */
494  if (debug::MinorTrace && !dyn_inst->isFault() &&
495  dyn_inst->staticInst->isMacroop())
496  {
497  dyn_inst->minorTraceInst(*this,
498  cpu.threads[0]->getIsaPtr()->regClasses());
499  }
500  }
501 
502  /* Remember the streamSeqNum of this line so we can tell when
503  * we change stream */
504  fetch_info.lastStreamSeqNum = line_in->id.streamSeqNum;
505 
506  /* Asked to discard line or there was a branch or fault */
507  if (!prediction.isBubble() || /* The remains of a
508  line with a prediction in it */
509  line_in->isFault() /* A line which is just a fault */)
510  {
511  DPRINTF(Fetch, "Discarding all input on branch/fault\n");
512  dumpAllInput(tid);
513  fetch_info.havePC = false;
514  line_in = NULL;
515  } else if (discard_line) {
516  /* Just discard one line, one's behind it may have new
517  * stream sequence numbers. There's a DPRINTF above
518  * for this event */
519  popInput(tid);
520  fetch_info.havePC = false;
521  line_in = NULL;
522  } else if (fetch_info.inputIndex == line_in->lineWidth) {
523  /* Got to end of a line, pop the line but keep PC
524  * in case this is a line-wrapping inst. */
525  popInput(tid);
526  line_in = NULL;
527  }
528 
529  if (!line_in && processMoreThanOneInput) {
530  DPRINTF(Fetch, "Wrapping\n");
531  line_in = getInput(tid);
532  }
533  }
534 
535  /* The rest of the output (if any) should already have been packed
536  * with bubble instructions by insts_out's initialisation */
537  }
538  if (tid == InvalidThreadID) {
539  assert(insts_out.isBubble());
540  }
542  *predictionOut.inputWire = prediction;
543 
544  /* If we generated output, reserve space for the result in the next stage
545  * and mark the stage as being active this cycle */
546  if (!insts_out.isBubble()) {
547  /* Note activity of following buffer */
549  insts_out.threadId = tid;
550  nextStageReserve[tid].reserve();
551  }
552 
553  /* If we still have input to process and somewhere to put it,
554  * mark stage as active */
555  for (ThreadID i = 0; i < cpu.numThreads; i++)
556  {
557  if (getInput(i) && nextStageReserve[i].canReserve()) {
559  break;
560  }
561  }
562 
563  /* Make sure the input (if any left) is pushed */
564  if (!inp.outputWire->isBubble())
565  inputBuffer[inp.outputWire->id.threadId].pushTail();
566 }
567 
568 inline ThreadID
570 {
571  /* Select thread via policy. */
572  std::vector<ThreadID> priority_list;
573 
574  switch (cpu.threadPolicy) {
575  case enums::SingleThreaded:
576  priority_list.push_back(0);
577  break;
578  case enums::RoundRobin:
579  priority_list = cpu.roundRobinPriority(threadPriority);
580  break;
581  case enums::Random:
582  priority_list = cpu.randomPriority();
583  break;
584  default:
585  panic("Unknown fetch policy");
586  }
587 
588  for (auto tid : priority_list) {
589  if (getInput(tid) && !fetchInfo[tid].blocked) {
590  threadPriority = tid;
591  return tid;
592  }
593  }
594 
595  return InvalidThreadID;
596 }
597 
598 bool
600 {
601  for (const auto &buffer : inputBuffer) {
602  if (!buffer.empty())
603  return false;
604  }
605 
606  return (*inp.outputWire).isBubble() &&
607  (*predictionOut.inputWire).isBubble();
608 }
609 
611  : statistics::Group(cpu, "fetch2"),
612  ADD_STAT(intInstructions, statistics::units::Count::get(),
613  "Number of integer instructions successfully decoded"),
614  ADD_STAT(fpInstructions, statistics::units::Count::get(),
615  "Number of floating point instructions successfully decoded"),
616  ADD_STAT(vecInstructions, statistics::units::Count::get(),
617  "Number of SIMD instructions successfully decoded"),
618  ADD_STAT(loadInstructions, statistics::units::Count::get(),
619  "Number of memory load instructions successfully decoded"),
620  ADD_STAT(storeInstructions, statistics::units::Count::get(),
621  "Number of memory store instructions successfully decoded"),
622  ADD_STAT(amoInstructions, statistics::units::Count::get(),
623  "Number of memory atomic instructions successfully decoded")
624 {
637 }
638 
639 void
641 {
642  std::ostringstream data;
643 
644  if (fetchInfo[0].blocked)
645  data << 'B';
646  else
647  (*out.inputWire).reportData(data);
648 
649  minor::minorTrace("inputIndex=%d havePC=%d predictionSeqNum=%d insts=%s\n",
650  fetchInfo[0].inputIndex, fetchInfo[0].havePC,
651  fetchInfo[0].predictionSeqNum, data.str());
652  inputBuffer[0].minorTrace();
653 }
654 
655 } // namespace minor
656 } // namespace gem5
gem5::minor::ForwardLineData
Line fetch data in the forward direction.
Definition: pipe_data.hh:175
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::branch_prediction::BPredUnit::update
void update(const InstSeqNum &done_sn, ThreadID tid)
Tells the branch predictor to commit any updates until the given sequence number.
Definition: bpred_unit.cc:305
gem5::MinorCPU::randomPriority
std::vector< ThreadID > randomPriority()
Definition: cpu.hh:182
gem5::minor::ForwardLineData::id
InstId id
Thread, stream, prediction ...
Definition: pipe_data.hh:199
gem5::minor::ForwardInstData::isBubble
bool isBubble() const
BubbleIF interface.
Definition: pipe_data.cc:251
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::minor::ForwardInstData::insts
MinorDynInstPtr insts[MAX_FORWARD_INSTS]
Array of carried insts, ref counted.
Definition: pipe_data.hh:261
gem5::minor::ForwardInstData::threadId
ThreadID threadId
Thread associated with these instructions.
Definition: pipe_data.hh:267
gem5::auxv::Random
@ Random
Definition: aux_vector.hh:89
gem5::minor::Fetch2::Fetch2ThreadInfo::lastStreamSeqNum
InstSeqNum lastStreamSeqNum
Stream sequence number of the last seen line used to identify changes of instruction stream.
Definition: fetch2.hh:150
gem5::minor::BranchData::reason
Reason reason
Explanation for this branch.
Definition: pipe_data.hh:113
gem5::minor::Fetch2::Fetch2ThreadInfo
Data members after this line are cycle-to-cycle state.
Definition: fetch2.hh:105
sc_dt::to_string
const std::string to_string(sc_enc enc)
Definition: sc_fxdefs.cc:91
gem5::minor::Fetch2::processMoreThanOneInput
bool processMoreThanOneInput
If true, more than one input word can be processed each cycle if there is room in the output to conta...
Definition: fetch2.hh:93
minor
gem5::MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:85
gem5::minor::ForwardLineData::lineWidth
unsigned int lineWidth
Explicit line width, don't rely on data.size.
Definition: pipe_data.hh:191
gem5::minor::Fetch2::minorTrace
void minorTrace() const
Definition: fetch2.cc:640
std::vector
STL vector class.
Definition: stl.hh:37
gem5::minor::BranchData::NoBranch
@ NoBranch
Definition: pipe_data.hh:74
gem5::minor::Fetch2::Fetch2Stats::loadInstructions
statistics::Scalar loadInstructions
Definition: fetch2.hh:181
gem5::minor::ForwardInstData
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
Definition: pipe_data.hh:257
gem5::minor::Fetch2::updateBranchPrediction
void updateBranchPrediction(const BranchData &branch)
Update local branch prediction structures from feedback from Execute.
Definition: fetch2.cc:130
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::minor::Fetch2::Fetch2ThreadInfo::inputIndex
unsigned int inputIndex
Index into an incompletely processed input line that instructions are to be extracted from.
Definition: fetch2.hh:132
gem5::minor::BranchData::isStreamChange
static bool isStreamChange(const BranchData::Reason reason)
Is a request with this reason actually a request to change the PC rather than a bubble or branch pred...
Definition: pipe_data.cc:85
gem5::ThreadContext::getDecoderPtr
virtual TheISA::Decoder * getDecoderPtr()=0
gem5::minor::Fetch2::branchPredictor
branch_prediction::BPredUnit & branchPredictor
Branch predictor passed from Python configuration.
Definition: fetch2.hh:96
gem5::RefCountingPtr< MinorDynInst >
gem5::MinorCPU::threads
std::vector< minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
Definition: cpu.hh:101
gem5::minor::Fetch2::inp
Latch< ForwardLineData >::Output inp
Input port carrying lines from Fetch1.
Definition: fetch2.hh:73
gem5::minor::InputBuffer
Like a Queue but with a restricted interface and a setTail function which, when the queue is empty,...
Definition: buffers.hh:572
gem5::minor::Fetch2::predictionOut
Latch< BranchData >::Input predictionOut
Output port carrying predictions back to Fetch1.
Definition: fetch2.hh:80
gem5::Named
Interface for things with names.
Definition: named.hh:38
fetch2.hh
gem5::BaseCPU::numThreads
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:368
gem5::StaticInst::isFloating
bool isFloating() const
Definition: static_inst.hh:179
gem5::minor::Latch::Output
Definition: buffers.hh:263
gem5::minor::Fetch2::getInput
const ForwardLineData * getInput(ThreadID tid)
Get a piece of data to work on from the inputBuffer, or 0 if there is no data.
Definition: fetch2.cc:98
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::minor::BranchData::Interrupt
@ Interrupt
Definition: pipe_data.hh:97
gem5::minor::Fetch2::Fetch2Stats::vecInstructions
statistics::Scalar vecInstructions
Definition: fetch2.hh:180
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::minor::Fetch2::branchInp
Latch< BranchData >::Output branchInp
Input port carrying branches from Execute.
Definition: fetch2.hh:77
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::StaticInst::isAtomic
bool isAtomic() const
Definition: static_inst.hh:171
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::minor::BranchData::CorrectlyPredictedBranch
@ CorrectlyPredictedBranch
Definition: pipe_data.hh:77
gem5::minor::Latch::Input
Encapsulate wires on either input or output of the latch.
Definition: buffers.hh:252
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::minor::InstId::streamSeqNum
InstSeqNum streamSeqNum
The 'stream' this instruction belongs to.
Definition: dyn_inst.hh:94
gem5::minor::Fetch2::Fetch2ThreadInfo::predictionSeqNum
InstSeqNum predictionSeqNum
Fetch2 is the source of prediction sequence numbers.
Definition: fetch2.hh:165
gem5::minor::BranchData::BadlyPredictedBranchTarget
@ BadlyPredictedBranchTarget
Definition: pipe_data.hh:86
pipeline.hh
gem5::minor::Fetch2::fetchInfo
std::vector< Fetch2ThreadInfo > fetchInfo
Definition: fetch2.hh:171
gem5::StaticInst::isLoad
bool isLoad() const
Definition: static_inst.hh:169
gem5::minor::ForwardLineData::line
uint8_t * line
Line data.
Definition: pipe_data.hh:203
gem5::StaticInst::isStore
bool isStore() const
Definition: static_inst.hh:170
gem5::InvalidThreadID
const ThreadID InvalidThreadID
Definition: types.hh:243
gem5::StaticInst::isVector
bool isVector() const
Definition: static_inst.hh:180
gem5::minor::BranchData
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
Definition: pipe_data.hh:66
gem5::minor::Fetch2::Fetch2Stats::intInstructions
statistics::Scalar intInstructions
Stats.
Definition: fetch2.hh:178
gem5::minor::Fetch2::dumpAllInput
void dumpAllInput(ThreadID tid)
Dump the whole contents of the input buffer.
Definition: fetch2.cc:120
gem5::branch_prediction::BPredUnit::squash
void squash(const InstSeqNum &squashed_sn, ThreadID tid)
Squashes all outstanding updates until a given sequence number.
Definition: bpred_unit.cc:328
gem5::minor::BranchData::target
TheISA::PCState target
Starting PC of that stream.
Definition: pipe_data.hh:123
gem5::BaseCPU::getContext
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
Definition: base.hh:290
gem5::minor::Pipeline::Fetch2StageId
@ Fetch2StageId
Definition: pipeline.hh:104
null_static_inst.hh
gem5::minor::Fetch2::threadPriority
ThreadID threadPriority
Definition: fetch2.hh:172
gem5::minor::BranchData::inst
MinorDynInstPtr inst
Instruction which caused this branch.
Definition: pipe_data.hh:126
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::minor::BranchData::isBubble
bool isBubble() const
Definition: pipe_data.hh:152
gem5::minor::Fetch2::evaluate
void evaluate()
Pass on input/buffer data to the output if you can.
Definition: fetch2.cc:243
name
const std::string & name()
Definition: trace.cc:49
gem5::minor::minorTrace
void minorTrace(const char *fmt, Args ...args)
DPRINTFN for MinorTrace reporting.
Definition: trace.hh:67
gem5::minor::Fetch2::isDrained
bool isDrained()
Is this stage drained? For Fetch2, draining is initiated by Execute halting Fetch1 causing Fetch2 to ...
Definition: fetch2.cc:599
gem5::minor::ForwardLineData::isFault
bool isFault() const
This is a fault, not a line.
Definition: pipe_data.hh:224
gem5::minor::Fetch2::inputBuffer
std::vector< InputBuffer< ForwardLineData > > inputBuffer
Definition: fetch2.hh:100
gem5::ActivityRecorder::activity
void activity()
Records that there is activity this cycle.
Definition: activity.cc:55
gem5::minor::Fetch2::popInput
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
Definition: fetch2.cc:109
gem5::minor::Fetch2::cpu
MinorCPU & cpu
Pointer back to the containing CPU.
Definition: fetch2.hh:70
gem5::minor::Fetch2::Fetch2Stats::amoInstructions
statistics::Scalar amoInstructions
Definition: fetch2.hh:183
gem5::ActivityRecorder::activateStage
void activateStage(const int idx)
Marks a stage as active.
Definition: activity.cc:91
gem5::minor::ForwardInstData::resize
void resize(unsigned int width)
Resize a bubble/empty ForwardInstData and fill with bubbles.
Definition: pipe_data.cc:264
gem5::minor::Fetch2::Fetch2Stats::Fetch2Stats
Fetch2Stats(MinorCPU *cpu)
Definition: fetch2.cc:610
gem5::minor::MinorDynInst
Dynamic instruction for Minor.
Definition: dyn_inst.hh:163
gem5::minor::BranchData::threadId
ThreadID threadId
ThreadID associated with branch.
Definition: pipe_data.hh:116
bpred_unit.hh
gem5::SparcISA::Branch
Base class for branch operations.
Definition: branch.hh:48
gem5::minor::Fetch2::out
Latch< ForwardInstData >::Input out
Output port carrying instructions into Decode.
Definition: fetch2.hh:83
gem5::minor::BranchData::HaltFetch
@ HaltFetch
Definition: pipe_data.hh:99
gem5::minor::Fetch2::Fetch2
Fetch2(const std::string &name, MinorCPU &cpu_, const MinorCPUParams &params, Latch< ForwardLineData >::Output inp_, Latch< BranchData >::Output branchInp_, Latch< BranchData >::Input predictionOut_, Latch< ForwardInstData >::Input out_, std::vector< InputBuffer< ForwardInstData >> &next_stage_input_buffer)
Definition: fetch2.cc:59
gem5::minor::Fetch2::Fetch2ThreadInfo::pc
TheISA::PCState pc
Remembered program counter value.
Definition: fetch2.hh:141
gem5::minor::Fetch2::Fetch2ThreadInfo::havePC
bool havePC
PC is currently valid.
Definition: fetch2.hh:146
gem5::minor::BranchData::BranchPrediction
@ BranchPrediction
Definition: pipe_data.hh:84
logging.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::StaticInst::isInteger
bool isInteger() const
Definition: static_inst.hh:178
gem5::minor::ForwardLineData::lineBaseAddr
Addr lineBaseAddr
First byte address in the line.
Definition: pipe_data.hh:185
gem5::minor::BranchData::BadlyPredictedBranch
@ BadlyPredictedBranch
Definition: pipe_data.hh:90
gem5::minor::ForwardLineData::fault
Fault fault
This line has a fault.
Definition: pipe_data.hh:196
gem5::minor::Fetch2::Fetch2ThreadInfo::expectedStreamSeqNum
InstSeqNum expectedStreamSeqNum
Stream sequence number remembered from last time the predictionSeqNum changed.
Definition: fetch2.hh:160
gem5::MinorCPU::threadPolicy
enums::ThreadPolicy threadPolicy
Thread Scheduling Policy (RoundRobin, Random, etc)
Definition: cpu.hh:120
trace.hh
gem5::MinorCPU::activityRecorder
minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Definition: cpu.hh:96
decoder
output decoder
Definition: nop.cc:61
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:355
gem5::minor::Fetch2::stats
gem5::minor::Fetch2::Fetch2Stats stats
gem5::minor::Fetch2::Fetch2ThreadInfo::fetchSeqNum
InstSeqNum fetchSeqNum
Fetch2 is the source of fetch sequence numbers.
Definition: fetch2.hh:154
gem5::minor::BranchData::SuspendThread
@ SuspendThread
Definition: pipe_data.hh:95
gem5::minor::Fetch2::Fetch2Stats::fpInstructions
statistics::Scalar fpInstructions
Definition: fetch2.hh:179
gem5::minor::ForwardLineData::pc
TheISA::PCState pc
PC of the first requested inst within this line.
Definition: pipe_data.hh:188
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
gem5::minor::InstId::predictionSeqNum
InstSeqNum predictionSeqNum
The predicted qualifier to stream, attached by Fetch2 as a consequence of branch prediction.
Definition: dyn_inst.hh:98
gem5::minor::Fetch2::Fetch2Stats::storeInstructions
statistics::Scalar storeInstructions
Definition: fetch2.hh:182
gem5::minor::BranchData::UnpredictedBranch
@ UnpredictedBranch
Definition: pipe_data.hh:82
gem5::minor::Fetch2::nextStageReserve
std::vector< InputBuffer< ForwardInstData > > & nextStageReserve
Interface to reserve space in the next stage.
Definition: fetch2.hh:86
gem5::StaticInst::advancePC
virtual void advancePC(TheISA::PCState &pc_state) const =0
gem5::MinorCPU::roundRobinPriority
std::vector< ThreadID > roundRobinPriority(ThreadID priority)
Thread scheduling utility functions.
Definition: cpu.hh:173
gem5::branch_prediction::BPredUnit::predict
bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, TheISA::PCState &pc, ThreadID tid)
Predicts whether or not the instruction is a taken branch, and the target of the branch if it is take...
Definition: bpred_unit.cc:130
gem5::minor::Fetch2::getScheduledThread
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to fetch from.
Definition: fetch2.cc:569
gem5::minor::Fetch2::Fetch2ThreadInfo::blocked
bool blocked
Blocked indication for report.
Definition: fetch2.hh:168
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::minor::Fetch2::outputWidth
unsigned int outputWidth
Width of output of this stage/input of next in instructions.
Definition: fetch2.hh:89
gem5::minor::InstId::threadId
ThreadID threadId
The thread to which this line/instruction belongs.
Definition: dyn_inst.hh:89
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::minor::Fetch2::predictBranch
void predictBranch(MinorDynInstPtr inst, BranchData &branch)
Predicts branches for the given instruction.
Definition: fetch2.cc:192

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