gem5  v21.2.1.1
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gem5::MinorCPU Class Reference

MinorCPU is an in-order CPU model with four fixed pipeline stages: More...

#include <cpu.hh>

Inheritance diagram for gem5::MinorCPU:

Classes

class  MinorCPUPort
 Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Execute. More...
 

Public Member Functions

 MinorCPU (const MinorCPUParams &params)
 
 ~MinorCPU ()
 
void init () override
 Starting, waking and initialisation. More...
 
void startup () override
 
void wakeup (ThreadID tid) override
 
void regStats () override
 Stats interface from SimObject (by way of BaseCPU) More...
 
Counter totalInsts () const override
 Simple inst count interface from BaseCPU. More...
 
Counter totalOps () const override
 
void serializeThread (CheckpointOut &cp, ThreadID tid) const override
 
void unserializeThread (CheckpointIn &cp, ThreadID tid) override
 
void serialize (CheckpointOut &cp) const override
 Serialize pipeline data. More...
 
void unserialize (CheckpointIn &cp) override
 
DrainState drain () override
 Drain interface. More...
 
void drainResume () override
 
void signalDrainDone ()
 Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState. More...
 
void memWriteback () override
 
void switchOut () override
 Switching interface from BaseCPU. More...
 
void takeOverFrom (BaseCPU *old_cpu) override
 
void activateContext (ThreadID thread_id) override
 Thread activation interface from BaseCPU. More...
 
void suspendContext (ThreadID thread_id) override
 
std::vector< ThreadIDroundRobinPriority (ThreadID priority)
 Thread scheduling utility functions. More...
 
std::vector< ThreadIDrandomPriority ()
 
void tick ()
 The tick method in the MinorCPU is simply updating the cycle counters as the ticking of the pipeline stages is already handled by the Pipeline object. More...
 
void wakeupOnEvent (unsigned int stage_id)
 Interface for stages to signal that they have become active after a callback or eventq event where the pipeline itself may have already been idled. More...
 

Public Attributes

minor::MinorActivityRecorderactivityRecorder
 Activity recording for pipeline. More...
 
std::vector< minor::MinorThread * > threads
 These are thread state-representing objects for this CPU. More...
 
enums::ThreadPolicy threadPolicy
 Thread Scheduling Policy (RoundRobin, Random, etc) More...
 
minor::MinorStats stats
 Processor-specific statistics. More...
 
EventFunctionWrapperfetchEventWrapper
 

Protected Member Functions

PortgetDataPort () override
 Return a reference to the data port. More...
 
PortgetInstPort () override
 Return a reference to the instruction port. More...
 

Protected Attributes

minor::Pipelinepipeline
 pipeline is a container for the clockable pipeline stage objects. More...
 

Detailed Description

MinorCPU is an in-order CPU model with four fixed pipeline stages:

Fetch1 - fetches lines from memory Fetch2 - decomposes lines into macro-op instructions Decode - decomposes macro-ops into micro-ops Execute - executes those micro-ops

This pipeline is carried in the MinorCPU::pipeline object. The exec_context interface is not carried by MinorCPU but by minor::ExecContext objects created by minor::Execute.

Definition at line 85 of file cpu.hh.

Constructor & Destructor Documentation

◆ MinorCPU()

gem5::MinorCPU::MinorCPU ( const MinorCPUParams &  params)

◆ ~MinorCPU()

gem5::MinorCPU::~MinorCPU ( )

Definition at line 85 of file cpu.cc.

References fetchEventWrapper, pipeline, and threads.

Member Function Documentation

◆ activateContext()

void gem5::MinorCPU::activateContext ( ThreadID  thread_id)
override

Thread activation interface from BaseCPU.

Definition at line 252 of file cpu.cc.

References gem5::minor::Pipeline::CPUStageId, DPRINTF, fetchEventWrapper, gem5::minor::MinorStats::quiesceCycles, stats, threads, and wakeupOnEvent().

◆ drain()

DrainState gem5::MinorCPU::drain ( )
override

Drain interface.

Definition at line 165 of file cpu.cc.

References DPRINTF, gem5::Drained, and gem5::Draining.

◆ drainResume()

void gem5::MinorCPU::drainResume ( )
override

Definition at line 196 of file cpu.cc.

References DPRINTF, fatal, gem5::X86ISA::system, and wakeup().

◆ getDataPort()

Port & gem5::MinorCPU::getDataPort ( )
overrideprotected

Return a reference to the data port.

Definition at line 307 of file cpu.cc.

◆ getInstPort()

Port & gem5::MinorCPU::getInstPort ( )
overrideprotected

Return a reference to the instruction port.

Definition at line 301 of file cpu.cc.

◆ init()

void gem5::MinorCPU::init ( )
override

Starting, waking and initialisation.

Definition at line 98 of file cpu.cc.

References fatal, gem5::statistics::init, and gem5::X86ISA::system.

◆ memWriteback()

void gem5::MinorCPU::memWriteback ( )
override

Definition at line 226 of file cpu.cc.

References DPRINTF.

◆ randomPriority()

std::vector<ThreadID> gem5::MinorCPU::randomPriority ( )
inline

◆ regStats()

void gem5::MinorCPU::regStats ( )
override

Stats interface from SimObject (by way of BaseCPU)

Definition at line 110 of file cpu.cc.

◆ roundRobinPriority()

std::vector<ThreadID> gem5::MinorCPU::roundRobinPriority ( ThreadID  priority)
inline

◆ serialize()

void gem5::MinorCPU::serialize ( CheckpointOut cp) const
override

Serialize pipeline data.

Definition at line 129 of file cpu.cc.

References gem5::serialize().

◆ serializeThread()

void gem5::MinorCPU::serializeThread ( CheckpointOut cp,
ThreadID  tid 
) const
override

Definition at line 117 of file cpu.cc.

References threads.

◆ signalDrainDone()

void gem5::MinorCPU::signalDrainDone ( )

Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState.

Definition at line 189 of file cpu.cc.

References DPRINTF, and gem5::Drainable::signalDrainDone().

Referenced by gem5::minor::Pipeline::evaluate().

◆ startup()

void gem5::MinorCPU::startup ( )
override

Definition at line 154 of file cpu.cc.

References DPRINTF.

◆ suspendContext()

void gem5::MinorCPU::suspendContext ( ThreadID  thread_id)
override

Definition at line 281 of file cpu.cc.

References DPRINTF, and threads.

◆ switchOut()

void gem5::MinorCPU::switchOut ( )
override

Switching interface from BaseCPU.

Definition at line 232 of file cpu.cc.

References activityRecorder, DPRINTF, and gem5::ActivityRecorder::reset().

◆ takeOverFrom()

void gem5::MinorCPU::takeOverFrom ( BaseCPU *  old_cpu)
override

Definition at line 244 of file cpu.cc.

References DPRINTF, and gem5::takeOverFrom().

◆ tick()

void gem5::MinorCPU::tick ( )
inline

The tick method in the MinorCPU is simply updating the cycle counters as the ticking of the pipeline stages is already handled by the Pipeline object.

Definition at line 199 of file cpu.hh.

Referenced by gem5::minor::Pipeline::evaluate().

◆ totalInsts()

Counter gem5::MinorCPU::totalInsts ( ) const
override

Simple inst count interface from BaseCPU.

Definition at line 313 of file cpu.cc.

References gem5::ArmISA::i, and threads.

◆ totalOps()

Counter gem5::MinorCPU::totalOps ( ) const
override

Definition at line 324 of file cpu.cc.

References gem5::ArmISA::i, and threads.

◆ unserialize()

void gem5::MinorCPU::unserialize ( CheckpointIn cp)
override

Definition at line 136 of file cpu.cc.

References gem5::unserialize().

◆ unserializeThread()

void gem5::MinorCPU::unserializeThread ( CheckpointIn cp,
ThreadID  tid 
)
override

Definition at line 123 of file cpu.cc.

References threads.

◆ wakeup()

void gem5::MinorCPU::wakeup ( ThreadID  tid)
override

◆ wakeupOnEvent()

void gem5::MinorCPU::wakeupOnEvent ( unsigned int  stage_id)

Interface for stages to signal that they have become active after a callback or eventq event where the pipeline itself may have already been idled.

The stage argument should be from the enumeration Pipeline::StageId

Definition at line 291 of file cpu.cc.

References gem5::ActivityRecorder::activateStage(), activityRecorder, and DPRINTF.

Referenced by activateContext(), gem5::minor::Execute::drain(), gem5::minor::Execute::drainResume(), gem5::minor::Execute::evaluate(), gem5::minor::Fetch1::evaluate(), gem5::minor::Fetch1::recvTimingResp(), gem5::minor::LSQ::recvTimingResp(), gem5::minor::Fetch1::tryToSendToTransfers(), and gem5::minor::Fetch1::wakeupFetch().

Member Data Documentation

◆ activityRecorder

minor::MinorActivityRecorder* gem5::MinorCPU::activityRecorder

Activity recording for pipeline.

This belongs to Pipeline but stages will access it through the CPU as the MinorCPU object actually mediates idling behaviour

Definition at line 96 of file cpu.hh.

Referenced by gem5::minor::Decode::evaluate(), gem5::minor::Fetch2::evaluate(), gem5::minor::Execute::evaluate(), gem5::minor::Fetch1::evaluate(), gem5::minor::Execute::issue(), MinorCPU(), switchOut(), and wakeupOnEvent().

◆ fetchEventWrapper

EventFunctionWrapper* gem5::MinorCPU::fetchEventWrapper

Definition at line 206 of file cpu.hh.

Referenced by activateContext(), MinorCPU(), and ~MinorCPU().

◆ pipeline

minor::Pipeline* gem5::MinorCPU::pipeline
protected

pipeline is a container for the clockable pipeline stage objects.

Elements of pipeline call TheISA to implement the model.

Definition at line 90 of file cpu.hh.

Referenced by ~MinorCPU().

◆ stats

minor::MinorStats gem5::MinorCPU::stats

◆ threadPolicy

enums::ThreadPolicy gem5::MinorCPU::threadPolicy

◆ threads

std::vector<minor::MinorThread *> gem5::MinorCPU::threads

The documentation for this class was generated from the following files:

Generated on Wed May 4 2022 12:14:40 for gem5 by doxygen 1.8.17