gem5  v21.1.0.2
floating.hh
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28 
29 #ifndef __ARCH_POWER_INSTS_FLOATING_HH__
30 #define __ARCH_POWER_INSTS_FLOATING_HH__
31 
33 #include "base/bitfield.hh"
34 #include "base/cprintf.hh"
35 
36 namespace gem5
37 {
38 
39 namespace PowerISA
40 {
41 
45 class FloatOp : public PowerStaticInst
46 {
47  protected:
48 
49  bool rc;
50 
52  FloatOp(const char *mnem, MachInst _machInst, OpClass __opClass)
53  : PowerStaticInst(mnem, _machInst, __opClass),
54  rc(machInst.rc)
55  {
56  }
57 
58  // Test for NaN (maximum biased exponent & non-zero fraction)
59  inline bool
60  isNan(uint32_t val_bits) const
61  {
62  return ((bits(val_bits, 30, 23) == 0xFF) && bits(val_bits, 22, 0));
63  }
64 
65  inline bool
66  isNan(uint64_t val_bits) const
67  {
68  return ((bits(val_bits, 62, 52) == 0x7FF) && bits(val_bits, 51, 0));
69  }
70 
71  inline bool
72  isNan(float val) const
73  {
74  void *val_ptr = &val;
75  uint32_t val_bits = *(uint32_t *) val_ptr;
76  return isNan(val_bits);
77  }
78 
79  inline bool
80  isNan(double val) const
81  {
82  void *val_ptr = &val;
83  uint64_t val_bits = *(uint64_t *) val_ptr;
84  return isNan(val_bits);
85  }
86 
87  // Test for SNaN (NaN with high order bit of fraction set to 0)
88  inline bool
89  isSnan(uint32_t val_bits) const
90  {
91  return ((bits(val_bits, 30, 22) == 0x1FE) && bits(val_bits, 22, 0));
92  }
93 
94  // Test for QNaN (NaN with high order bit of fraction set to 1)
95  inline bool
96  isQnan(uint32_t val_bits) const
97  {
98  return (bits(val_bits, 30, 22) == 0x1FF);
99  }
100 
101  // Test for infinity (maximum biased exponent and zero fraction)
102  inline bool
103  isInfinity(uint32_t val_bits) const
104  {
105  return ((bits(val_bits, 30, 23) == 0xFF) && !bits(val_bits, 22, 0));
106  }
107 
108  // Test for normalized numbers (biased exponent in the range 1 to 254)
109  inline bool
110  isNormalized(uint32_t val_bits) const
111  {
112  return ((bits(val_bits, 30, 23) != 0xFF) && bits(val_bits, 22, 0));
113  }
114 
115  // Test for denormalized numbers (biased exponent of zero and
116  // non-zero fraction)
117  inline bool
118  isDenormalized(uint32_t val_bits) const
119  {
120  return (!bits(val_bits, 30, 23) && bits(val_bits, 22, 0));
121  }
122 
123  // Test for zero (biased exponent of zero and fraction of zero)
124  inline bool
125  isZero(uint32_t val_bits) const
126  {
127  return (!bits(val_bits, 30, 23) && !bits(val_bits, 22, 0));
128  }
129 
130  // Test for negative
131  inline bool
132  isNegative(uint32_t val_bits) const
133  {
134  return (bits(val_bits, 31));
135  }
136 
137  // Compute the CR field
138  inline uint32_t
139  makeCRField(double a, double b) const
140  {
141  uint32_t c = 0;
142  if (isNan(a) || isNan(b)) { c = 0x1; }
143  else if (a < b) { c = 0x8; }
144  else if (a > b) { c = 0x4; }
145  else { c = 0x2; }
146  return c;
147  }
148 
149  std::string generateDisassembly(
150  Addr pc, const loader::SymbolTable *symtab) const override;
151 };
152 
153 } // namespace PowerISA
154 } // namespace gem5
155 
156 #endif //__ARCH_POWER_INSTS_FLOATING_HH__
gem5::PowerISA::PowerStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:45
gem5::PowerISA::FloatOp
Base class for floating point operations.
Definition: floating.hh:45
gem5::PowerISA::FloatOp::isZero
bool isZero(uint32_t val_bits) const
Definition: floating.hh:125
gem5::PowerISA::FloatOp::isQnan
bool isQnan(uint32_t val_bits) const
Definition: floating.hh:96
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
gem5::PowerISA::FloatOp::makeCRField
uint32_t makeCRField(double a, double b) const
Definition: floating.hh:139
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::PowerISA::FloatOp::isNegative
bool isNegative(uint32_t val_bits) const
Definition: floating.hh:132
gem5::PowerISA::FloatOp::isDenormalized
bool isDenormalized(uint32_t val_bits) const
Definition: floating.hh:118
gem5::PowerISA::FloatOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: floating.cc:37
gem5::PowerISA::FloatOp::isNan
bool isNan(uint64_t val_bits) const
Definition: floating.hh:66
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:381
bitfield.hh
gem5::PowerISA::FloatOp::rc
bool rc
Definition: floating.hh:49
gem5::PowerISA::FloatOp::isSnan
bool isSnan(uint32_t val_bits) const
Definition: floating.hh:89
cprintf.hh
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::PowerISA::FloatOp::isNan
bool isNan(float val) const
Definition: floating.hh:72
gem5::ArmISA::c
Bitfield< 29 > c
Definition: misc_types.hh:53
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PowerISA::FloatOp::isNan
bool isNan(double val) const
Definition: floating.hh:80
gem5::PowerISA::MachInst
uint32_t MachInst
Definition: types.hh:44
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::PowerISA::FloatOp::FloatOp
FloatOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: floating.hh:52
gem5::PowerISA::FloatOp::isNan
bool isNan(uint32_t val_bits) const
Definition: floating.hh:60
gem5::PowerISA::FloatOp::isNormalized
bool isNormalized(uint32_t val_bits) const
Definition: floating.hh:110
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
static_inst.hh
gem5::PowerISA::PowerStaticInst
Definition: static_inst.hh:42
gem5::PowerISA::FloatOp::isInfinity
bool isInfinity(uint32_t val_bits) const
Definition: floating.hh:103

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