gem5  v21.1.0.2
gpu_compute_driver.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2018 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * For use for simulation and test purposes only
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  * this list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright notice,
14  * this list of conditions and the following disclaimer in the documentation
15  * and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  * contributors may be used to endorse or promote products derived from this
19  * software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
42 #ifndef __GPU_COMPUTE_GPU_COMPUTE_DRIVER_HH__
43 #define __GPU_COMPUTE_GPU_COMPUTE_DRIVER_HH__
44 
45 #include <cassert>
46 #include <cstdint>
47 #include <set>
48 #include <unordered_map>
49 
50 #include "base/addr_range_map.hh"
51 #include "base/types.hh"
52 #include "enums/GfxVersion.hh"
53 #include "mem/request.hh"
54 #include "sim/emul_driver.hh"
55 
56 namespace gem5
57 {
58 
59 struct GPUComputeDriverParams;
60 class GPUCommandProcessor;
61 class PortProxy;
62 class ThreadContext;
63 
64 class GPUComputeDriver final : public EmulatedDriver
65 {
66  public:
67  typedef GPUComputeDriverParams Params;
68  GPUComputeDriver(const Params &p);
69  int ioctl(ThreadContext *tc, unsigned req, Addr ioc_buf) override;
70 
71  int open(ThreadContext *tc, int mode, int flags) override;
72  Addr mmap(ThreadContext *tc, Addr start, uint64_t length,
73  int prot, int tgt_flags, int tgt_fd, off_t offset) override;
74  virtual void signalWakeupEvent(uint32_t event_id);
75  void sleepCPU(ThreadContext *tc, uint32_t milliSecTimeout);
85  void setMtype(RequestPtr req);
86 
87  int
89  {
90  switch (gfxVersion) {
91  case GfxVersion::gfx801:
92  case GfxVersion::gfx803:
93  case GfxVersion::gfx902:
94  return 4;
95  case GfxVersion::gfx900:
96  // gfx900 supports large BAR, so it has a larger doorbell
97  return 8;
98  default:
99  fatal("Invalid GPU type\n");
100  }
101  return 4;
102  }
103 
104  class DriverWakeupEvent : public Event
105  {
106  public:
108  ThreadContext *thrd_cntxt)
109  : driver(gpu_driver), tc(thrd_cntxt) {}
110  void process() override;
111  const char *description() const override;
112  void scheduleWakeup(Tick wakeup_delay);
113  private:
116  };
117 
119  {
120  public:
122  mailBoxPtr(0), tc(nullptr), threadWaiting(false), setEvent(false)
123  {}
124  // Mail box pointer for this address. Current implementation does not
125  // use this mailBoxPtr to notify events but directly calls
126  // signalWakeupEvent from dispatcher (GPU) to notifiy events. So,
127  // currently this mailBoxPtr is not used. But a future implementation
128  // may communicate to the driver using mailBoxPtr.
130  // Thread context waiting on this even. We do not support multiple
131  // threads waiting on an event currently.
133  // threadWaiting = true, if some thread context is waiting on this
134  // event. A thread context waiting on this event is put to sleep.
136  // setEvent = true, if this event is triggered but when this event
137  // triggered, no thread context was waiting on it. In the future, some
138  // thread context will try to wait on this event but since event has
139  // already happened, we will not allow that thread context to go to
140  // sleep. The above mentioned scneario can happen when the waiting
141  // thread and wakeup thread race on this event and the wakeup thread
142  // beat the waiting thread at the driver.
143  bool setEvent;
144  };
145  typedef class EventTableEntry ETEntry;
146 
147  private:
152  uint32_t queueId;
153  bool isdGPU;
154  GfxVersion gfxVersion;
157  uint32_t eventSlotIndex;
158  //Event table that keeps track of events. It is indexed with event ID.
159  std::unordered_map<uint32_t, ETEntry> ETable;
160 
165 
170  {
171  SHARED = 0,
173  CACHED = 2
174  };
175 
177 
178  // TCEvents map keeps trak of the events that can wakeup this thread. When
179  // multiple events can wake up this thread, this data structure helps to
180  // reset all events when one of those events wake up this thread. the
181  // signal events that can wake up this thread are stored in signalEvents
182  // whereas the timer wakeup event is stored in timerEvent.
183  class EventList
184  {
185  public:
186  EventList() : driver(nullptr), timerEvent(nullptr, nullptr) {}
187  EventList(GPUComputeDriver *gpu_driver, ThreadContext *thrd_cntxt)
188  : driver(gpu_driver), timerEvent(gpu_driver, thrd_cntxt)
189  { }
190  void clearEvents() {
191  assert(driver);
192  for (auto event : signalEvents) {
193  assert(event < driver->eventSlotIndex);
194  driver->ETable[event].tc = nullptr;
195  driver->ETable[event].threadWaiting = false;
196  }
197  signalEvents.clear();
198  if (timerEvent.scheduled()) {
200  }
201  }
204  // The set of events that can wake up the same thread.
205  std::set<uint32_t> signalEvents;
206  };
207  std::unordered_map<ThreadContext *, EventList> TCEvents;
208 
213  void registerUncacheableMemory(Addr start, Addr length);
214 
230  Addr gpuVmApeBase(int gpuNum) const;
231  Addr gpuVmApeLimit(Addr apeBase) const;
232  Addr scratchApeBase(int gpuNum) const;
233  Addr scratchApeBaseV9() const;
234  Addr scratchApeLimit(Addr apeBase) const;
235  Addr ldsApeBase(int gpuNum) const;
236  Addr ldsApeBaseV9() const;
237  Addr ldsApeLimit(Addr apeBase) const;
238 
246  Addr length);
247  Addr deallocateGpuVma(Addr start);
248 
249  void allocateQueue(PortProxy &mem_proxy, Addr ioc_buf_addr);
250 
251 };
252 
253 } // namespace gem5
254 
255 #endif // __GPU_COMPUTE_GPU_COMPUTE_DRIVER_HH__
gem5::GPUComputeDriver::registerUncacheableMemory
void registerUncacheableMemory(Addr start, Addr length)
Register a region of host memory as uncacheable from the perspective of the dGPU.
gem5::GPUComputeDriver::ETEntry
class EventTableEntry ETEntry
Definition: gpu_compute_driver.hh:145
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::GPUComputeDriver::TCEvents
std::unordered_map< ThreadContext *, EventList > TCEvents
Definition: gpu_compute_driver.hh:207
gem5::GPUComputeDriver::signalWakeupEvent
virtual void signalWakeupEvent(uint32_t event_id)
Definition: gpu_compute_driver.cc:184
gem5::GPUComputeDriver::EventTableEntry::tc
ThreadContext * tc
Definition: gpu_compute_driver.hh:132
gem5::GPUComputeDriver::gpuVmas
AddrRangeMap< Request::CacheCoherenceFlags, 1 > gpuVmas
VMA structures for GPUVM memory.
Definition: gpu_compute_driver.hh:164
gem5::GPUComputeDriver::allocateQueue
void allocateQueue(PortProxy &mem_proxy, Addr ioc_buf_addr)
Forward relevant parameters to packet processor; queueId is used to link doorbell.
Definition: gpu_compute_driver.cc:152
gem5::AddrRangeMap
The AddrRangeMap uses an STL map to implement an interval tree for address decoding.
Definition: addr_range_map.hh:62
gem5::GPUComputeDriver::DriverWakeupEvent::driver
GPUComputeDriver * driver
Definition: gpu_compute_driver.hh:114
gem5::GPUComputeDriver::deallocateGpuVma
Addr deallocateGpuVma(Addr start)
Definition: gpu_compute_driver.cc:997
gem5::GPUComputeDriver::EventTableEntry::threadWaiting
bool threadWaiting
Definition: gpu_compute_driver.hh:135
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::GPUComputeDriver::READ_WRITE
@ READ_WRITE
Definition: gpu_compute_driver.hh:172
gem5::GPUComputeDriver::gpuVmApeLimit
Addr gpuVmApeLimit(Addr apeBase) const
Definition: gpu_compute_driver.cc:939
gem5::GPUComputeDriver::EventTableEntry::mailBoxPtr
Addr mailBoxPtr
Definition: gpu_compute_driver.hh:129
gem5::GPUComputeDriver::allocateGpuVma
void allocateGpuVma(Request::CacheCoherenceFlags mtype, Addr start, Addr length)
Allocate/deallocate GPUVM VMAs for tracking virtual address allocations and properties on DGPUs.
Definition: gpu_compute_driver.cc:985
request.hh
gem5::GPUComputeDriver::eventSlotIndex
uint32_t eventSlotIndex
Definition: gpu_compute_driver.hh:157
gem5::GPUComputeDriver::setMtype
void setMtype(RequestPtr req)
Called by the compute units right before a request is issued to ruby.
Definition: gpu_compute_driver.cc:1010
gem5::GPUComputeDriver::ETable
std::unordered_map< uint32_t, ETEntry > ETable
Definition: gpu_compute_driver.hh:159
gem5::Flags< CacheCoherenceFlagsType >
gem5::GPUComputeDriver::EventList::driver
GPUComputeDriver * driver
Definition: gpu_compute_driver.hh:202
gem5::GPUComputeDriver::CACHED
@ CACHED
Definition: gpu_compute_driver.hh:173
gem5::GPUComputeDriver::sleepCPU
void sleepCPU(ThreadContext *tc, uint32_t milliSecTimeout)
Definition: gpu_compute_driver.cc:921
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::GPUCommandProcessor
Definition: gpu_command_processor.hh:71
gem5::GPUComputeDriver::defaultMtype
Request::CacheCoherenceFlags defaultMtype
Definition: gpu_compute_driver.hh:176
addr_range_map.hh
gem5::GPUComputeDriver::EventTableEntry::EventTableEntry
EventTableEntry()
Definition: gpu_compute_driver.hh:121
gem5::GPUComputeDriver::queueId
uint32_t queueId
Definition: gpu_compute_driver.hh:152
gem5::Event
Definition: eventq.hh:251
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::GPUComputeDriver::ldsApeBaseV9
Addr ldsApeBaseV9() const
Definition: gpu_compute_driver.cc:973
gem5::GPUComputeDriver::EventList::signalEvents
std::set< uint32_t > signalEvents
Definition: gpu_compute_driver.hh:205
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
gem5::GPUComputeDriver::scratchApeBase
Addr scratchApeBase(int gpuNum) const
Definition: gpu_compute_driver.cc:945
gem5::GPUComputeDriver::GPUComputeDriver
GPUComputeDriver(const Params &p)
Definition: gpu_compute_driver.cc:57
gem5::GPUComputeDriver::EventList::clearEvents
void clearEvents()
Definition: gpu_compute_driver.hh:190
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GPUComputeDriver::open
int open(ThreadContext *tc, int mode, int flags) override
Create an FD entry for the KFD inside of the owning process.
Definition: gpu_compute_driver.cc:87
gem5::GPUComputeDriver::scratchApeBaseV9
Addr scratchApeBaseV9() const
Definition: gpu_compute_driver.cc:953
gem5::GPUComputeDriver::dGPUPoolID
int dGPUPoolID
Definition: gpu_compute_driver.hh:155
gem5::GPUComputeDriver::doorbellSize
int doorbellSize()
Definition: gpu_compute_driver.hh:88
gem5::GPUComputeDriver::DriverWakeupEvent::tc
ThreadContext * tc
Definition: gpu_compute_driver.hh:115
gem5::EventManager::deschedule
void deschedule(Event &event)
Definition: eventq.hh:1028
gem5::GPUComputeDriver::DriverWakeupEvent
Definition: gpu_compute_driver.hh:104
gem5::EmulatedDriver
EmulatedDriver is an abstract base class for fake SE-mode device drivers.
Definition: emul_driver.hh:55
gem5::GPUComputeDriver::MtypeFlags
MtypeFlags
Mtype bits {Cached, Read Write, Shared} for caches.
Definition: gpu_compute_driver.hh:169
gem5::GPUComputeDriver::ioctl
int ioctl(ThreadContext *tc, unsigned req, Addr ioc_buf) override
Abstract method, invoked when the user program calls ioctl() on the file descriptor returned by a pre...
Definition: gpu_compute_driver.cc:222
gem5::GPUComputeDriver::DriverWakeupEvent::scheduleWakeup
void scheduleWakeup(Tick wakeup_delay)
Definition: gpu_compute_driver.cc:177
gem5::GPUComputeDriver::EventList::EventList
EventList()
Definition: gpu_compute_driver.hh:186
gem5::GPUComputeDriver::device
GPUCommandProcessor * device
GPU that is controlled by this driver.
Definition: gpu_compute_driver.hh:151
types.hh
gem5::GPUComputeDriver::isdGPU
bool isdGPU
Definition: gpu_compute_driver.hh:153
gem5::GPUComputeDriver::SHARED
@ SHARED
Definition: gpu_compute_driver.hh:171
gem5::GPUComputeDriver
Definition: gpu_compute_driver.hh:64
gem5::GPUComputeDriver::mmap
Addr mmap(ThreadContext *tc, Addr start, uint64_t length, int prot, int tgt_flags, int tgt_fd, off_t offset) override
Currently, mmap() will simply setup a mapping for the associated device's packet processor's doorbell...
Definition: gpu_compute_driver.cc:101
emul_driver.hh
gem5::GPUComputeDriver::EventList
Definition: gpu_compute_driver.hh:183
gem5::GPUComputeDriver::EventTableEntry
Definition: gpu_compute_driver.hh:118
gem5::GPUComputeDriver::Params
GPUComputeDriverParams Params
Definition: gpu_compute_driver.hh:67
gem5::GPUComputeDriver::EventList::timerEvent
DriverWakeupEvent timerEvent
Definition: gpu_compute_driver.hh:203
gem5::GPUComputeDriver::DriverWakeupEvent::process
void process() override
Definition: gpu_compute_driver.cc:211
gem5::GPUComputeDriver::ldsApeLimit
Addr ldsApeLimit(Addr apeBase) const
Definition: gpu_compute_driver.cc:979
gem5::GPUComputeDriver::EventTableEntry::setEvent
bool setEvent
Definition: gpu_compute_driver.hh:143
gem5::GPUComputeDriver::DriverWakeupEvent::description
const char * description() const override
Return a C string describing the event.
Definition: gpu_compute_driver.cc:78
gem5::GPUComputeDriver::EventList::EventList
EventList(GPUComputeDriver *gpu_driver, ThreadContext *thrd_cntxt)
Definition: gpu_compute_driver.hh:187
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::GPUComputeDriver::gpuVmApeBase
Addr gpuVmApeBase(int gpuNum) const
The aperture (APE) base/limit pairs are set statically at startup by the real KFD.
Definition: gpu_compute_driver.cc:933
gem5::GPUComputeDriver::scratchApeLimit
Addr scratchApeLimit(Addr apeBase) const
Definition: gpu_compute_driver.cc:959
gem5::GPUComputeDriver::ldsApeBase
Addr ldsApeBase(int gpuNum) const
Definition: gpu_compute_driver.cc:965
gem5::GPUComputeDriver::DriverWakeupEvent::DriverWakeupEvent
DriverWakeupEvent(GPUComputeDriver *gpu_driver, ThreadContext *thrd_cntxt)
Definition: gpu_compute_driver.hh:107
gem5::GPUComputeDriver::gfxVersion
GfxVersion gfxVersion
Definition: gpu_compute_driver.hh:154
gem5::X86ISA::prot
Bitfield< 7 > prot
Definition: misc.hh:588
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::GPUComputeDriver::eventPage
Addr eventPage
Definition: gpu_compute_driver.hh:156

Generated on Tue Sep 21 2021 12:25:23 for gem5 by doxygen 1.8.17