gem5  v21.2.1.1
gpu_compute_driver.hh
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31 
40 #ifndef __GPU_COMPUTE_GPU_COMPUTE_DRIVER_HH__
41 #define __GPU_COMPUTE_GPU_COMPUTE_DRIVER_HH__
42 
43 #include <cassert>
44 #include <cstdint>
45 #include <set>
46 #include <unordered_map>
47 
48 #include "base/addr_range_map.hh"
49 #include "base/types.hh"
50 #include "enums/GfxVersion.hh"
51 #include "mem/request.hh"
52 #include "sim/emul_driver.hh"
53 
54 namespace gem5
55 {
56 
57 struct GPUComputeDriverParams;
58 class GPUCommandProcessor;
59 class PortProxy;
60 class ThreadContext;
61 
62 class GPUComputeDriver final : public EmulatedDriver
63 {
64  public:
65  typedef GPUComputeDriverParams Params;
66  GPUComputeDriver(const Params &p);
67  int ioctl(ThreadContext *tc, unsigned req, Addr ioc_buf) override;
68 
69  int open(ThreadContext *tc, int mode, int flags) override;
70  Addr mmap(ThreadContext *tc, Addr start, uint64_t length,
71  int prot, int tgt_flags, int tgt_fd, off_t offset) override;
72  virtual void signalWakeupEvent(uint32_t event_id);
73  void sleepCPU(ThreadContext *tc, uint32_t milliSecTimeout);
83  void setMtype(RequestPtr req);
84 
85  int
87  {
88  switch (gfxVersion) {
89  case GfxVersion::gfx801:
90  case GfxVersion::gfx803:
91  case GfxVersion::gfx902:
92  return 4;
93  case GfxVersion::gfx900:
94  // gfx900 supports large BAR, so it has a larger doorbell
95  return 8;
96  default:
97  fatal("Invalid GPU type\n");
98  }
99  return 4;
100  }
101 
102  class DriverWakeupEvent : public Event
103  {
104  public:
106  ThreadContext *thrd_cntxt)
107  : driver(gpu_driver), tc(thrd_cntxt) {}
108  void process() override;
109  const char *description() const override;
110  void scheduleWakeup(Tick wakeup_delay);
111  private:
114  };
115 
117  {
118  public:
120  mailBoxPtr(0), tc(nullptr), threadWaiting(false), setEvent(false)
121  {}
122  // Mail box pointer for this address. Current implementation does not
123  // use this mailBoxPtr to notify events but directly calls
124  // signalWakeupEvent from dispatcher (GPU) to notifiy events. So,
125  // currently this mailBoxPtr is not used. But a future implementation
126  // may communicate to the driver using mailBoxPtr.
128  // Thread context waiting on this even. We do not support multiple
129  // threads waiting on an event currently.
131  // threadWaiting = true, if some thread context is waiting on this
132  // event. A thread context waiting on this event is put to sleep.
134  // setEvent = true, if this event is triggered but when this event
135  // triggered, no thread context was waiting on it. In the future, some
136  // thread context will try to wait on this event but since event has
137  // already happened, we will not allow that thread context to go to
138  // sleep. The above mentioned scneario can happen when the waiting
139  // thread and wakeup thread race on this event and the wakeup thread
140  // beat the waiting thread at the driver.
141  bool setEvent;
142  };
143  typedef class EventTableEntry ETEntry;
144 
145  private:
150  uint32_t queueId;
151  bool isdGPU;
152  GfxVersion gfxVersion;
155  uint32_t eventSlotIndex;
156  //Event table that keeps track of events. It is indexed with event ID.
157  std::unordered_map<uint32_t, ETEntry> ETable;
158 
163 
168  {
169  SHARED = 0,
171  CACHED = 2
172  };
173 
175 
176  // TCEvents map keeps trak of the events that can wakeup this thread. When
177  // multiple events can wake up this thread, this data structure helps to
178  // reset all events when one of those events wake up this thread. the
179  // signal events that can wake up this thread are stored in signalEvents
180  // whereas the timer wakeup event is stored in timerEvent.
181  class EventList
182  {
183  public:
184  EventList() : driver(nullptr), timerEvent(nullptr, nullptr) {}
185  EventList(GPUComputeDriver *gpu_driver, ThreadContext *thrd_cntxt)
186  : driver(gpu_driver), timerEvent(gpu_driver, thrd_cntxt)
187  { }
188  void clearEvents() {
189  assert(driver);
190  for (auto event : signalEvents) {
191  assert(event < driver->eventSlotIndex);
192  driver->ETable[event].tc = nullptr;
193  driver->ETable[event].threadWaiting = false;
194  }
195  signalEvents.clear();
196  if (timerEvent.scheduled()) {
198  }
199  }
202  // The set of events that can wake up the same thread.
203  std::set<uint32_t> signalEvents;
204  };
205  std::unordered_map<ThreadContext *, EventList> TCEvents;
206 
211  void registerUncacheableMemory(Addr start, Addr length);
212 
228  Addr gpuVmApeBase(int gpuNum) const;
229  Addr gpuVmApeLimit(Addr apeBase) const;
230  Addr scratchApeBase(int gpuNum) const;
231  Addr scratchApeBaseV9() const;
232  Addr scratchApeLimit(Addr apeBase) const;
233  Addr ldsApeBase(int gpuNum) const;
234  Addr ldsApeBaseV9() const;
235  Addr ldsApeLimit(Addr apeBase) const;
236 
244  Addr length);
245  Addr deallocateGpuVma(Addr start);
246 
247  void allocateQueue(PortProxy &mem_proxy, Addr ioc_buf_addr);
248 
249 };
250 
251 } // namespace gem5
252 
253 #endif // __GPU_COMPUTE_GPU_COMPUTE_DRIVER_HH__
gem5::GPUComputeDriver::registerUncacheableMemory
void registerUncacheableMemory(Addr start, Addr length)
Register a region of host memory as uncacheable from the perspective of the dGPU.
gem5::GPUComputeDriver::ETEntry
class EventTableEntry ETEntry
Definition: gpu_compute_driver.hh:143
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::GPUComputeDriver::TCEvents
std::unordered_map< ThreadContext *, EventList > TCEvents
Definition: gpu_compute_driver.hh:205
gem5::GPUComputeDriver::signalWakeupEvent
virtual void signalWakeupEvent(uint32_t event_id)
Definition: gpu_compute_driver.cc:187
gem5::GPUComputeDriver::EventTableEntry::tc
ThreadContext * tc
Definition: gpu_compute_driver.hh:130
gem5::GPUComputeDriver::gpuVmas
AddrRangeMap< Request::CacheCoherenceFlags, 1 > gpuVmas
VMA structures for GPUVM memory.
Definition: gpu_compute_driver.hh:162
gem5::GPUComputeDriver::allocateQueue
void allocateQueue(PortProxy &mem_proxy, Addr ioc_buf_addr)
Forward relevant parameters to packet processor; queueId is used to link doorbell.
Definition: gpu_compute_driver.cc:155
gem5::AddrRangeMap
The AddrRangeMap uses an STL map to implement an interval tree for address decoding.
Definition: addr_range_map.hh:62
gem5::GPUComputeDriver::DriverWakeupEvent::driver
GPUComputeDriver * driver
Definition: gpu_compute_driver.hh:112
gem5::GPUComputeDriver::deallocateGpuVma
Addr deallocateGpuVma(Addr start)
Definition: gpu_compute_driver.cc:1003
gem5::GPUComputeDriver::EventTableEntry::threadWaiting
bool threadWaiting
Definition: gpu_compute_driver.hh:133
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::GPUComputeDriver::READ_WRITE
@ READ_WRITE
Definition: gpu_compute_driver.hh:170
gem5::GPUComputeDriver::gpuVmApeLimit
Addr gpuVmApeLimit(Addr apeBase) const
Definition: gpu_compute_driver.cc:945
gem5::GPUComputeDriver::EventTableEntry::mailBoxPtr
Addr mailBoxPtr
Definition: gpu_compute_driver.hh:127
gem5::GPUComputeDriver::allocateGpuVma
void allocateGpuVma(Request::CacheCoherenceFlags mtype, Addr start, Addr length)
Allocate/deallocate GPUVM VMAs for tracking virtual address allocations and properties on DGPUs.
Definition: gpu_compute_driver.cc:991
request.hh
gem5::GPUComputeDriver::eventSlotIndex
uint32_t eventSlotIndex
Definition: gpu_compute_driver.hh:155
gem5::GPUComputeDriver::setMtype
void setMtype(RequestPtr req)
Called by the compute units right before a request is issued to ruby.
Definition: gpu_compute_driver.cc:1016
gem5::GPUComputeDriver::ETable
std::unordered_map< uint32_t, ETEntry > ETable
Definition: gpu_compute_driver.hh:157
gem5::Flags< CacheCoherenceFlagsType >
gem5::GPUComputeDriver::EventList::driver
GPUComputeDriver * driver
Definition: gpu_compute_driver.hh:200
gem5::GPUComputeDriver::CACHED
@ CACHED
Definition: gpu_compute_driver.hh:171
gem5::GPUComputeDriver::sleepCPU
void sleepCPU(ThreadContext *tc, uint32_t milliSecTimeout)
Definition: gpu_compute_driver.cc:927
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::GPUCommandProcessor
Definition: gpu_command_processor.hh:69
gem5::GPUComputeDriver::defaultMtype
Request::CacheCoherenceFlags defaultMtype
Definition: gpu_compute_driver.hh:174
addr_range_map.hh
gem5::GPUComputeDriver::EventTableEntry::EventTableEntry
EventTableEntry()
Definition: gpu_compute_driver.hh:119
gem5::GPUComputeDriver::queueId
uint32_t queueId
Definition: gpu_compute_driver.hh:150
gem5::Event
Definition: eventq.hh:251
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::GPUComputeDriver::ldsApeBaseV9
Addr ldsApeBaseV9() const
Definition: gpu_compute_driver.cc:979
gem5::GPUComputeDriver::EventList::signalEvents
std::set< uint32_t > signalEvents
Definition: gpu_compute_driver.hh:203
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
gem5::GPUComputeDriver::scratchApeBase
Addr scratchApeBase(int gpuNum) const
Definition: gpu_compute_driver.cc:951
gem5::GPUComputeDriver::GPUComputeDriver
GPUComputeDriver(const Params &p)
Definition: gpu_compute_driver.cc:60
gem5::GPUComputeDriver::EventList::clearEvents
void clearEvents()
Definition: gpu_compute_driver.hh:188
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GPUComputeDriver::open
int open(ThreadContext *tc, int mode, int flags) override
Create an FD entry for the KFD inside of the owning process.
Definition: gpu_compute_driver.cc:90
gem5::GPUComputeDriver::scratchApeBaseV9
Addr scratchApeBaseV9() const
Definition: gpu_compute_driver.cc:959
gem5::GPUComputeDriver::dGPUPoolID
int dGPUPoolID
Definition: gpu_compute_driver.hh:153
gem5::GPUComputeDriver::doorbellSize
int doorbellSize()
Definition: gpu_compute_driver.hh:86
gem5::GPUComputeDriver::DriverWakeupEvent::tc
ThreadContext * tc
Definition: gpu_compute_driver.hh:113
gem5::EventManager::deschedule
void deschedule(Event &event)
Definition: eventq.hh:1028
gem5::GPUComputeDriver::DriverWakeupEvent
Definition: gpu_compute_driver.hh:102
gem5::EmulatedDriver
EmulatedDriver is an abstract base class for fake SE-mode device drivers.
Definition: emul_driver.hh:55
gem5::GPUComputeDriver::MtypeFlags
MtypeFlags
Mtype bits {Cached, Read Write, Shared} for caches.
Definition: gpu_compute_driver.hh:167
gem5::GPUComputeDriver::ioctl
int ioctl(ThreadContext *tc, unsigned req, Addr ioc_buf) override
Abstract method, invoked when the user program calls ioctl() on the file descriptor returned by a pre...
Definition: gpu_compute_driver.cc:225
gem5::GPUComputeDriver::DriverWakeupEvent::scheduleWakeup
void scheduleWakeup(Tick wakeup_delay)
Definition: gpu_compute_driver.cc:180
gem5::GPUComputeDriver::EventList::EventList
EventList()
Definition: gpu_compute_driver.hh:184
gem5::GPUComputeDriver::device
GPUCommandProcessor * device
GPU that is controlled by this driver.
Definition: gpu_compute_driver.hh:149
types.hh
gem5::GPUComputeDriver::isdGPU
bool isdGPU
Definition: gpu_compute_driver.hh:151
gem5::GPUComputeDriver::SHARED
@ SHARED
Definition: gpu_compute_driver.hh:169
gem5::GPUComputeDriver
Definition: gpu_compute_driver.hh:62
gem5::GPUComputeDriver::mmap
Addr mmap(ThreadContext *tc, Addr start, uint64_t length, int prot, int tgt_flags, int tgt_fd, off_t offset) override
Currently, mmap() will simply setup a mapping for the associated device's packet processor's doorbell...
Definition: gpu_compute_driver.cc:104
emul_driver.hh
gem5::GPUComputeDriver::EventList
Definition: gpu_compute_driver.hh:181
gem5::GPUComputeDriver::EventTableEntry
Definition: gpu_compute_driver.hh:116
gem5::GPUComputeDriver::Params
GPUComputeDriverParams Params
Definition: gpu_compute_driver.hh:65
gem5::GPUComputeDriver::EventList::timerEvent
DriverWakeupEvent timerEvent
Definition: gpu_compute_driver.hh:201
gem5::GPUComputeDriver::DriverWakeupEvent::process
void process() override
Definition: gpu_compute_driver.cc:214
gem5::GPUComputeDriver::ldsApeLimit
Addr ldsApeLimit(Addr apeBase) const
Definition: gpu_compute_driver.cc:985
gem5::GPUComputeDriver::EventTableEntry::setEvent
bool setEvent
Definition: gpu_compute_driver.hh:141
gem5::GPUComputeDriver::DriverWakeupEvent::description
const char * description() const override
Return a C string describing the event.
Definition: gpu_compute_driver.cc:81
gem5::GPUComputeDriver::EventList::EventList
EventList(GPUComputeDriver *gpu_driver, ThreadContext *thrd_cntxt)
Definition: gpu_compute_driver.hh:185
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::GPUComputeDriver::gpuVmApeBase
Addr gpuVmApeBase(int gpuNum) const
The aperture (APE) base/limit pairs are set statically at startup by the real KFD.
Definition: gpu_compute_driver.cc:939
gem5::GPUComputeDriver::scratchApeLimit
Addr scratchApeLimit(Addr apeBase) const
Definition: gpu_compute_driver.cc:965
gem5::GPUComputeDriver::ldsApeBase
Addr ldsApeBase(int gpuNum) const
Definition: gpu_compute_driver.cc:971
gem5::GPUComputeDriver::DriverWakeupEvent::DriverWakeupEvent
DriverWakeupEvent(GPUComputeDriver *gpu_driver, ThreadContext *thrd_cntxt)
Definition: gpu_compute_driver.hh:105
gem5::GPUComputeDriver::gfxVersion
GfxVersion gfxVersion
Definition: gpu_compute_driver.hh:152
gem5::X86ISA::prot
Bitfield< 7 > prot
Definition: misc.hh:588
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::GPUComputeDriver::eventPage
Addr eventPage
Definition: gpu_compute_driver.hh:154

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