#include "base/bitfield.hh"
#include "base/compiler.hh"

Go to the source code of this file.

Classes
struct	gem5::igbreg::RxDesc

struct	gem5::igbreg::TxDesc

struct	gem5::igbreg::Regs

struct	gem5::igbreg::Regs::Reg< T >

struct	gem5::igbreg::Regs::CTRL

struct	gem5::igbreg::Regs::STATUS

struct	gem5::igbreg::Regs::EECD

struct	gem5::igbreg::Regs::EERD

struct	gem5::igbreg::Regs::CTRL_EXT

struct	gem5::igbreg::Regs::MDIC

struct	gem5::igbreg::Regs::ICR

struct	gem5::igbreg::Regs::ITR

struct	gem5::igbreg::Regs::RCTL

struct	gem5::igbreg::Regs::FCTTV

struct	gem5::igbreg::Regs::TCTL

struct	gem5::igbreg::Regs::PBA

struct	gem5::igbreg::Regs::FCRTL

struct	gem5::igbreg::Regs::FCRTH

struct	gem5::igbreg::Regs::RDBA

struct	gem5::igbreg::Regs::RDLEN

struct	gem5::igbreg::Regs::SRRCTL

struct	gem5::igbreg::Regs::RDH

struct	gem5::igbreg::Regs::RDT

struct	gem5::igbreg::Regs::RDTR

struct	gem5::igbreg::Regs::RXDCTL

struct	gem5::igbreg::Regs::RADV

struct	gem5::igbreg::Regs::RSRPD

struct	gem5::igbreg::Regs::TDBA

struct	gem5::igbreg::Regs::TDLEN

struct	gem5::igbreg::Regs::TDH

struct	gem5::igbreg::Regs::TXDCA_CTL

struct	gem5::igbreg::Regs::TDT

struct	gem5::igbreg::Regs::TIDV

struct	gem5::igbreg::Regs::TXDCTL

struct	gem5::igbreg::Regs::TADV

struct	gem5::igbreg::Regs::RXCSUM

struct	gem5::igbreg::Regs::RFCTL

struct	gem5::igbreg::Regs::MANC

struct	gem5::igbreg::Regs::SWSM

struct	gem5::igbreg::Regs::FWSM

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.

namespace	gem5::igbreg

namespace	gem5::igbreg::txd_op

Macros
#define	ADD_FIELD32(NAME, OFFSET, BITS)

#define	ADD_FIELD64(NAME, OFFSET, BITS)

Enumerations
enum	gem5::igbreg::IntTypes { gem5::igbreg::IT_NONE = 0x00000 , gem5::igbreg::IT_TXDW = 0x00001 , gem5::igbreg::IT_TXQE = 0x00002 , gem5::igbreg::IT_LSC = 0x00004 , gem5::igbreg::IT_RXSEQ = 0x00008 , gem5::igbreg::IT_RXDMT = 0x00010 , gem5::igbreg::IT_RXO = 0x00040 , gem5::igbreg::IT_RXT = 0x00080 , gem5::igbreg::IT_MADC = 0x00200 , gem5::igbreg::IT_RXCFG = 0x00400 , gem5::igbreg::IT_GPI0 = 0x02000 , gem5::igbreg::IT_GPI1 = 0x04000 , gem5::igbreg::IT_TXDLOW = 0x08000 , gem5::igbreg::IT_SRPD = 0x10000 , gem5::igbreg::IT_ACK = 0x20000 }

Functions
bool	gem5::igbreg::txd_op::isLegacy (TxDesc *d)

uint8_t	gem5::igbreg::txd_op::getType (TxDesc *d)

bool	gem5::igbreg::txd_op::isType (TxDesc *d, uint8_t type)

bool	gem5::igbreg::txd_op::isTypes (TxDesc *d, uint8_t t1, uint8_t t2)

bool	gem5::igbreg::txd_op::isAdvDesc (TxDesc *d)

bool	gem5::igbreg::txd_op::isContext (TxDesc *d)

bool	gem5::igbreg::txd_op::isData (TxDesc *d)

Addr	gem5::igbreg::txd_op::getBuf (TxDesc *d)

Addr	gem5::igbreg::txd_op::getLen (TxDesc *d)

void	gem5::igbreg::txd_op::setDd (TxDesc *d)

bool	gem5::igbreg::txd_op::ide (TxDesc *d)

bool	gem5::igbreg::txd_op::vle (TxDesc *d)

bool	gem5::igbreg::txd_op::rs (TxDesc *d)

bool	gem5::igbreg::txd_op::ic (TxDesc *d)

bool	gem5::igbreg::txd_op::tse (TxDesc *d)

bool	gem5::igbreg::txd_op::ifcs (TxDesc *d)

bool	gem5::igbreg::txd_op::eop (TxDesc *d)

bool	gem5::igbreg::txd_op::ip (TxDesc *d)

bool	gem5::igbreg::txd_op::tcp (TxDesc *d)

uint8_t	gem5::igbreg::txd_op::getCso (TxDesc *d)

uint8_t	gem5::igbreg::txd_op::getCss (TxDesc *d)

bool	gem5::igbreg::txd_op::ixsm (TxDesc *d)

bool	gem5::igbreg::txd_op::txsm (TxDesc *d)

int	gem5::igbreg::txd_op::tucse (TxDesc *d)

int	gem5::igbreg::txd_op::tucso (TxDesc *d)

int	gem5::igbreg::txd_op::tucss (TxDesc *d)

int	gem5::igbreg::txd_op::ipcse (TxDesc *d)

int	gem5::igbreg::txd_op::ipcso (TxDesc *d)

int	gem5::igbreg::txd_op::ipcss (TxDesc *d)

int	gem5::igbreg::txd_op::mss (TxDesc *d)

int	gem5::igbreg::txd_op::hdrlen (TxDesc *d)

int	gem5::igbreg::txd_op::getTsoLen (TxDesc *d)

int	gem5::igbreg::txd_op::utcmd (TxDesc *d)

Variables
const uint32_t	gem5::igbreg::REG_CTRL = 0x00000

const uint32_t	gem5::igbreg::REG_STATUS = 0x00008

const uint32_t	gem5::igbreg::REG_EECD = 0x00010

const uint32_t	gem5::igbreg::REG_EERD = 0x00014

const uint32_t	gem5::igbreg::REG_CTRL_EXT = 0x00018

const uint32_t	gem5::igbreg::REG_MDIC = 0x00020

const uint32_t	gem5::igbreg::REG_FCAL = 0x00028

const uint32_t	gem5::igbreg::REG_FCAH = 0x0002C

const uint32_t	gem5::igbreg::REG_FCT = 0x00030

const uint32_t	gem5::igbreg::REG_VET = 0x00038

const uint32_t	gem5::igbreg::REG_PBA = 0x01000

const uint32_t	gem5::igbreg::REG_ICR = 0x000C0

const uint32_t	gem5::igbreg::REG_ITR = 0x000C4

const uint32_t	gem5::igbreg::REG_ICS = 0x000C8

const uint32_t	gem5::igbreg::REG_IMS = 0x000D0

const uint32_t	gem5::igbreg::REG_IMC = 0x000D8

const uint32_t	gem5::igbreg::REG_IAM = 0x000E0

const uint32_t	gem5::igbreg::REG_RCTL = 0x00100

const uint32_t	gem5::igbreg::REG_FCTTV = 0x00170

const uint32_t	gem5::igbreg::REG_TIPG = 0x00410

const uint32_t	gem5::igbreg::REG_AIFS = 0x00458

const uint32_t	gem5::igbreg::REG_LEDCTL = 0x00e00

const uint32_t	gem5::igbreg::REG_EICR = 0x01580

const uint32_t	gem5::igbreg::REG_IVAR0 = 0x01700

const uint32_t	gem5::igbreg::REG_FCRTL = 0x02160

const uint32_t	gem5::igbreg::REG_FCRTH = 0x02168

const uint32_t	gem5::igbreg::REG_RDBAL = 0x02800

const uint32_t	gem5::igbreg::REG_RDBAH = 0x02804

const uint32_t	gem5::igbreg::REG_RDLEN = 0x02808

const uint32_t	gem5::igbreg::REG_SRRCTL = 0x0280C

const uint32_t	gem5::igbreg::REG_RDH = 0x02810

const uint32_t	gem5::igbreg::REG_RDT = 0x02818

const uint32_t	gem5::igbreg::REG_RDTR = 0x02820

const uint32_t	gem5::igbreg::REG_RXDCTL = 0x02828

const uint32_t	gem5::igbreg::REG_RADV = 0x0282C

const uint32_t	gem5::igbreg::REG_TCTL = 0x00400

const uint32_t	gem5::igbreg::REG_TDBAL = 0x03800

const uint32_t	gem5::igbreg::REG_TDBAH = 0x03804

const uint32_t	gem5::igbreg::REG_TDLEN = 0x03808

const uint32_t	gem5::igbreg::REG_TDH = 0x03810

const uint32_t	gem5::igbreg::REG_TXDCA_CTL = 0x03814

const uint32_t	gem5::igbreg::REG_TDT = 0x03818

const uint32_t	gem5::igbreg::REG_TIDV = 0x03820

const uint32_t	gem5::igbreg::REG_TXDCTL = 0x03828

const uint32_t	gem5::igbreg::REG_TADV = 0x0382C

const uint32_t	gem5::igbreg::REG_TDWBAL = 0x03838

const uint32_t	gem5::igbreg::REG_TDWBAH = 0x0383C

const uint32_t	gem5::igbreg::REG_CRCERRS = 0x04000

const uint32_t	gem5::igbreg::REG_RXCSUM = 0x05000

const uint32_t	gem5::igbreg::REG_RLPML = 0x05004

const uint32_t	gem5::igbreg::REG_RFCTL = 0x05008

const uint32_t	gem5::igbreg::REG_MTA = 0x05200

const uint32_t	gem5::igbreg::REG_RAL = 0x05400

const uint32_t	gem5::igbreg::REG_RAH = 0x05404

const uint32_t	gem5::igbreg::REG_VFTA = 0x05600

const uint32_t	gem5::igbreg::REG_WUC = 0x05800

const uint32_t	gem5::igbreg::REG_WUFC = 0x05808

const uint32_t	gem5::igbreg::REG_WUS = 0x05810

const uint32_t	gem5::igbreg::REG_MANC = 0x05820

const uint32_t	gem5::igbreg::REG_SWSM = 0x05B50

const uint32_t	gem5::igbreg::REG_FWSM = 0x05B54

const uint32_t	gem5::igbreg::REG_SWFWSYNC = 0x05B5C

const uint8_t	gem5::igbreg::EEPROM_READ_OPCODE_SPI = 0x03

const uint8_t	gem5::igbreg::EEPROM_RDSR_OPCODE_SPI = 0x05

const uint8_t	gem5::igbreg::EEPROM_SIZE = 64

const uint16_t	gem5::igbreg::EEPROM_CSUM = 0xBABA

const uint8_t	gem5::igbreg::VLAN_FILTER_TABLE_SIZE = 128

const uint8_t	gem5::igbreg::RCV_ADDRESS_TABLE_SIZE = 24

const uint8_t	gem5::igbreg::MULTICAST_TABLE_SIZE = 128

const uint32_t	gem5::igbreg::STATS_REGS_SIZE = 0x228

const uint8_t	gem5::igbreg::PHY_PSTATUS = 0x1

const uint8_t	gem5::igbreg::PHY_PID = 0x2

const uint8_t	gem5::igbreg::PHY_EPID = 0x3

const uint8_t	gem5::igbreg::PHY_GSTATUS = 10

const uint8_t	gem5::igbreg::PHY_EPSTATUS = 15

const uint8_t	gem5::igbreg::PHY_AGC = 18

const uint16_t	gem5::igbreg::RXDS_DYNINT = 0x800

const uint16_t	gem5::igbreg::RXDS_UDPV = 0x400

const uint16_t	gem5::igbreg::RXDS_CRCV = 0x100

const uint16_t	gem5::igbreg::RXDS_PIF = 0x080

const uint16_t	gem5::igbreg::RXDS_IPCS = 0x040

const uint16_t	gem5::igbreg::RXDS_TCPCS = 0x020

const uint16_t	gem5::igbreg::RXDS_UDPCS = 0x010

const uint16_t	gem5::igbreg::RXDS_VP = 0x008

const uint16_t	gem5::igbreg::RXDS_IXSM = 0x004

const uint16_t	gem5::igbreg::RXDS_EOP = 0x002

const uint16_t	gem5::igbreg::RXDS_DD = 0x001

const uint8_t	gem5::igbreg::RXDE_RXE = 0x80

const uint8_t	gem5::igbreg::RXDE_IPE = 0x40

const uint8_t	gem5::igbreg::RXDE_TCPE = 0x20

const uint8_t	gem5::igbreg::RXDE_SEQ = 0x04

const uint8_t	gem5::igbreg::RXDE_SE = 0x02

const uint8_t	gem5::igbreg::RXDE_CE = 0x01

const uint16_t	gem5::igbreg::RXDEE_HBO = 0x008

const uint16_t	gem5::igbreg::RXDEE_CE = 0x010

const uint16_t	gem5::igbreg::RXDEE_LE = 0x020

const uint16_t	gem5::igbreg::RXDEE_PE = 0x080

const uint16_t	gem5::igbreg::RXDEE_OSE = 0x100

const uint16_t	gem5::igbreg::RXDEE_USE = 0x200

const uint16_t	gem5::igbreg::RXDEE_TCPE = 0x400

const uint16_t	gem5::igbreg::RXDEE_IPE = 0x800

const uint8_t	gem5::igbreg::RXDT_LEGACY = 0x00

const uint8_t	gem5::igbreg::RXDT_ADV_ONEBUF = 0x01

const uint8_t	gem5::igbreg::RXDT_ADV_SPLIT_A = 0x05

const uint16_t	gem5::igbreg::RXDP_IPV4 = 0x001

const uint16_t	gem5::igbreg::RXDP_IPV4E = 0x002

const uint16_t	gem5::igbreg::RXDP_IPV6 = 0x004

const uint16_t	gem5::igbreg::RXDP_IPV6E = 0x008

const uint16_t	gem5::igbreg::RXDP_TCP = 0x010

const uint16_t	gem5::igbreg::RXDP_UDP = 0x020

const uint16_t	gem5::igbreg::RXDP_SCTP = 0x040

const uint16_t	gem5::igbreg::RXDP_NFS = 0x080

const uint8_t	gem5::igbreg::txd_op::TXD_CNXT = 0x0

const uint8_t	gem5::igbreg::txd_op::TXD_DATA = 0x1

const uint8_t	gem5::igbreg::txd_op::TXD_ADVCNXT = 0x2

const uint8_t	gem5::igbreg::txd_op::TXD_ADVDATA = 0x3

Macro Definition Documentation

◆ ADD_FIELD32

#define ADD_FIELD32	(	NAME,
		OFFSET,
		BITS )

Value:

inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \

inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }

Definition at line 425 of file i8254xGBe_defs.hh.

◆ ADD_FIELD64

#define ADD_FIELD64	(	NAME,
		OFFSET,
		BITS )

Value:

inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \

inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }

Definition at line 429 of file i8254xGBe_defs.hh.

Classes

Namespaces

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ ADD_FIELD32

◆ ADD_FIELD64