gem5  v21.2.1.1
i8254xGBe_defs.hh
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1 /*
2  * Copyright (c) 2006 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 /* @file
30  * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers.
31  */
32 #include "base/bitfield.hh"
33 #include "base/compiler.hh"
34 
35 namespace gem5
36 {
37 
38 GEM5_DEPRECATED_NAMESPACE(iGbReg, igbreg);
39 namespace igbreg
40 {
41 
42 // Registers used by the Intel GbE NIC
43 const uint32_t REG_CTRL = 0x00000;
44 const uint32_t REG_STATUS = 0x00008;
45 const uint32_t REG_EECD = 0x00010;
46 const uint32_t REG_EERD = 0x00014;
47 const uint32_t REG_CTRL_EXT = 0x00018;
48 const uint32_t REG_MDIC = 0x00020;
49 const uint32_t REG_FCAL = 0x00028;
50 const uint32_t REG_FCAH = 0x0002C;
51 const uint32_t REG_FCT = 0x00030;
52 const uint32_t REG_VET = 0x00038;
53 const uint32_t REG_PBA = 0x01000;
54 const uint32_t REG_ICR = 0x000C0;
55 const uint32_t REG_ITR = 0x000C4;
56 const uint32_t REG_ICS = 0x000C8;
57 const uint32_t REG_IMS = 0x000D0;
58 const uint32_t REG_IMC = 0x000D8;
59 const uint32_t REG_IAM = 0x000E0;
60 const uint32_t REG_RCTL = 0x00100;
61 const uint32_t REG_FCTTV = 0x00170;
62 const uint32_t REG_TIPG = 0x00410;
63 const uint32_t REG_AIFS = 0x00458;
64 const uint32_t REG_LEDCTL = 0x00e00;
65 const uint32_t REG_EICR = 0x01580;
66 const uint32_t REG_IVAR0 = 0x01700;
67 const uint32_t REG_FCRTL = 0x02160;
68 const uint32_t REG_FCRTH = 0x02168;
69 const uint32_t REG_RDBAL = 0x02800;
70 const uint32_t REG_RDBAH = 0x02804;
71 const uint32_t REG_RDLEN = 0x02808;
72 const uint32_t REG_SRRCTL = 0x0280C;
73 const uint32_t REG_RDH = 0x02810;
74 const uint32_t REG_RDT = 0x02818;
75 const uint32_t REG_RDTR = 0x02820;
76 const uint32_t REG_RXDCTL = 0x02828;
77 const uint32_t REG_RADV = 0x0282C;
78 const uint32_t REG_TCTL = 0x00400;
79 const uint32_t REG_TDBAL = 0x03800;
80 const uint32_t REG_TDBAH = 0x03804;
81 const uint32_t REG_TDLEN = 0x03808;
82 const uint32_t REG_TDH = 0x03810;
83 const uint32_t REG_TXDCA_CTL = 0x03814;
84 const uint32_t REG_TDT = 0x03818;
85 const uint32_t REG_TIDV = 0x03820;
86 const uint32_t REG_TXDCTL = 0x03828;
87 const uint32_t REG_TADV = 0x0382C;
88 const uint32_t REG_TDWBAL = 0x03838;
89 const uint32_t REG_TDWBAH = 0x0383C;
90 const uint32_t REG_CRCERRS = 0x04000;
91 const uint32_t REG_RXCSUM = 0x05000;
92 const uint32_t REG_RLPML = 0x05004;
93 const uint32_t REG_RFCTL = 0x05008;
94 const uint32_t REG_MTA = 0x05200;
95 const uint32_t REG_RAL = 0x05400;
96 const uint32_t REG_RAH = 0x05404;
97 const uint32_t REG_VFTA = 0x05600;
98 
99 const uint32_t REG_WUC = 0x05800;
100 const uint32_t REG_WUFC = 0x05808;
101 const uint32_t REG_WUS = 0x05810;
102 const uint32_t REG_MANC = 0x05820;
103 const uint32_t REG_SWSM = 0x05B50;
104 const uint32_t REG_FWSM = 0x05B54;
105 const uint32_t REG_SWFWSYNC = 0x05B5C;
106 
107 const uint8_t EEPROM_READ_OPCODE_SPI = 0x03;
108 const uint8_t EEPROM_RDSR_OPCODE_SPI = 0x05;
109 const uint8_t EEPROM_SIZE = 64;
110 const uint16_t EEPROM_CSUM = 0xBABA;
111 
112 const uint8_t VLAN_FILTER_TABLE_SIZE = 128;
113 const uint8_t RCV_ADDRESS_TABLE_SIZE = 24;
114 const uint8_t MULTICAST_TABLE_SIZE = 128;
115 const uint32_t STATS_REGS_SIZE = 0x228;
116 
117 
118 // Registers in that are accessed in the PHY
119 const uint8_t PHY_PSTATUS = 0x1;
120 const uint8_t PHY_PID = 0x2;
121 const uint8_t PHY_EPID = 0x3;
122 const uint8_t PHY_GSTATUS = 10;
123 const uint8_t PHY_EPSTATUS = 15;
124 const uint8_t PHY_AGC = 18;
125 
126 // Receive Descriptor Status Flags
127 const uint16_t RXDS_DYNINT = 0x800;
128 const uint16_t RXDS_UDPV = 0x400;
129 const uint16_t RXDS_CRCV = 0x100;
130 const uint16_t RXDS_PIF = 0x080;
131 const uint16_t RXDS_IPCS = 0x040;
132 const uint16_t RXDS_TCPCS = 0x020;
133 const uint16_t RXDS_UDPCS = 0x010;
134 const uint16_t RXDS_VP = 0x008;
135 const uint16_t RXDS_IXSM = 0x004;
136 const uint16_t RXDS_EOP = 0x002;
137 const uint16_t RXDS_DD = 0x001;
138 
139 // Receive Descriptor Error Flags
140 const uint8_t RXDE_RXE = 0x80;
141 const uint8_t RXDE_IPE = 0x40;
142 const uint8_t RXDE_TCPE = 0x20;
143 const uint8_t RXDE_SEQ = 0x04;
144 const uint8_t RXDE_SE = 0x02;
145 const uint8_t RXDE_CE = 0x01;
146 
147 // Receive Descriptor Extended Error Flags
148 const uint16_t RXDEE_HBO = 0x008;
149 const uint16_t RXDEE_CE = 0x010;
150 const uint16_t RXDEE_LE = 0x020;
151 const uint16_t RXDEE_PE = 0x080;
152 const uint16_t RXDEE_OSE = 0x100;
153 const uint16_t RXDEE_USE = 0x200;
154 const uint16_t RXDEE_TCPE = 0x400;
155 const uint16_t RXDEE_IPE = 0x800;
156 
157 
158 // Receive Descriptor Types
159 const uint8_t RXDT_LEGACY = 0x00;
160 const uint8_t RXDT_ADV_ONEBUF = 0x01;
161 const uint8_t RXDT_ADV_SPLIT_A = 0x05;
162 
163 // Receive Descriptor Packet Types
164 const uint16_t RXDP_IPV4 = 0x001;
165 const uint16_t RXDP_IPV4E = 0x002;
166 const uint16_t RXDP_IPV6 = 0x004;
167 const uint16_t RXDP_IPV6E = 0x008;
168 const uint16_t RXDP_TCP = 0x010;
169 const uint16_t RXDP_UDP = 0x020;
170 const uint16_t RXDP_SCTP = 0x040;
171 const uint16_t RXDP_NFS = 0x080;
172 
173 // Interrupt types
175 {
176  IT_NONE = 0x00000, //dummy value
177  IT_TXDW = 0x00001,
178  IT_TXQE = 0x00002,
179  IT_LSC = 0x00004,
180  IT_RXSEQ = 0x00008,
181  IT_RXDMT = 0x00010,
182  IT_RXO = 0x00040,
183  IT_RXT = 0x00080,
184  IT_MADC = 0x00200,
185  IT_RXCFG = 0x00400,
186  IT_GPI0 = 0x02000,
187  IT_GPI1 = 0x04000,
188  IT_TXDLOW = 0x08000,
189  IT_SRPD = 0x10000,
190  IT_ACK = 0x20000
191 };
192 
193 // Receive Descriptor struct
194 struct RxDesc
195 {
196  union
197  {
198  struct
199  {
201  uint16_t len;
202  uint16_t csum;
203  uint8_t status;
204  uint8_t errors;
205  uint16_t vlan;
206  } legacy;
207  struct
208  {
211  } adv_read;
212  struct
213  {
214  uint16_t rss_type:4;
215  uint16_t pkt_type:12;
216  uint16_t __reserved1:5;
217  uint16_t header_len:10;
218  uint16_t sph:1;
219  union
220  {
221  struct
222  {
223  uint16_t id;
224  uint16_t csum;
225  };
226  uint32_t rss_hash;
227  };
228  uint32_t status:20;
229  uint32_t errors:12;
230  uint16_t pkt_len;
231  uint16_t vlan_tag;
232  } adv_wb ;
233  };
234 };
235 
236 struct TxDesc
237 {
238  uint64_t d1;
239  uint64_t d2;
240 };
241 
242 GEM5_DEPRECATED_NAMESPACE(TxdOp, txd_op);
243 namespace txd_op
244 {
245 
246 const uint8_t TXD_CNXT = 0x0;
247 const uint8_t TXD_DATA = 0x1;
248 const uint8_t TXD_ADVCNXT = 0x2;
249 const uint8_t TXD_ADVDATA = 0x3;
250 
251 inline bool isLegacy(TxDesc *d) { return !bits(d->d2, 29); }
252 inline uint8_t getType(TxDesc *d) { return bits(d->d2, 23, 20); }
253 inline bool isType(TxDesc *d, uint8_t type) { return getType(d) == type; }
254 inline bool
255 isTypes(TxDesc *d, uint8_t t1, uint8_t t2)
256 {
257  return isType(d, t1) || isType(d, t2);
258 }
259 inline bool
261 {
262  return !isLegacy(d) && isTypes(d, TXD_ADVDATA,TXD_ADVCNXT);
263 }
264 inline bool
266 {
267  return !isLegacy(d) && isTypes(d,TXD_CNXT, TXD_ADVCNXT);
268 }
269 inline bool
271 {
272  return !isLegacy(d) && isTypes(d, TXD_DATA, TXD_ADVDATA);
273 }
274 
275 inline Addr
277 {
278  assert(isLegacy(d) || isData(d));
279  return d->d1;
280 }
281 inline Addr
283 {
284  if (isLegacy(d))
285  return bits(d->d2, 15, 0);
286  else
287  return bits(d->d2, 19, 0);
288 }
289 inline void setDd(TxDesc *d) { replaceBits(d->d2, 35, 32, 1ULL); }
290 
291 inline bool
293 {
294  return bits(d->d2, 31, 31) && (getType(d) == TXD_DATA || isLegacy(d));
295 }
296 inline bool
298 {
299  assert(isLegacy(d) || isData(d));
300  return bits(d->d2, 30);
301 }
302 inline bool rs(TxDesc *d) { return bits(d->d2, 27); }
303 inline bool
305 {
306  assert(isLegacy(d) || isData(d));
307  return isLegacy(d) && bits(d->d2, 26);
308 }
309 inline bool
311 {
312  if (isTypes(d, TXD_CNXT, TXD_DATA))
313  return bits(d->d2, 26);
314  if (isType(d, TXD_ADVDATA))
315  return bits(d->d2, 31);
316  return false;
317 }
318 
319 inline bool
321 {
322  assert(isLegacy(d) || isData(d));
323  return bits(d->d2, 25);
324 }
325 inline bool
327 {
328  assert(isLegacy(d) || isData(d));
329  return bits(d->d2, 24);
330 }
331 inline bool
333 {
334  assert(isContext(d));
335  return bits(d->d2, 25);
336 }
337 inline bool
339 {
340  assert(isContext(d));
341  return bits(d->d2, 24);
342 }
343 
344 inline uint8_t
346 {
347  assert(isLegacy(d));
348  return bits(d->d2, 23, 16);
349 }
350 inline uint8_t
352 {
353  assert(isLegacy(d));
354  return bits(d->d2, 47, 40);
355 }
356 
357 inline bool ixsm(TxDesc *d) { return isData(d) && bits(d->d2, 40, 40); }
358 inline bool txsm(TxDesc *d) { return isData(d) && bits(d->d2, 41, 41); }
359 
360 inline int
362 {
363  assert(isContext(d));
364  return bits(d->d1, 63, 48);
365 }
366 inline int
368 {
369  assert(isContext(d));
370  return bits(d->d1, 47, 40);
371 }
372 inline int
374 {
375  assert(isContext(d));
376  return bits(d->d1, 39, 32);
377 }
378 inline int
380 {
381  assert(isContext(d));
382  return bits(d->d1, 31, 16);
383 }
384 inline int
386 {
387  assert(isContext(d));
388  return bits(d->d1, 15, 8);
389 }
390 inline int
392 {
393  assert(isContext(d));
394  return bits(d->d1, 7, 0);
395 }
396 inline int
398 {
399  assert(isContext(d));
400  return bits(d->d2, 63, 48);
401 }
402 inline int
404 {
405  assert(isContext(d));
406  if (!isAdvDesc(d))
407  return bits(d->d2, 47, 40);
408  return bits(d->d2, 47, 40) + bits(d->d1, 8, 0) + bits(d->d1, 15, 9);
409 }
410 
411 inline int
413 {
414  assert(isType(d, TXD_ADVDATA));
415  return bits(d->d2, 63, 46);
416 }
417 inline int
419 {
420  assert(isContext(d));
421  return bits(d->d2, 24, 31);
422 }
423 
424 } // namespace txd_op
425 
426 
427 #define ADD_FIELD32(NAME, OFFSET, BITS) \
428  inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
429  inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
430 
431 #define ADD_FIELD64(NAME, OFFSET, BITS) \
432  inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
433  inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
434 
435 struct Regs : public Serializable
436 {
437  template<class T>
438  struct Reg
439  {
440  T _data;
441  T operator()() { return _data; }
442  const Reg<T> &operator=(T d) { _data = d; return *this;}
443  bool operator==(T d) { return d == _data; }
444  void operator()(T d) { _data = d; }
445  Reg() { _data = 0; }
446  void serialize(CheckpointOut &cp) const
447  {
449  }
451  {
453  }
454  };
455 
456  struct CTRL : public Reg<uint32_t>
457  {
458  // 0x0000 CTRL Register
460  ADD_FIELD32(fd, 0, 1); // full duplex
461  ADD_FIELD32(bem, 1, 1); // big endian mode
462  ADD_FIELD32(pcipr, 2, 1); // PCI priority
463  ADD_FIELD32(lrst, 3, 1); // link reset
464  ADD_FIELD32(tme, 4, 1); // test mode enable
465  ADD_FIELD32(asde, 5, 1); // Auto-speed detection
466  ADD_FIELD32(slu, 6, 1); // Set link up
467  ADD_FIELD32(ilos, 7, 1); // invert los-of-signal
468  ADD_FIELD32(speed, 8, 2); // speed selection bits
469  ADD_FIELD32(be32, 10, 1); // big endian mode 32
470  ADD_FIELD32(frcspd, 11, 1); // force speed
471  ADD_FIELD32(frcdpx, 12, 1); // force duplex
472  ADD_FIELD32(duden, 13, 1); // dock/undock enable
473  ADD_FIELD32(dudpol, 14, 1); // dock/undock polarity
474  ADD_FIELD32(fphyrst, 15, 1); // force phy reset
475  ADD_FIELD32(extlen, 16, 1); // external link status enable
476  ADD_FIELD32(rsvd, 17, 1); // reserved
477  ADD_FIELD32(sdp0d, 18, 1); // software controlled pin data
478  ADD_FIELD32(sdp1d, 19, 1); // software controlled pin data
479  ADD_FIELD32(sdp2d, 20, 1); // software controlled pin data
480  ADD_FIELD32(sdp3d, 21, 1); // software controlled pin data
481  ADD_FIELD32(sdp0i, 22, 1); // software controlled pin dir
482  ADD_FIELD32(sdp1i, 23, 1); // software controlled pin dir
483  ADD_FIELD32(sdp2i, 24, 1); // software controlled pin dir
484  ADD_FIELD32(sdp3i, 25, 1); // software controlled pin dir
485  ADD_FIELD32(rst, 26, 1); // reset
486  ADD_FIELD32(rfce, 27, 1); // receive flow control enable
487  ADD_FIELD32(tfce, 28, 1); // transmit flow control enable
488  ADD_FIELD32(rte, 29, 1); // routing tag enable
489  ADD_FIELD32(vme, 30, 1); // vlan enable
490  ADD_FIELD32(phyrst, 31, 1); // phy reset
491  };
493 
494  struct STATUS : public Reg<uint32_t>
495  {
496  // 0x0008 STATUS Register
498  ADD_FIELD32(fd, 0, 1); // full duplex
499  ADD_FIELD32(lu, 1, 1); // link up
500  ADD_FIELD32(func, 2, 2); // function id
501  ADD_FIELD32(txoff, 4, 1); // transmission paused
502  ADD_FIELD32(tbimode, 5, 1); // tbi mode
503  ADD_FIELD32(speed, 6, 2); // link speed
504  ADD_FIELD32(asdv, 8, 2); // auto speed detection value
505  ADD_FIELD32(mtxckok, 10, 1); // mtx clock running ok
506  ADD_FIELD32(pci66, 11, 1); // In 66Mhz pci slot
507  ADD_FIELD32(bus64, 12, 1); // in 64 bit slot
508  ADD_FIELD32(pcix, 13, 1); // Pci mode
509  ADD_FIELD32(pcixspd, 14, 2); // pci x speed
510  };
512 
513  struct EECD : public Reg<uint32_t>
514  {
515  // 0x0010 EECD Register
517  ADD_FIELD32(sk, 0, 1); // clack input to the eeprom
518  ADD_FIELD32(cs, 1, 1); // chip select to eeprom
519  ADD_FIELD32(din, 2, 1); // data input to eeprom
520  ADD_FIELD32(dout, 3, 1); // data output bit
521  ADD_FIELD32(fwe, 4, 2); // flash write enable
522  ADD_FIELD32(ee_req, 6, 1); // request eeprom access
523  ADD_FIELD32(ee_gnt, 7, 1); // grant eeprom access
524  ADD_FIELD32(ee_pres, 8, 1); // eeprom present
525  ADD_FIELD32(ee_size, 9, 1); // eeprom size
526  ADD_FIELD32(ee_sz1, 10, 1); // eeprom size
527  ADD_FIELD32(rsvd, 11, 2); // reserved
528  ADD_FIELD32(ee_type, 13, 1); // type of eeprom
529  } ;
531 
532  struct EERD : public Reg<uint32_t>
533  {
534  // 0x0014 EERD Register
536  ADD_FIELD32(start, 0, 1); // start read
537  ADD_FIELD32(done, 1, 1); // done read
538  ADD_FIELD32(addr, 2, 14); // address
539  ADD_FIELD32(data, 16, 16); // data
540  };
542 
543  struct CTRL_EXT : public Reg<uint32_t>
544  {
545  // 0x0018 CTRL_EXT Register
547  ADD_FIELD32(gpi_en, 0, 4); // enable interrupts from gpio
548  ADD_FIELD32(phyint, 5, 1); // reads the phy internal int status
549  ADD_FIELD32(sdp2_data, 6, 1); // data from gpio sdp
550  ADD_FIELD32(spd3_data, 7, 1); // data frmo gpio sdp
551  ADD_FIELD32(spd2_iodir, 10, 1); // direction of sdp2
552  ADD_FIELD32(spd3_iodir, 11, 1); // direction of sdp2
553  ADD_FIELD32(asdchk, 12, 1); // initiate auto-speed-detection
554  ADD_FIELD32(eerst, 13, 1); // reset the eeprom
555  ADD_FIELD32(spd_byps, 15, 1); // bypass speed select
556  ADD_FIELD32(ro_dis, 17, 1); // disable relaxed memory ordering
557  ADD_FIELD32(vreg, 21, 1); // power down the voltage regulator
558  ADD_FIELD32(link_mode, 22, 2); // interface to talk to the link
559  ADD_FIELD32(iame, 27, 1); // interrupt acknowledge auto-mask ??
560  ADD_FIELD32(drv_loaded, 28, 1); // driver is loaded and incharge of
561  // device
562  ADD_FIELD32(timer_clr, 29, 1); // clear interrupt timers after IMS
563  // clear ??
564  };
566 
567  struct MDIC : public Reg<uint32_t>
568  {
569  // 0x0020 MDIC Register
571  ADD_FIELD32(data, 0, 16); // data
572  ADD_FIELD32(regadd, 16, 5); // register address
573  ADD_FIELD32(phyadd, 21, 5); // phy addresses
574  ADD_FIELD32(op, 26, 2); // opcode
575  ADD_FIELD32(r, 28, 1); // ready
576  ADD_FIELD32(i, 29, 1); // interrupt
577  ADD_FIELD32(e, 30, 1); // error
578  };
580 
581  struct ICR : public Reg<uint32_t>
582  {
583  // 0x00C0 ICR Register
585  ADD_FIELD32(txdw, 0, 1) // tx descr witten back
586  ADD_FIELD32(txqe, 1, 1) // tx queue empty
587  ADD_FIELD32(lsc, 2, 1) // link status change
588  ADD_FIELD32(rxseq, 3, 1) // rcv sequence error
589  ADD_FIELD32(rxdmt0, 4, 1) // rcv descriptor min thresh
590  ADD_FIELD32(rsvd1, 5, 1) // reserved
591  ADD_FIELD32(rxo, 6, 1) // receive overrunn
592  ADD_FIELD32(rxt0, 7, 1) // receiver timer interrupt
593  ADD_FIELD32(mdac, 9, 1) // mdi/o access complete
594  ADD_FIELD32(rxcfg, 10, 1) // recv /c/ ordered sets
595  ADD_FIELD32(phyint, 12, 1) // phy interrupt
596  ADD_FIELD32(gpi1, 13, 1) // gpi int 1
597  ADD_FIELD32(gpi2, 14, 1) // gpi int 2
598  ADD_FIELD32(txdlow, 15, 1) // transmit desc low thresh
599  ADD_FIELD32(srpd, 16, 1) // small receive packet detected
600  ADD_FIELD32(ack, 17, 1); // receive ack frame
601  ADD_FIELD32(int_assert, 31, 1); // interrupt caused a system interrupt
602  };
604 
605  uint32_t imr; // register that contains the current interrupt mask
606 
607  struct ITR : public Reg<uint32_t>
608  {
609  // 0x00C4 ITR Register
611  ADD_FIELD32(interval, 0, 16); // minimum inter-interrutp inteval
612  // specified in 256ns interrupts
613  };
615 
616  // When CTRL_EXT.IAME and the ICR.INT_ASSERT is 1 an ICR read or write
617  // causes the IAM register contents to be written into the IMC
618  // automatically clearing all interrupts that have a bit in the IAM set
619  uint32_t iam;
620 
621  struct RCTL : public Reg<uint32_t>
622  {
623  // 0x0100 RCTL Register
625  ADD_FIELD32(rst, 0, 1); // Reset
626  ADD_FIELD32(en, 1, 1); // Enable
627  ADD_FIELD32(sbp, 2, 1); // Store bad packets
628  ADD_FIELD32(upe, 3, 1); // Unicast Promiscuous enabled
629  ADD_FIELD32(mpe, 4, 1); // Multicast promiscuous enabled
630  ADD_FIELD32(lpe, 5, 1); // long packet reception enabled
631  ADD_FIELD32(lbm, 6, 2); //
632  ADD_FIELD32(rdmts, 8, 2); //
633  ADD_FIELD32(mo, 12, 2); //
634  ADD_FIELD32(mdr, 14, 1); //
635  ADD_FIELD32(bam, 15, 1); //
636  ADD_FIELD32(bsize, 16, 2); //
637  ADD_FIELD32(vfe, 18, 1); //
638  ADD_FIELD32(cfien, 19, 1); //
639  ADD_FIELD32(cfi, 20, 1); //
640  ADD_FIELD32(dpf, 22, 1); // discard pause frames
641  ADD_FIELD32(pmcf, 23, 1); // pass mac control frames
642  ADD_FIELD32(bsex, 25, 1); // buffer size extension
643  ADD_FIELD32(secrc, 26, 1); // strip ethernet crc from incoming packet
644  unsigned descSize()
645  {
646  switch(bsize()) {
647  case 0: return bsex() == 0 ? 2048 : 0;
648  case 1: return bsex() == 0 ? 1024 : 16384;
649  case 2: return bsex() == 0 ? 512 : 8192;
650  case 3: return bsex() == 0 ? 256 : 4096;
651  default:
652  return 0;
653  }
654  }
655  };
657 
658  struct FCTTV : public Reg<uint32_t>
659  {
660  // 0x0170 FCTTV
662  ADD_FIELD32(ttv, 0, 16); // Transmit Timer Value
663  };
665 
666  struct TCTL : public Reg<uint32_t>
667  {
668  // 0x0400 TCTL Register
670  ADD_FIELD32(rst, 0, 1); // Reset
671  ADD_FIELD32(en, 1, 1); // Enable
672  ADD_FIELD32(bce, 2, 1); // busy check enable
673  ADD_FIELD32(psp, 3, 1); // pad short packets
674  ADD_FIELD32(ct, 4, 8); // collision threshold
675  ADD_FIELD32(cold, 12, 10); // collision distance
676  ADD_FIELD32(swxoff, 22, 1); // software xoff transmission
677  ADD_FIELD32(pbe, 23, 1); // packet burst enable
678  ADD_FIELD32(rtlc, 24, 1); // retransmit late collisions
679  ADD_FIELD32(nrtu, 25, 1); // on underrun no TX
680  ADD_FIELD32(mulr, 26, 1); // multiple request
681  };
683 
684  struct PBA : public Reg<uint32_t>
685  {
686  // 0x1000 PBA Register
688  ADD_FIELD32(rxa, 0, 16);
689  ADD_FIELD32(txa, 16, 16);
690  };
692 
693  struct FCRTL : public Reg<uint32_t>
694  {
695  // 0x2160 FCRTL Register
697  ADD_FIELD32(rtl, 3, 28); // make this bigger than the spec so we can
698  // have a larger buffer
699  ADD_FIELD32(xone, 31, 1);
700  };
702 
703  struct FCRTH : public Reg<uint32_t>
704  {
705  // 0x2168 FCRTL Register
707  ADD_FIELD32(rth, 3, 13); // make this bigger than the spec so we can
708  // have a larger buffer
709  ADD_FIELD32(xfce, 31, 1);
710  };
712 
713  struct RDBA : public Reg<uint64_t>
714  {
715  // 0x2800 RDBA Register
717  ADD_FIELD64(rdbal, 0, 32); // base address of rx descriptor ring
718  ADD_FIELD64(rdbah, 32, 32); // base address of rx descriptor ring
719  };
721 
722  struct RDLEN : public Reg<uint32_t>
723  {
724  // 0x2808 RDLEN Register
726  ADD_FIELD32(len, 7, 13); // number of bytes in the descriptor buffer
727  };
729 
730  struct SRRCTL : public Reg<uint32_t>
731  {
732  // 0x280C SRRCTL Register
734  ADD_FIELD32(pktlen, 0, 8);
735  ADD_FIELD32(hdrlen, 8, 8); // guess based on header, not documented
736  ADD_FIELD32(desctype, 25, 3); // type of descriptor 000 legacy,
737  // 001 adv, 101 hdr split
738  unsigned bufLen() { return pktlen() << 10; }
739  unsigned hdrLen() { return hdrlen() << 6; }
740  };
742 
743  struct RDH : public Reg<uint32_t>
744  {
745  // 0x2810 RDH Register
747  ADD_FIELD32(rdh, 0, 16); // head of the descriptor ring
748  };
750 
751  struct RDT : public Reg<uint32_t>
752  {
753  // 0x2818 RDT Register
755  ADD_FIELD32(rdt, 0, 16); // tail of the descriptor ring
756  };
758 
759  struct RDTR : public Reg<uint32_t>
760  {
761  // 0x2820 RDTR Register
763  ADD_FIELD32(delay, 0, 16); // receive delay timer
764  ADD_FIELD32(fpd, 31, 1); // flush partial descriptor block ??
765  };
767 
768  struct RXDCTL : public Reg<uint32_t>
769  {
770  // 0x2828 RXDCTL Register
772  ADD_FIELD32(pthresh, 0, 6); // prefetch threshold, less that this
773  // consider prefetch
774  ADD_FIELD32(hthresh, 8, 6); // number of descriptors in host mem to
775  // consider prefetch
776  ADD_FIELD32(wthresh, 16, 6); // writeback threshold
777  ADD_FIELD32(gran, 24, 1); // granularity 0 = desc, 1 = cacheline
778  };
780 
781  struct RADV : public Reg<uint32_t>
782  {
783  // 0x282C RADV Register
785  ADD_FIELD32(idv, 0, 16); // absolute interrupt delay
786  };
788 
789  struct RSRPD : public Reg<uint32_t>
790  {
791  // 0x2C00 RSRPD Register
793  ADD_FIELD32(idv, 0, 12); // size to interrutp on small packets
794  };
796 
797  struct TDBA : public Reg<uint64_t>
798  {
799  // 0x3800 TDBAL Register
801  ADD_FIELD64(tdbal, 0, 32); // base address of transmit descriptor ring
802  ADD_FIELD64(tdbah, 32, 32); // base address of transmit descriptor ring
803  };
805 
806  struct TDLEN : public Reg<uint32_t>
807  {
808  // 0x3808 TDLEN Register
810  ADD_FIELD32(len, 7, 13); // number of bytes in the descriptor buffer
811  };
813 
814  struct TDH : public Reg<uint32_t>
815  {
816  // 0x3810 TDH Register
818  ADD_FIELD32(tdh, 0, 16); // head of the descriptor ring
819  };
821 
822  struct TXDCA_CTL : public Reg<uint32_t>
823  {
824  // 0x3814 TXDCA_CTL Register
826  ADD_FIELD32(cpu_mask, 0, 5);
827  ADD_FIELD32(enabled, 5, 1);
828  ADD_FIELD32(relax_ordering, 6, 1);
829  };
831 
832  struct TDT : public Reg<uint32_t>
833  {
834  // 0x3818 TDT Register
836  ADD_FIELD32(tdt, 0, 16); // tail of the descriptor ring
837  };
839 
840  struct TIDV : public Reg<uint32_t>
841  {
842  // 0x3820 TIDV Register
844  ADD_FIELD32(idv, 0, 16); // interrupt delay
845  };
847 
848  struct TXDCTL : public Reg<uint32_t>
849  {
850  // 0x3828 TXDCTL Register
852  ADD_FIELD32(pthresh, 0, 6); // if number of descriptors control has is
853  // below this number, a prefetch is
854  //considered
855  ADD_FIELD32(hthresh, 8, 8); // number of valid descriptors is host
856  // memory before a prefetch is considered
857  ADD_FIELD32(wthresh, 16, 6);// number of descriptors to keep until
858  // writeback is considered
859  ADD_FIELD32(gran, 24, 1); // granulatiry of above values
860  // (0 = cacheline, 1 == desscriptor)
861  ADD_FIELD32(lwthresh, 25, 7); // xmit descriptor low thresh, interrupt
862  // below this level
863  };
865 
866  struct TADV : public Reg<uint32_t>
867  {
868  // 0x382C TADV Register
870  ADD_FIELD32(idv, 0, 16); // absolute interrupt delay
871  };
873  uint64_t tdwba;
874 
875  struct RXCSUM : public Reg<uint32_t>
876  {
877  // 0x5000 RXCSUM Register
879  ADD_FIELD32(pcss, 0, 8);
880  ADD_FIELD32(ipofld, 8, 1);
881  ADD_FIELD32(tuofld, 9, 1);
882  ADD_FIELD32(pcsd, 13, 1);
883  };
885 
886  uint32_t rlpml; // 0x5004 RLPML probably maximum accepted packet size
887 
888  struct RFCTL : public Reg<uint32_t>
889  {
890  // 0x5008 RFCTL Register
892  ADD_FIELD32(iscsi_dis, 0, 1);
893  ADD_FIELD32(iscsi_dwc, 1, 5);
894  ADD_FIELD32(nfsw_dis, 6, 1);
895  ADD_FIELD32(nfsr_dis, 7, 1);
896  ADD_FIELD32(nfs_ver, 8, 2);
897  ADD_FIELD32(ipv6_dis, 10, 1);
898  ADD_FIELD32(ipv6xsum_dis, 11, 1);
899  ADD_FIELD32(ackdis, 13, 1);
900  ADD_FIELD32(ipfrsp_dis, 14, 1);
901  ADD_FIELD32(exsten, 15, 1);
902  };
904 
905  struct MANC : public Reg<uint32_t>
906  {
907  // 0x5820 MANC Register
909  ADD_FIELD32(smbus, 0, 1); // SMBus enabled #####
910  ADD_FIELD32(asf, 1, 1); // ASF enabled #####
911  ADD_FIELD32(ronforce, 2, 1); // reset of force
912  ADD_FIELD32(rsvd, 3, 5); // reserved
913  ADD_FIELD32(rmcp1, 8, 1); // rcmp1 filtering
914  ADD_FIELD32(rmcp2, 9, 1); // rcmp2 filtering
915  ADD_FIELD32(ipv4, 10, 1); // enable ipv4
916  ADD_FIELD32(ipv6, 11, 1); // enable ipv6
917  ADD_FIELD32(snap, 12, 1); // accept snap
918  ADD_FIELD32(arp, 13, 1); // filter arp #####
919  ADD_FIELD32(neighbor, 14, 1); // neighbor discovery
920  ADD_FIELD32(arp_resp, 15, 1); // arp response
921  ADD_FIELD32(tcorst, 16, 1); // tco reset happened
922  ADD_FIELD32(rcvtco, 17, 1); // receive tco enabled ######
923  ADD_FIELD32(blkphyrst, 18, 1);// block phy resets ########
924  ADD_FIELD32(rcvall, 19, 1); // receive all
925  ADD_FIELD32(macaddrfltr, 20, 1); // mac address filtering ######
926  ADD_FIELD32(mng2host, 21, 1); // mng2 host packets #######
927  ADD_FIELD32(ipaddrfltr, 22, 1); // ip address filtering
928  ADD_FIELD32(xsumfilter, 23, 1); // checksum filtering
929  ADD_FIELD32(brfilter, 24, 1); // broadcast filtering
930  ADD_FIELD32(smbreq, 25, 1); // smb request
931  ADD_FIELD32(smbgnt, 26, 1); // smb grant
932  ADD_FIELD32(smbclkin, 27, 1); // smbclkin
933  ADD_FIELD32(smbdatain, 28, 1); // smbdatain
934  ADD_FIELD32(smbdataout, 29, 1); // smb data out
935  ADD_FIELD32(smbclkout, 30, 1); // smb clock out
936  };
938 
939  struct SWSM : public Reg<uint32_t>
940  {
941  // 0x5B50 SWSM register
943  ADD_FIELD32(smbi, 0, 1); // Semaphone bit
944  ADD_FIELD32(swesmbi, 1, 1); // Software eeporm semaphore
945  ADD_FIELD32(wmng, 2, 1); // Wake MNG clock
946  ADD_FIELD32(reserved, 3, 29);
947  };
949 
950  struct FWSM : public Reg<uint32_t>
951  {
952  // 0x5B54 FWSM register
954  ADD_FIELD32(eep_fw_semaphore, 0, 1);
955  ADD_FIELD32(fw_mode, 1, 3);
956  ADD_FIELD32(ide, 4, 1);
957  ADD_FIELD32(sol, 5, 1);
958  ADD_FIELD32(eep_roload, 6, 1);
959  ADD_FIELD32(reserved, 7, 8);
960  ADD_FIELD32(fw_val_bit, 15, 1);
961  ADD_FIELD32(reset_cnt, 16, 3);
962  ADD_FIELD32(ext_err_ind, 19, 6);
963  ADD_FIELD32(reserved2, 25, 7);
964  };
966 
967  uint32_t sw_fw_sync;
968 
969  void serialize(CheckpointOut &cp) const override
970  {
971  paramOut(cp, "ctrl", ctrl._data);
972  paramOut(cp, "sts", sts._data);
973  paramOut(cp, "eecd", eecd._data);
974  paramOut(cp, "eerd", eerd._data);
975  paramOut(cp, "ctrl_ext", ctrl_ext._data);
976  paramOut(cp, "mdic", mdic._data);
977  paramOut(cp, "icr", icr._data);
979  paramOut(cp, "itr", itr._data);
981  paramOut(cp, "rctl", rctl._data);
982  paramOut(cp, "fcttv", fcttv._data);
983  paramOut(cp, "tctl", tctl._data);
984  paramOut(cp, "pba", pba._data);
985  paramOut(cp, "fcrtl", fcrtl._data);
986  paramOut(cp, "fcrth", fcrth._data);
987  paramOut(cp, "rdba", rdba._data);
988  paramOut(cp, "rdlen", rdlen._data);
989  paramOut(cp, "srrctl", srrctl._data);
990  paramOut(cp, "rdh", rdh._data);
991  paramOut(cp, "rdt", rdt._data);
992  paramOut(cp, "rdtr", rdtr._data);
993  paramOut(cp, "rxdctl", rxdctl._data);
994  paramOut(cp, "radv", radv._data);
995  paramOut(cp, "rsrpd", rsrpd._data);
996  paramOut(cp, "tdba", tdba._data);
997  paramOut(cp, "tdlen", tdlen._data);
998  paramOut(cp, "tdh", tdh._data);
999  paramOut(cp, "txdca_ctl", txdca_ctl._data);
1000  paramOut(cp, "tdt", tdt._data);
1001  paramOut(cp, "tidv", tidv._data);
1002  paramOut(cp, "txdctl", txdctl._data);
1003  paramOut(cp, "tadv", tadv._data);
1004  //paramOut(cp, "tdwba", tdwba._data);
1006  paramOut(cp, "rxcsum", rxcsum._data);
1008  paramOut(cp, "rfctl", rfctl._data);
1009  paramOut(cp, "manc", manc._data);
1010  paramOut(cp, "swsm", swsm._data);
1011  paramOut(cp, "fwsm", fwsm._data);
1013  }
1014 
1015  void unserialize(CheckpointIn &cp) override
1016  {
1017  paramIn(cp, "ctrl", ctrl._data);
1018  paramIn(cp, "sts", sts._data);
1019  paramIn(cp, "eecd", eecd._data);
1020  paramIn(cp, "eerd", eerd._data);
1021  paramIn(cp, "ctrl_ext", ctrl_ext._data);
1022  paramIn(cp, "mdic", mdic._data);
1023  paramIn(cp, "icr", icr._data);
1025  paramIn(cp, "itr", itr._data);
1027  paramIn(cp, "rctl", rctl._data);
1028  paramIn(cp, "fcttv", fcttv._data);
1029  paramIn(cp, "tctl", tctl._data);
1030  paramIn(cp, "pba", pba._data);
1031  paramIn(cp, "fcrtl", fcrtl._data);
1032  paramIn(cp, "fcrth", fcrth._data);
1033  paramIn(cp, "rdba", rdba._data);
1034  paramIn(cp, "rdlen", rdlen._data);
1035  paramIn(cp, "srrctl", srrctl._data);
1036  paramIn(cp, "rdh", rdh._data);
1037  paramIn(cp, "rdt", rdt._data);
1038  paramIn(cp, "rdtr", rdtr._data);
1039  paramIn(cp, "rxdctl", rxdctl._data);
1040  paramIn(cp, "radv", radv._data);
1041  paramIn(cp, "rsrpd", rsrpd._data);
1042  paramIn(cp, "tdba", tdba._data);
1043  paramIn(cp, "tdlen", tdlen._data);
1044  paramIn(cp, "tdh", tdh._data);
1045  paramIn(cp, "txdca_ctl", txdca_ctl._data);
1046  paramIn(cp, "tdt", tdt._data);
1047  paramIn(cp, "tidv", tidv._data);
1048  paramIn(cp, "txdctl", txdctl._data);
1049  paramIn(cp, "tadv", tadv._data);
1051  //paramIn(cp, "tdwba", tdwba._data);
1052  paramIn(cp, "rxcsum", rxcsum._data);
1054  paramIn(cp, "rfctl", rfctl._data);
1055  paramIn(cp, "manc", manc._data);
1056  paramIn(cp, "swsm", swsm._data);
1057  paramIn(cp, "fwsm", fwsm._data);
1059  }
1060 };
1061 
1062 } // namespace igbreg
1063 } // namespace gem5
gem5::igbreg::Regs::TDBA::ADD_FIELD64
ADD_FIELD64(tdbal, 0, 32)
gem5::igbreg::RXDS_IPCS
const uint16_t RXDS_IPCS
Definition: i8254xGBe_defs.hh:131
gem5::igbreg::Regs::rctl
RCTL rctl
Definition: i8254xGBe_defs.hh:656
gem5::igbreg::RXDEE_PE
const uint16_t RXDEE_PE
Definition: i8254xGBe_defs.hh:151
gem5::igbreg::RXDE_SE
const uint8_t RXDE_SE
Definition: i8254xGBe_defs.hh:144
gem5::igbreg::Regs::Reg::Reg
Reg()
Definition: i8254xGBe_defs.hh:445
gem5::igbreg::REG_FCT
const uint32_t REG_FCT
Definition: i8254xGBe_defs.hh:51
gem5::igbreg::Regs::Reg::serialize
void serialize(CheckpointOut &cp) const
Definition: i8254xGBe_defs.hh:446
gem5::igbreg::txd_op::ipcss
int ipcss(TxDesc *d)
Definition: i8254xGBe_defs.hh:391
gem5::igbreg::RXDE_RXE
const uint8_t RXDE_RXE
Definition: i8254xGBe_defs.hh:140
gem5::igbreg::Regs::SRRCTL::bufLen
unsigned bufLen()
Definition: i8254xGBe_defs.hh:738
gem5::igbreg::Regs::RDBA
Definition: i8254xGBe_defs.hh:713
gem5::igbreg::Regs::TCTL
Definition: i8254xGBe_defs.hh:666
gem5::igbreg::txd_op::mss
int mss(TxDesc *d)
Definition: i8254xGBe_defs.hh:397
gem5::igbreg::REG_RDTR
const uint32_t REG_RDTR
Definition: i8254xGBe_defs.hh:75
gem5::igbreg::RxDesc::len
uint16_t len
Definition: i8254xGBe_defs.hh:201
gem5::igbreg::txd_op::tucso
int tucso(TxDesc *d)
Definition: i8254xGBe_defs.hh:367
gem5::igbreg::txd_op::isContext
bool isContext(TxDesc *d)
Definition: i8254xGBe_defs.hh:265
gem5::igbreg::REG_CRCERRS
const uint32_t REG_CRCERRS
Definition: i8254xGBe_defs.hh:90
gem5::igbreg::RxDesc::status
uint8_t status
Definition: i8254xGBe_defs.hh:203
gem5::igbreg::REG_PBA
const uint32_t REG_PBA
Definition: i8254xGBe_defs.hh:53
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:445
gem5::igbreg::Regs::RXCSUM::ADD_FIELD32
ADD_FIELD32(pcss, 0, 8)
gem5::igbreg::Regs::tadv
TADV tadv
Definition: i8254xGBe_defs.hh:872
gem5::igbreg::Regs::SRRCTL
Definition: i8254xGBe_defs.hh:730
gem5::igbreg::REG_WUFC
const uint32_t REG_WUFC
Definition: i8254xGBe_defs.hh:100
gem5::igbreg::REG_MTA
const uint32_t REG_MTA
Definition: i8254xGBe_defs.hh:94
gem5::igbreg::Regs::imr
uint32_t imr
Definition: i8254xGBe_defs.hh:605
gem5::igbreg::REG_VFTA
const uint32_t REG_VFTA
Definition: i8254xGBe_defs.hh:97
gem5::igbreg::Regs::pba
PBA pba
Definition: i8254xGBe_defs.hh:691
gem5::igbreg::Regs::txdctl
TXDCTL txdctl
Definition: i8254xGBe_defs.hh:864
gem5::igbreg::Regs::TDLEN::ADD_FIELD32
ADD_FIELD32(len, 7, 13)
gem5::igbreg::Regs::ITR::ADD_FIELD32
ADD_FIELD32(interval, 0, 16)
gem5::igbreg::txd_op::TXD_DATA
const uint8_t TXD_DATA
Definition: i8254xGBe_defs.hh:247
gem5::igbreg::RXDP_UDP
const uint16_t RXDP_UDP
Definition: i8254xGBe_defs.hh:169
gem5::igbreg::REG_RXDCTL
const uint32_t REG_RXDCTL
Definition: i8254xGBe_defs.hh:76
gem5::igbreg::REG_SWSM
const uint32_t REG_SWSM
Definition: i8254xGBe_defs.hh:103
gem5::igbreg::Regs::TDBA
Definition: i8254xGBe_defs.hh:797
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::igbreg::RXDS_UDPV
const uint16_t RXDS_UDPV
Definition: i8254xGBe_defs.hh:128
gem5::igbreg::txd_op::ic
bool ic(TxDesc *d)
Definition: i8254xGBe_defs.hh:304
gem5::igbreg::RXDEE_HBO
const uint16_t RXDEE_HBO
Definition: i8254xGBe_defs.hh:148
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::ArmISA::fd
Bitfield< 14, 12 > fd
Definition: types.hh:150
gem5::igbreg::Regs::TDH::ADD_FIELD32
ADD_FIELD32(tdh, 0, 16)
gem5::igbreg::RXDE_TCPE
const uint8_t RXDE_TCPE
Definition: i8254xGBe_defs.hh:142
gem5::igbreg::Regs::TDT
Definition: i8254xGBe_defs.hh:832
gem5::igbreg::Regs::FCRTH::ADD_FIELD32
ADD_FIELD32(rth, 3, 13)
gem5::igbreg::Regs::PBA::ADD_FIELD32
ADD_FIELD32(rxa, 0, 16)
gem5::igbreg::REG_CTRL
const uint32_t REG_CTRL
Definition: i8254xGBe_defs.hh:43
gem5::igbreg::TxDesc
Definition: i8254xGBe_defs.hh:236
gem5::igbreg::txd_op::eop
bool eop(TxDesc *d)
Definition: i8254xGBe_defs.hh:326
gem5::igbreg::Regs::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8254xGBe_defs.hh:969
gem5::igbreg::Regs::Reg::operator=
const Reg< T > & operator=(T d)
Definition: i8254xGBe_defs.hh:442
gem5::igbreg::REG_TDWBAL
const uint32_t REG_TDWBAL
Definition: i8254xGBe_defs.hh:88
gem5::igbreg::Regs::ctrl
CTRL ctrl
Definition: i8254xGBe_defs.hh:492
gem5::igbreg::Regs::RDT
Definition: i8254xGBe_defs.hh:751
gem5::igbreg::Regs::RDBA::ADD_FIELD64
ADD_FIELD64(rdbal, 0, 32)
gem5::igbreg::Regs::fcrth
FCRTH fcrth
Definition: i8254xGBe_defs.hh:711
gem5::igbreg::REG_TIDV
const uint32_t REG_TIDV
Definition: i8254xGBe_defs.hh:85
gem5::igbreg::txd_op::rs
bool rs(TxDesc *d)
Definition: i8254xGBe_defs.hh:302
gem5::igbreg::Regs::RXCSUM
Definition: i8254xGBe_defs.hh:875
gem5::igbreg::RxDesc::rss_type
uint16_t rss_type
Definition: i8254xGBe_defs.hh:214
gem5::igbreg::RXDE_SEQ
const uint8_t RXDE_SEQ
Definition: i8254xGBe_defs.hh:143
gem5::igbreg::REG_RLPML
const uint32_t REG_RLPML
Definition: i8254xGBe_defs.hh:92
gem5::igbreg::IT_TXDW
@ IT_TXDW
Definition: i8254xGBe_defs.hh:177
gem5::igbreg::Regs::RDT::ADD_FIELD32
ADD_FIELD32(rdt, 0, 16)
gem5::igbreg::Regs::TCTL::ADD_FIELD32
ADD_FIELD32(rst, 0, 1)
gem5::igbreg::txd_op::isAdvDesc
bool isAdvDesc(TxDesc *d)
Definition: i8254xGBe_defs.hh:260
gem5::igbreg::txd_op::isData
bool isData(TxDesc *d)
Definition: i8254xGBe_defs.hh:270
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::igbreg::VLAN_FILTER_TABLE_SIZE
const uint8_t VLAN_FILTER_TABLE_SIZE
Definition: i8254xGBe_defs.hh:112
gem5::igbreg::IT_GPI0
@ IT_GPI0
Definition: i8254xGBe_defs.hh:186
gem5::igbreg::REG_IAM
const uint32_t REG_IAM
Definition: i8254xGBe_defs.hh:59
gem5::igbreg::txd_op::tucse
int tucse(TxDesc *d)
Definition: i8254xGBe_defs.hh:361
gem5::igbreg::Regs::RDLEN::ADD_FIELD32
ADD_FIELD32(len, 7, 13)
gem5::igbreg::Regs::fcttv
FCTTV fcttv
Definition: i8254xGBe_defs.hh:664
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::igbreg::txd_op::getCss
uint8_t getCss(TxDesc *d)
Definition: i8254xGBe_defs.hh:351
gem5::igbreg::REG_ICS
const uint32_t REG_ICS
Definition: i8254xGBe_defs.hh:56
gem5::igbreg::Regs::EECD
Definition: i8254xGBe_defs.hh:513
gem5::igbreg::Regs::mdic
MDIC mdic
Definition: i8254xGBe_defs.hh:579
gem5::igbreg::REG_RCTL
const uint32_t REG_RCTL
Definition: i8254xGBe_defs.hh:60
gem5::igbreg::Regs::PBA
Definition: i8254xGBe_defs.hh:684
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::igbreg::Regs::MANC::ADD_FIELD32
ADD_FIELD32(smbus, 0, 1)
gem5::igbreg::txd_op::ipcse
int ipcse(TxDesc *d)
Definition: i8254xGBe_defs.hh:379
gem5::igbreg::RXDP_SCTP
const uint16_t RXDP_SCTP
Definition: i8254xGBe_defs.hh:170
gem5::igbreg::txd_op::isType
bool isType(TxDesc *d, uint8_t type)
Definition: i8254xGBe_defs.hh:253
gem5::igbreg::REG_RADV
const uint32_t REG_RADV
Definition: i8254xGBe_defs.hh:77
gem5::igbreg::IT_LSC
@ IT_LSC
Definition: i8254xGBe_defs.hh:179
gem5::igbreg::RCV_ADDRESS_TABLE_SIZE
const uint8_t RCV_ADDRESS_TABLE_SIZE
Definition: i8254xGBe_defs.hh:113
gem5::igbreg::RxDesc
Definition: i8254xGBe_defs.hh:194
gem5::igbreg::Regs::SWSM
Definition: i8254xGBe_defs.hh:939
gem5::igbreg::Regs::ITR
Definition: i8254xGBe_defs.hh:607
gem5::igbreg::Regs::sw_fw_sync
uint32_t sw_fw_sync
Definition: i8254xGBe_defs.hh:967
gem5::igbreg::Regs::tdlen
TDLEN tdlen
Definition: i8254xGBe_defs.hh:812
gem5::igbreg::Regs::STATUS
Definition: i8254xGBe_defs.hh:494
gem5::igbreg::EEPROM_CSUM
const uint16_t EEPROM_CSUM
Definition: i8254xGBe_defs.hh:110
gem5::igbreg::RxDesc::pkt_len
uint16_t pkt_len
Definition: i8254xGBe_defs.hh:230
gem5::igbreg::REG_EECD
const uint32_t REG_EECD
Definition: i8254xGBe_defs.hh:45
gem5::igbreg::Regs::STATUS::ADD_FIELD32
ADD_FIELD32(fd, 0, 1)
gem5::igbreg::REG_RDT
const uint32_t REG_RDT
Definition: i8254xGBe_defs.hh:74
gem5::igbreg::txd_op::ipcso
int ipcso(TxDesc *d)
Definition: i8254xGBe_defs.hh:385
gem5::igbreg::Regs::MDIC
Definition: i8254xGBe_defs.hh:567
gem5::igbreg::REG_IVAR0
const uint32_t REG_IVAR0
Definition: i8254xGBe_defs.hh:66
gem5::igbreg::txd_op::TXD_CNXT
const uint8_t TXD_CNXT
Definition: i8254xGBe_defs.hh:246
gem5::igbreg::IT_MADC
@ IT_MADC
Definition: i8254xGBe_defs.hh:184
gem5::igbreg::Regs::CTRL_EXT
Definition: i8254xGBe_defs.hh:543
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::igbreg::RXDEE_TCPE
const uint16_t RXDEE_TCPE
Definition: i8254xGBe_defs.hh:154
gem5::igbreg::txd_op::TXD_ADVDATA
const uint8_t TXD_ADVDATA
Definition: i8254xGBe_defs.hh:249
gem5::igbreg::txd_op::setDd
void setDd(TxDesc *d)
Definition: i8254xGBe_defs.hh:289
gem5::igbreg::Regs::rdh
RDH rdh
Definition: i8254xGBe_defs.hh:749
gem5::igbreg::Regs::CTRL_EXT::ADD_FIELD32
ADD_FIELD32(gpi_en, 0, 4)
gem5::igbreg::RxDesc::vlan_tag
uint16_t vlan_tag
Definition: i8254xGBe_defs.hh:231
gem5::igbreg::Regs::RFCTL::ADD_FIELD32
ADD_FIELD32(iscsi_dis, 0, 1)
gem5::igbreg::REG_FCAL
const uint32_t REG_FCAL
Definition: i8254xGBe_defs.hh:49
gem5::igbreg::IT_TXDLOW
@ IT_TXDLOW
Definition: i8254xGBe_defs.hh:188
gem5::igbreg::Regs::tdba
TDBA tdba
Definition: i8254xGBe_defs.hh:804
gem5::igbreg::Regs::FCRTH
Definition: i8254xGBe_defs.hh:703
gem5::igbreg::Regs::eecd
EECD eecd
Definition: i8254xGBe_defs.hh:530
gem5::igbreg::Regs::TDT::ADD_FIELD32
ADD_FIELD32(tdt, 0, 16)
gem5::igbreg::Regs::EERD::ADD_FIELD32
ADD_FIELD32(start, 0, 1)
gem5::igbreg::IT_RXDMT
@ IT_RXDMT
Definition: i8254xGBe_defs.hh:181
gem5::igbreg::txd_op::getBuf
Addr getBuf(TxDesc *d)
Definition: i8254xGBe_defs.hh:276
gem5::ArmISA::t1
Bitfield< 1 > t1
Definition: misc_types.hh:233
gem5::igbreg::REG_TXDCA_CTL
const uint32_t REG_TXDCA_CTL
Definition: i8254xGBe_defs.hh:83
gem5::igbreg::RxDesc::legacy
struct gem5::igbreg::RxDesc::@87::@89 legacy
gem5::igbreg::Regs::radv
RADV radv
Definition: i8254xGBe_defs.hh:787
gem5::igbreg::txd_op::utcmd
int utcmd(TxDesc *d)
Definition: i8254xGBe_defs.hh:418
gem5::igbreg::RXDP_IPV6E
const uint16_t RXDP_IPV6E
Definition: i8254xGBe_defs.hh:167
reserved
reserved
Definition: pcireg.h:54
gem5::igbreg::RxDesc::csum
uint16_t csum
Definition: i8254xGBe_defs.hh:202
gem5::igbreg::RxDesc::pkt
Addr pkt
Definition: i8254xGBe_defs.hh:209
gem5::igbreg::REG_STATUS
const uint32_t REG_STATUS
Definition: i8254xGBe_defs.hh:44
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::igbreg::Regs::rxdctl
RXDCTL rxdctl
Definition: i8254xGBe_defs.hh:779
gem5::igbreg::REG_ICR
const uint32_t REG_ICR
Definition: i8254xGBe_defs.hh:54
gem5::igbreg::Regs::tctl
TCTL tctl
Definition: i8254xGBe_defs.hh:682
gem5::igbreg::IntTypes
IntTypes
Definition: i8254xGBe_defs.hh:174
gem5::igbreg::REG_EERD
const uint32_t REG_EERD
Definition: i8254xGBe_defs.hh:46
gem5::igbreg::Regs::itr
ITR itr
Definition: i8254xGBe_defs.hh:614
gem5::igbreg::RXDP_IPV6
const uint16_t RXDP_IPV6
Definition: i8254xGBe_defs.hh:166
gem5::igbreg::REG_FCRTL
const uint32_t REG_FCRTL
Definition: i8254xGBe_defs.hh:67
gem5::igbreg::txd_op::tucss
int tucss(TxDesc *d)
Definition: i8254xGBe_defs.hh:373
gem5::igbreg::RXDEE_OSE
const uint16_t RXDEE_OSE
Definition: i8254xGBe_defs.hh:152
gem5::igbreg::Regs::RDH::ADD_FIELD32
ADD_FIELD32(rdh, 0, 16)
gem5::igbreg::REG_TCTL
const uint32_t REG_TCTL
Definition: i8254xGBe_defs.hh:78
gem5::igbreg::IT_GPI1
@ IT_GPI1
Definition: i8254xGBe_defs.hh:187
gem5::igbreg::Regs::Reg::operator()
T operator()()
Definition: i8254xGBe_defs.hh:441
gem5::igbreg::Regs::ICR::ADD_FIELD32
ADD_FIELD32(txdw, 0, 1) ADD_FIELD32(txqe
bitfield.hh
gem5::igbreg::Regs::FWSM::ADD_FIELD32
ADD_FIELD32(eep_fw_semaphore, 0, 1)
gem5::igbreg::Regs::SWSM::ADD_FIELD32
ADD_FIELD32(smbi, 0, 1)
gem5::igbreg::Regs::FCTTV::ADD_FIELD32
ADD_FIELD32(ttv, 0, 16)
gem5::igbreg::RxDesc::hdr
Addr hdr
Definition: i8254xGBe_defs.hh:210
gem5::igbreg::RXDEE_CE
const uint16_t RXDEE_CE
Definition: i8254xGBe_defs.hh:149
gem5::igbreg::Regs::TXDCA_CTL::ADD_FIELD32
ADD_FIELD32(cpu_mask, 0, 5)
gem5::igbreg::REG_IMC
const uint32_t REG_IMC
Definition: i8254xGBe_defs.hh:58
gem5::ArmISA::rxo
Bitfield< 27 > rxo
Definition: misc_types.hh:735
gem5::igbreg::txd_op::isTypes
bool isTypes(TxDesc *d, uint8_t t1, uint8_t t2)
Definition: i8254xGBe_defs.hh:255
gem5::igbreg::Regs::RCTL::ADD_FIELD32
ADD_FIELD32(rst, 0, 1)
gem5::igbreg::Regs::tdwba
uint64_t tdwba
Definition: i8254xGBe_defs.hh:873
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:64
gem5::igbreg::REG_RDLEN
const uint32_t REG_RDLEN
Definition: i8254xGBe_defs.hh:71
gem5::igbreg::REG_FCTTV
const uint32_t REG_FCTTV
Definition: i8254xGBe_defs.hh:61
gem5::igbreg::REG_RDBAH
const uint32_t REG_RDBAH
Definition: i8254xGBe_defs.hh:70
gem5::igbreg::txd_op::hdrlen
int hdrlen(TxDesc *d)
Definition: i8254xGBe_defs.hh:403
gem5::igbreg::RXDT_ADV_SPLIT_A
const uint8_t RXDT_ADV_SPLIT_A
Definition: i8254xGBe_defs.hh:161
gem5::igbreg::RXDP_IPV4E
const uint16_t RXDP_IPV4E
Definition: i8254xGBe_defs.hh:165
gem5::igbreg::EEPROM_RDSR_OPCODE_SPI
const uint8_t EEPROM_RDSR_OPCODE_SPI
Definition: i8254xGBe_defs.hh:108
gem5::igbreg::RXDEE_USE
const uint16_t RXDEE_USE
Definition: i8254xGBe_defs.hh:153
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::igbreg::Regs::RXDCTL::ADD_FIELD32
ADD_FIELD32(pthresh, 0, 6)
gem5::X86ISA::vme
Bitfield< 0 > vme
Definition: misc.hh:644
gem5::igbreg::txd_op::txsm
bool txsm(TxDesc *d)
Definition: i8254xGBe_defs.hh:358
gem5::igbreg::Regs::tdh
TDH tdh
Definition: i8254xGBe_defs.hh:820
gem5::igbreg::PHY_GSTATUS
const uint8_t PHY_GSTATUS
Definition: i8254xGBe_defs.hh:122
gem5::igbreg::Regs::Reg::operator()
void operator()(T d)
Definition: i8254xGBe_defs.hh:444
gem5::igbreg::REG_WUC
const uint32_t REG_WUC
Definition: i8254xGBe_defs.hh:99
gem5::igbreg::RXDS_DYNINT
const uint16_t RXDS_DYNINT
Definition: i8254xGBe_defs.hh:127
gem5::igbreg::txd_op::getCso
uint8_t getCso(TxDesc *d)
Definition: i8254xGBe_defs.hh:345
gem5::igbreg::Regs::MANC
Definition: i8254xGBe_defs.hh:905
gem5::igbreg::Regs::srrctl
SRRCTL srrctl
Definition: i8254xGBe_defs.hh:741
gem5::igbreg::REG_MANC
const uint32_t REG_MANC
Definition: i8254xGBe_defs.hh:102
gem5::igbreg::RXDS_IXSM
const uint16_t RXDS_IXSM
Definition: i8254xGBe_defs.hh:135
gem5::igbreg::Regs::TDH
Definition: i8254xGBe_defs.hh:814
gem5::igbreg::Regs::CTRL
Definition: i8254xGBe_defs.hh:456
gem5::igbreg::MULTICAST_TABLE_SIZE
const uint8_t MULTICAST_TABLE_SIZE
Definition: i8254xGBe_defs.hh:114
gem5::igbreg::txd_op::ixsm
bool ixsm(TxDesc *d)
Definition: i8254xGBe_defs.hh:357
gem5::igbreg::REG_FWSM
const uint32_t REG_FWSM
Definition: i8254xGBe_defs.hh:104
gem5::igbreg::txd_op::ifcs
bool ifcs(TxDesc *d)
Definition: i8254xGBe_defs.hh:320
gem5::igbreg::Regs::RFCTL
Definition: i8254xGBe_defs.hh:888
gem5::igbreg::RxDesc::id
uint16_t id
Definition: i8254xGBe_defs.hh:223
gem5::igbreg::RxDesc::buf
Addr buf
Definition: i8254xGBe_defs.hh:200
gem5::igbreg::RXDP_NFS
const uint16_t RXDP_NFS
Definition: i8254xGBe_defs.hh:171
gem5::igbreg::Regs::TADV::ADD_FIELD32
ADD_FIELD32(idv, 0, 16)
gem5::igbreg::Regs::RDH
Definition: i8254xGBe_defs.hh:743
gem5::igbreg::REG_AIFS
const uint32_t REG_AIFS
Definition: i8254xGBe_defs.hh:63
gem5::igbreg::Regs::sts
STATUS sts
Definition: i8254xGBe_defs.hh:511
gem5::igbreg::IT_RXCFG
@ IT_RXCFG
Definition: i8254xGBe_defs.hh:185
gem5::igbreg::REG_RDBAL
const uint32_t REG_RDBAL
Definition: i8254xGBe_defs.hh:69
gem5::igbreg::REG_RDH
const uint32_t REG_RDH
Definition: i8254xGBe_defs.hh:73
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::igbreg::REG_WUS
const uint32_t REG_WUS
Definition: i8254xGBe_defs.hh:101
gem5::igbreg::REG_ITR
const uint32_t REG_ITR
Definition: i8254xGBe_defs.hh:55
gem5::igbreg::Regs::Reg::operator==
bool operator==(T d)
Definition: i8254xGBe_defs.hh:443
gem5::ArmISA::en
Bitfield< 30 > en
Definition: misc_types.hh:461
gem5::igbreg::Regs::rxcsum
RXCSUM rxcsum
Definition: i8254xGBe_defs.hh:884
gem5::igbreg::EEPROM_SIZE
const uint8_t EEPROM_SIZE
Definition: i8254xGBe_defs.hh:109
gem5::igbreg::REG_LEDCTL
const uint32_t REG_LEDCTL
Definition: i8254xGBe_defs.hh:64
gem5::igbreg::Regs::RSRPD::ADD_FIELD32
ADD_FIELD32(idv, 0, 12)
gem5::igbreg::REG_RAH
const uint32_t REG_RAH
Definition: i8254xGBe_defs.hh:96
gem5::igbreg::REG_RFCTL
const uint32_t REG_RFCTL
Definition: i8254xGBe_defs.hh:93
gem5::igbreg::REG_TDLEN
const uint32_t REG_TDLEN
Definition: i8254xGBe_defs.hh:81
gem5::igbreg::RXDS_UDPCS
const uint16_t RXDS_UDPCS
Definition: i8254xGBe_defs.hh:133
gem5::igbreg::RXDE_IPE
const uint8_t RXDE_IPE
Definition: i8254xGBe_defs.hh:141
gem5::igbreg::Regs::FCTTV
Definition: i8254xGBe_defs.hh:658
gem5::igbreg::RXDT_LEGACY
const uint8_t RXDT_LEGACY
Definition: i8254xGBe_defs.hh:159
gem5::igbreg::Regs::rlpml
uint32_t rlpml
Definition: i8254xGBe_defs.hh:886
gem5::igbreg::Regs::manc
MANC manc
Definition: i8254xGBe_defs.hh:937
gem5::igbreg::EEPROM_READ_OPCODE_SPI
const uint8_t EEPROM_READ_OPCODE_SPI
Definition: i8254xGBe_defs.hh:107
gem5::igbreg::RXDT_ADV_ONEBUF
const uint8_t RXDT_ADV_ONEBUF
Definition: i8254xGBe_defs.hh:160
gem5::igbreg::Regs::SRRCTL::hdrLen
unsigned hdrLen()
Definition: i8254xGBe_defs.hh:739
gem5::igbreg::txd_op::getType
uint8_t getType(TxDesc *d)
Definition: i8254xGBe_defs.hh:252
gem5::igbreg::RXDS_VP
const uint16_t RXDS_VP
Definition: i8254xGBe_defs.hh:134
gem5::igbreg::Regs::rdtr
RDTR rdtr
Definition: i8254xGBe_defs.hh:766
gem5::igbreg::txd_op::ip
bool ip(TxDesc *d)
Definition: i8254xGBe_defs.hh:332
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::igbreg::RXDS_PIF
const uint16_t RXDS_PIF
Definition: i8254xGBe_defs.hh:130
gem5::ArmISA::rsvd
Bitfield< 29, 28 > rsvd
Definition: misc_types.hh:415
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::igbreg::RXDP_IPV4
const uint16_t RXDP_IPV4
Definition: i8254xGBe_defs.hh:164
gem5::igbreg::Regs::icr
ICR icr
Definition: i8254xGBe_defs.hh:603
gem5::igbreg::IT_TXQE
@ IT_TXQE
Definition: i8254xGBe_defs.hh:178
gem5::igbreg::REG_SWFWSYNC
const uint32_t REG_SWFWSYNC
Definition: i8254xGBe_defs.hh:105
gem5::igbreg::Regs::RADV::ADD_FIELD32
ADD_FIELD32(idv, 0, 16)
gem5::ArmISA::t2
Bitfield< 2 > t2
Definition: misc_types.hh:232
gem5::igbreg::IT_RXO
@ IT_RXO
Definition: i8254xGBe_defs.hh:182
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::igbreg::RxDesc::pkt_type
uint16_t pkt_type
Definition: i8254xGBe_defs.hh:215
gem5::igbreg::RXDE_CE
const uint8_t RXDE_CE
Definition: i8254xGBe_defs.hh:145
gem5::igbreg::REG_TXDCTL
const uint32_t REG_TXDCTL
Definition: i8254xGBe_defs.hh:86
gem5::statistics::enabled
bool enabled()
Definition: statistics.cc:286
gem5::igbreg::RxDesc::header_len
uint16_t header_len
Definition: i8254xGBe_defs.hh:217
gem5::igbreg::REG_TADV
const uint32_t REG_TADV
Definition: i8254xGBe_defs.hh:87
gem5::igbreg::Regs::Reg
Definition: i8254xGBe_defs.hh:438
gem5::igbreg::RxDesc::errors
uint8_t errors
Definition: i8254xGBe_defs.hh:204
gem5::igbreg::REG_TDT
const uint32_t REG_TDT
Definition: i8254xGBe_defs.hh:84
gem5::igbreg::RxDesc::rss_hash
uint32_t rss_hash
Definition: i8254xGBe_defs.hh:226
gem5::igbreg::Regs::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8254xGBe_defs.hh:1015
gem5::igbreg::REG_VET
const uint32_t REG_VET
Definition: i8254xGBe_defs.hh:52
gem5::igbreg::PHY_AGC
const uint8_t PHY_AGC
Definition: i8254xGBe_defs.hh:124
gem5::igbreg::Regs::ctrl_ext
CTRL_EXT ctrl_ext
Definition: i8254xGBe_defs.hh:565
gem5::igbreg::REG_TDWBAH
const uint32_t REG_TDWBAH
Definition: i8254xGBe_defs.hh:89
gem5::igbreg::IT_NONE
@ IT_NONE
Definition: i8254xGBe_defs.hh:176
gem5::igbreg::Regs::rsrpd
RSRPD rsrpd
Definition: i8254xGBe_defs.hh:795
gem5::igbreg::Regs::Reg::unserialize
void unserialize(CheckpointIn &cp)
Definition: i8254xGBe_defs.hh:450
gem5::igbreg::Regs::FWSM
Definition: i8254xGBe_defs.hh:950
gem5::igbreg::PHY_PID
const uint8_t PHY_PID
Definition: i8254xGBe_defs.hh:120
gem5::igbreg::Regs::RDLEN
Definition: i8254xGBe_defs.hh:722
gem5::igbreg::Regs::fcrtl
FCRTL fcrtl
Definition: i8254xGBe_defs.hh:701
gem5::igbreg::REG_MDIC
const uint32_t REG_MDIC
Definition: i8254xGBe_defs.hh:48
gem5::igbreg::IT_RXT
@ IT_RXT
Definition: i8254xGBe_defs.hh:183
gem5::igbreg::txd_op::TXD_ADVCNXT
const uint8_t TXD_ADVCNXT
Definition: i8254xGBe_defs.hh:248
gem5::igbreg::RXDS_DD
const uint16_t RXDS_DD
Definition: i8254xGBe_defs.hh:137
gem5::igbreg::Regs::EERD
Definition: i8254xGBe_defs.hh:532
gem5::igbreg::Regs::FCRTL
Definition: i8254xGBe_defs.hh:693
gem5::paramOut
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
gem5::igbreg::REG_EICR
const uint32_t REG_EICR
Definition: i8254xGBe_defs.hh:65
gem5::igbreg::RXDS_CRCV
const uint16_t RXDS_CRCV
Definition: i8254xGBe_defs.hh:129
gem5::igbreg::PHY_PSTATUS
const uint8_t PHY_PSTATUS
Definition: i8254xGBe_defs.hh:119
gem5::igbreg::Regs::FCRTL::ADD_FIELD32
ADD_FIELD32(rtl, 3, 28)
gem5::igbreg::STATS_REGS_SIZE
const uint32_t STATS_REGS_SIZE
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Definition: i8254xGBe_defs.hh:840
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Definition: i8254xGBe_defs.hh:132
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Definition: i8254xGBe_defs.hh:50
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Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
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Definition: i8254xGBe_defs.hh:121
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Definition: i8254xGBe_defs.hh:62
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Definition: i8254xGBe_defs.hh:644
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Definition: i8254xGBe_defs.hh:228
gem5::igbreg::Regs::RSRPD
Definition: i8254xGBe_defs.hh:789
gem5::igbreg::Regs::RCTL
Definition: i8254xGBe_defs.hh:621
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Definition: types.hh:84
gem5::igbreg::Regs::TIDV::ADD_FIELD32
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Definition: i8254xGBe_defs.hh:720
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