gem5  v21.1.0.2
i8254xGBe_defs.hh
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1 /*
2  * Copyright (c) 2006 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 /* @file
30  * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers.
31  */
32 #include "base/bitfield.hh"
33 #include "base/compiler.hh"
34 
35 namespace gem5
36 {
37 
38 GEM5_DEPRECATED_NAMESPACE(iGbReg, igbreg);
39 namespace igbreg
40 {
41 
42 // Registers used by the Intel GbE NIC
43 const uint32_t REG_CTRL = 0x00000;
44 const uint32_t REG_STATUS = 0x00008;
45 const uint32_t REG_EECD = 0x00010;
46 const uint32_t REG_EERD = 0x00014;
47 const uint32_t REG_CTRL_EXT = 0x00018;
48 const uint32_t REG_MDIC = 0x00020;
49 const uint32_t REG_FCAL = 0x00028;
50 const uint32_t REG_FCAH = 0x0002C;
51 const uint32_t REG_FCT = 0x00030;
52 const uint32_t REG_VET = 0x00038;
53 const uint32_t REG_PBA = 0x01000;
54 const uint32_t REG_ICR = 0x000C0;
55 const uint32_t REG_ITR = 0x000C4;
56 const uint32_t REG_ICS = 0x000C8;
57 const uint32_t REG_IMS = 0x000D0;
58 const uint32_t REG_IMC = 0x000D8;
59 const uint32_t REG_IAM = 0x000E0;
60 const uint32_t REG_RCTL = 0x00100;
61 const uint32_t REG_FCTTV = 0x00170;
62 const uint32_t REG_TIPG = 0x00410;
63 const uint32_t REG_AIFS = 0x00458;
64 const uint32_t REG_LEDCTL = 0x00e00;
65 const uint32_t REG_EICR = 0x01580;
66 const uint32_t REG_IVAR0 = 0x01700;
67 const uint32_t REG_FCRTL = 0x02160;
68 const uint32_t REG_FCRTH = 0x02168;
69 const uint32_t REG_RDBAL = 0x02800;
70 const uint32_t REG_RDBAH = 0x02804;
71 const uint32_t REG_RDLEN = 0x02808;
72 const uint32_t REG_SRRCTL = 0x0280C;
73 const uint32_t REG_RDH = 0x02810;
74 const uint32_t REG_RDT = 0x02818;
75 const uint32_t REG_RDTR = 0x02820;
76 const uint32_t REG_RXDCTL = 0x02828;
77 const uint32_t REG_RADV = 0x0282C;
78 const uint32_t REG_TCTL = 0x00400;
79 const uint32_t REG_TDBAL = 0x03800;
80 const uint32_t REG_TDBAH = 0x03804;
81 const uint32_t REG_TDLEN = 0x03808;
82 const uint32_t REG_TDH = 0x03810;
83 const uint32_t REG_TXDCA_CTL = 0x03814;
84 const uint32_t REG_TDT = 0x03818;
85 const uint32_t REG_TIDV = 0x03820;
86 const uint32_t REG_TXDCTL = 0x03828;
87 const uint32_t REG_TADV = 0x0382C;
88 const uint32_t REG_TDWBAL = 0x03838;
89 const uint32_t REG_TDWBAH = 0x0383C;
90 const uint32_t REG_CRCERRS = 0x04000;
91 const uint32_t REG_RXCSUM = 0x05000;
92 const uint32_t REG_RLPML = 0x05004;
93 const uint32_t REG_RFCTL = 0x05008;
94 const uint32_t REG_MTA = 0x05200;
95 const uint32_t REG_RAL = 0x05400;
96 const uint32_t REG_RAH = 0x05404;
97 const uint32_t REG_VFTA = 0x05600;
98 
99 const uint32_t REG_WUC = 0x05800;
100 const uint32_t REG_WUFC = 0x05808;
101 const uint32_t REG_WUS = 0x05810;
102 const uint32_t REG_MANC = 0x05820;
103 const uint32_t REG_SWSM = 0x05B50;
104 const uint32_t REG_FWSM = 0x05B54;
105 const uint32_t REG_SWFWSYNC = 0x05B5C;
106 
107 const uint8_t EEPROM_READ_OPCODE_SPI = 0x03;
108 const uint8_t EEPROM_RDSR_OPCODE_SPI = 0x05;
109 const uint8_t EEPROM_SIZE = 64;
110 const uint16_t EEPROM_CSUM = 0xBABA;
111 
112 const uint8_t VLAN_FILTER_TABLE_SIZE = 128;
113 const uint8_t RCV_ADDRESS_TABLE_SIZE = 24;
114 const uint8_t MULTICAST_TABLE_SIZE = 128;
115 const uint32_t STATS_REGS_SIZE = 0x228;
116 
117 
118 // Registers in that are accessed in the PHY
119 const uint8_t PHY_PSTATUS = 0x1;
120 const uint8_t PHY_PID = 0x2;
121 const uint8_t PHY_EPID = 0x3;
122 const uint8_t PHY_GSTATUS = 10;
123 const uint8_t PHY_EPSTATUS = 15;
124 const uint8_t PHY_AGC = 18;
125 
126 // Receive Descriptor Status Flags
127 const uint16_t RXDS_DYNINT = 0x800;
128 const uint16_t RXDS_UDPV = 0x400;
129 const uint16_t RXDS_CRCV = 0x100;
130 const uint16_t RXDS_PIF = 0x080;
131 const uint16_t RXDS_IPCS = 0x040;
132 const uint16_t RXDS_TCPCS = 0x020;
133 const uint16_t RXDS_UDPCS = 0x010;
134 const uint16_t RXDS_VP = 0x008;
135 const uint16_t RXDS_IXSM = 0x004;
136 const uint16_t RXDS_EOP = 0x002;
137 const uint16_t RXDS_DD = 0x001;
138 
139 // Receive Descriptor Error Flags
140 const uint8_t RXDE_RXE = 0x80;
141 const uint8_t RXDE_IPE = 0x40;
142 const uint8_t RXDE_TCPE = 0x20;
143 const uint8_t RXDE_SEQ = 0x04;
144 const uint8_t RXDE_SE = 0x02;
145 const uint8_t RXDE_CE = 0x01;
146 
147 // Receive Descriptor Extended Error Flags
148 const uint16_t RXDEE_HBO = 0x008;
149 const uint16_t RXDEE_CE = 0x010;
150 const uint16_t RXDEE_LE = 0x020;
151 const uint16_t RXDEE_PE = 0x080;
152 const uint16_t RXDEE_OSE = 0x100;
153 const uint16_t RXDEE_USE = 0x200;
154 const uint16_t RXDEE_TCPE = 0x400;
155 const uint16_t RXDEE_IPE = 0x800;
156 
157 
158 // Receive Descriptor Types
159 const uint8_t RXDT_LEGACY = 0x00;
160 const uint8_t RXDT_ADV_ONEBUF = 0x01;
161 const uint8_t RXDT_ADV_SPLIT_A = 0x05;
162 
163 // Receive Descriptor Packet Types
164 const uint16_t RXDP_IPV4 = 0x001;
165 const uint16_t RXDP_IPV4E = 0x002;
166 const uint16_t RXDP_IPV6 = 0x004;
167 const uint16_t RXDP_IPV6E = 0x008;
168 const uint16_t RXDP_TCP = 0x010;
169 const uint16_t RXDP_UDP = 0x020;
170 const uint16_t RXDP_SCTP = 0x040;
171 const uint16_t RXDP_NFS = 0x080;
172 
173 // Interrupt types
175 {
176  IT_NONE = 0x00000, //dummy value
177  IT_TXDW = 0x00001,
178  IT_TXQE = 0x00002,
179  IT_LSC = 0x00004,
180  IT_RXSEQ = 0x00008,
181  IT_RXDMT = 0x00010,
182  IT_RXO = 0x00040,
183  IT_RXT = 0x00080,
184  IT_MADC = 0x00200,
185  IT_RXCFG = 0x00400,
186  IT_GPI0 = 0x02000,
187  IT_GPI1 = 0x04000,
188  IT_TXDLOW = 0x08000,
189  IT_SRPD = 0x10000,
190  IT_ACK = 0x20000
191 };
192 
193 // Receive Descriptor struct
194 struct RxDesc
195 {
196  union
197  {
198  struct
199  {
201  uint16_t len;
202  uint16_t csum;
203  uint8_t status;
204  uint8_t errors;
205  uint16_t vlan;
206  } legacy;
207  struct
208  {
211  } adv_read;
212  struct
213  {
214  uint16_t rss_type:4;
215  uint16_t pkt_type:12;
216  uint16_t __reserved1:5;
217  uint16_t header_len:10;
218  uint16_t sph:1;
219  union
220  {
221  struct
222  {
223  uint16_t id;
224  uint16_t csum;
225  };
226  uint32_t rss_hash;
227  };
228  uint32_t status:20;
229  uint32_t errors:12;
230  uint16_t pkt_len;
231  uint16_t vlan_tag;
232  } adv_wb ;
233  };
234 };
235 
236 struct TxDesc
237 {
238  uint64_t d1;
239  uint64_t d2;
240 };
241 
242 GEM5_DEPRECATED_NAMESPACE(TxdOp, txd_op);
243 namespace txd_op
244 {
245 
246 const uint8_t TXD_CNXT = 0x0;
247 const uint8_t TXD_DATA = 0x1;
248 const uint8_t TXD_ADVCNXT = 0x2;
249 const uint8_t TXD_ADVDATA = 0x3;
250 
251 inline bool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); }
252 inline uint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); }
253 inline bool isType(TxDesc *d, uint8_t type) { return getType(d) == type; }
254 inline bool isTypes(TxDesc *d, uint8_t t1, uint8_t t2) { return isType(d, t1) || isType(d, t2); }
255 inline bool isAdvDesc(TxDesc *d) { return !isLegacy(d) && isTypes(d, TXD_ADVDATA,TXD_ADVCNXT); }
256 inline bool isContext(TxDesc *d) { return !isLegacy(d) && isTypes(d,TXD_CNXT, TXD_ADVCNXT); }
257 inline bool isData(TxDesc *d) { return !isLegacy(d) && isTypes(d, TXD_DATA, TXD_ADVDATA); }
258 
259 inline Addr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; }
260 inline Addr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); }
261 inline void setDd(TxDesc *d) { replaceBits(d->d2, 35, 32, 1ULL); }
262 
263 inline bool ide(TxDesc *d) { return bits(d->d2, 31,31) && (getType(d) == TXD_DATA || isLegacy(d)); }
264 inline bool vle(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); }
265 inline bool rs(TxDesc *d) { return bits(d->d2, 27,27); }
266 inline bool ic(TxDesc *d) { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); }
267 inline bool tse(TxDesc *d) {
268  if (isTypes(d, TXD_CNXT, TXD_DATA))
269  return bits(d->d2, 26,26);
270  if (isType(d, TXD_ADVDATA))
271  return bits(d->d2, 31, 31);
272  return false;
273 }
274 
275 inline bool ifcs(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 25,25); }
276 inline bool eop(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 24,24); }
277 inline bool ip(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 25,25); }
278 inline bool tcp(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 24,24); }
279 
280 inline uint8_t getCso(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 23,16); }
281 inline uint8_t getCss(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 47,40); }
282 
283 inline bool ixsm(TxDesc *d) { return isData(d) && bits(d->d2, 40,40); }
284 inline bool txsm(TxDesc *d) { return isData(d) && bits(d->d2, 41,41); }
285 
286 inline int tucse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,63,48); }
287 inline int tucso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,47,40); }
288 inline int tucss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,39,32); }
289 inline int ipcse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,31,16); }
290 inline int ipcso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,15,8); }
291 inline int ipcss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,7,0); }
292 inline int mss(TxDesc *d) { assert(isContext(d)); return bits(d->d2,63,48); }
293 inline int hdrlen(TxDesc *d) {
294  assert(isContext(d));
295  if (!isAdvDesc(d))
296  return bits(d->d2,47,40);
297  return bits(d->d2, 47,40) + bits(d->d1, 8,0) + bits(d->d1, 15, 9);
298 }
299 
300 inline int getTsoLen(TxDesc *d) { assert(isType(d, TXD_ADVDATA)); return bits(d->d2, 63,46); }
301 inline int utcmd(TxDesc *d) { assert(isContext(d)); return bits(d->d2,24,31); }
302 } // namespace txd_op
303 
304 
305 #define ADD_FIELD32(NAME, OFFSET, BITS) \
306  inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
307  inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
308 
309 #define ADD_FIELD64(NAME, OFFSET, BITS) \
310  inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
311  inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
312 
313 struct Regs : public Serializable
314 {
315  template<class T>
316  struct Reg
317  {
318  T _data;
319  T operator()() { return _data; }
320  const Reg<T> &operator=(T d) { _data = d; return *this;}
321  bool operator==(T d) { return d == _data; }
322  void operator()(T d) { _data = d; }
323  Reg() { _data = 0; }
324  void serialize(CheckpointOut &cp) const
325  {
327  }
329  {
331  }
332  };
333 
334  struct CTRL : public Reg<uint32_t>
335  {
336  // 0x0000 CTRL Register
338  ADD_FIELD32(fd,0,1); // full duplex
339  ADD_FIELD32(bem,1,1); // big endian mode
340  ADD_FIELD32(pcipr,2,1); // PCI priority
341  ADD_FIELD32(lrst,3,1); // link reset
342  ADD_FIELD32(tme,4,1); // test mode enable
343  ADD_FIELD32(asde,5,1); // Auto-speed detection
344  ADD_FIELD32(slu,6,1); // Set link up
345  ADD_FIELD32(ilos,7,1); // invert los-of-signal
346  ADD_FIELD32(speed,8,2); // speed selection bits
347  ADD_FIELD32(be32,10,1); // big endian mode 32
348  ADD_FIELD32(frcspd,11,1); // force speed
349  ADD_FIELD32(frcdpx,12,1); // force duplex
350  ADD_FIELD32(duden,13,1); // dock/undock enable
351  ADD_FIELD32(dudpol,14,1); // dock/undock polarity
352  ADD_FIELD32(fphyrst,15,1); // force phy reset
353  ADD_FIELD32(extlen,16,1); // external link status enable
354  ADD_FIELD32(rsvd,17,1); // reserved
355  ADD_FIELD32(sdp0d,18,1); // software controlled pin data
356  ADD_FIELD32(sdp1d,19,1); // software controlled pin data
357  ADD_FIELD32(sdp2d,20,1); // software controlled pin data
358  ADD_FIELD32(sdp3d,21,1); // software controlled pin data
359  ADD_FIELD32(sdp0i,22,1); // software controlled pin dir
360  ADD_FIELD32(sdp1i,23,1); // software controlled pin dir
361  ADD_FIELD32(sdp2i,24,1); // software controlled pin dir
362  ADD_FIELD32(sdp3i,25,1); // software controlled pin dir
363  ADD_FIELD32(rst,26,1); // reset
364  ADD_FIELD32(rfce,27,1); // receive flow control enable
365  ADD_FIELD32(tfce,28,1); // transmit flow control enable
366  ADD_FIELD32(rte,29,1); // routing tag enable
367  ADD_FIELD32(vme,30,1); // vlan enable
368  ADD_FIELD32(phyrst,31,1); // phy reset
369  };
371 
372  struct STATUS : public Reg<uint32_t>
373  {
374  // 0x0008 STATUS Register
376  ADD_FIELD32(fd,0,1); // full duplex
377  ADD_FIELD32(lu,1,1); // link up
378  ADD_FIELD32(func,2,2); // function id
379  ADD_FIELD32(txoff,4,1); // transmission paused
380  ADD_FIELD32(tbimode,5,1); // tbi mode
381  ADD_FIELD32(speed,6,2); // link speed
382  ADD_FIELD32(asdv,8,2); // auto speed detection value
383  ADD_FIELD32(mtxckok,10,1); // mtx clock running ok
384  ADD_FIELD32(pci66,11,1); // In 66Mhz pci slot
385  ADD_FIELD32(bus64,12,1); // in 64 bit slot
386  ADD_FIELD32(pcix,13,1); // Pci mode
387  ADD_FIELD32(pcixspd,14,2); // pci x speed
388  };
390 
391  struct EECD : public Reg<uint32_t>
392  {
393  // 0x0010 EECD Register
395  ADD_FIELD32(sk,0,1); // clack input to the eeprom
396  ADD_FIELD32(cs,1,1); // chip select to eeprom
397  ADD_FIELD32(din,2,1); // data input to eeprom
398  ADD_FIELD32(dout,3,1); // data output bit
399  ADD_FIELD32(fwe,4,2); // flash write enable
400  ADD_FIELD32(ee_req,6,1); // request eeprom access
401  ADD_FIELD32(ee_gnt,7,1); // grant eeprom access
402  ADD_FIELD32(ee_pres,8,1); // eeprom present
403  ADD_FIELD32(ee_size,9,1); // eeprom size
404  ADD_FIELD32(ee_sz1,10,1); // eeprom size
405  ADD_FIELD32(rsvd,11,2); // reserved
406  ADD_FIELD32(ee_type,13,1); // type of eeprom
407  } ;
409 
410  struct EERD : public Reg<uint32_t>
411  {
412  // 0x0014 EERD Register
414  ADD_FIELD32(start,0,1); // start read
415  ADD_FIELD32(done,1,1); // done read
416  ADD_FIELD32(addr,2,14); // address
417  ADD_FIELD32(data,16,16); // data
418  };
420 
421  struct CTRL_EXT : public Reg<uint32_t>
422  {
423  // 0x0018 CTRL_EXT Register
425  ADD_FIELD32(gpi_en,0,4); // enable interrupts from gpio
426  ADD_FIELD32(phyint,5,1); // reads the phy internal int status
427  ADD_FIELD32(sdp2_data,6,1); // data from gpio sdp
428  ADD_FIELD32(spd3_data,7,1); // data frmo gpio sdp
429  ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2
430  ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2
431  ADD_FIELD32(asdchk,12,1); // initiate auto-speed-detection
432  ADD_FIELD32(eerst,13,1); // reset the eeprom
433  ADD_FIELD32(spd_byps,15,1); // bypass speed select
434  ADD_FIELD32(ro_dis,17,1); // disable relaxed memory ordering
435  ADD_FIELD32(vreg,21,1); // power down the voltage regulator
436  ADD_FIELD32(link_mode,22,2); // interface to talk to the link
437  ADD_FIELD32(iame, 27,1); // interrupt acknowledge auto-mask ??
438  ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device
439  ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ??
440  };
442 
443  struct MDIC : public Reg<uint32_t>
444  {
445  // 0x0020 MDIC Register
447  ADD_FIELD32(data,0,16); // data
448  ADD_FIELD32(regadd,16,5); // register address
449  ADD_FIELD32(phyadd,21,5); // phy addresses
450  ADD_FIELD32(op,26,2); // opcode
451  ADD_FIELD32(r,28,1); // ready
452  ADD_FIELD32(i,29,1); // interrupt
453  ADD_FIELD32(e,30,1); // error
454  };
456 
457  struct ICR : public Reg<uint32_t>
458  {
459  // 0x00C0 ICR Register
461  ADD_FIELD32(txdw,0,1) // tx descr witten back
462  ADD_FIELD32(txqe,1,1) // tx queue empty
463  ADD_FIELD32(lsc,2,1) // link status change
464  ADD_FIELD32(rxseq,3,1) // rcv sequence error
465  ADD_FIELD32(rxdmt0,4,1) // rcv descriptor min thresh
466  ADD_FIELD32(rsvd1,5,1) // reserved
467  ADD_FIELD32(rxo,6,1) // receive overrunn
468  ADD_FIELD32(rxt0,7,1) // receiver timer interrupt
469  ADD_FIELD32(mdac,9,1) // mdi/o access complete
470  ADD_FIELD32(rxcfg,10,1) // recv /c/ ordered sets
471  ADD_FIELD32(phyint,12,1) // phy interrupt
472  ADD_FIELD32(gpi1,13,1) // gpi int 1
473  ADD_FIELD32(gpi2,14,1) // gpi int 2
474  ADD_FIELD32(txdlow,15,1) // transmit desc low thresh
475  ADD_FIELD32(srpd,16,1) // small receive packet detected
476  ADD_FIELD32(ack,17,1); // receive ack frame
477  ADD_FIELD32(int_assert, 31,1); // interrupt caused a system interrupt
478  };
480 
481  uint32_t imr; // register that contains the current interrupt mask
482 
483  struct ITR : public Reg<uint32_t>
484  {
485  // 0x00C4 ITR Register
487  ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval
488  // specified in 256ns interrupts
489  };
491 
492  // When CTRL_EXT.IAME and the ICR.INT_ASSERT is 1 an ICR read or write
493  // causes the IAM register contents to be written into the IMC
494  // automatically clearing all interrupts that have a bit in the IAM set
495  uint32_t iam;
496 
497  struct RCTL : public Reg<uint32_t>
498  {
499  // 0x0100 RCTL Register
501  ADD_FIELD32(rst,0,1); // Reset
502  ADD_FIELD32(en,1,1); // Enable
503  ADD_FIELD32(sbp,2,1); // Store bad packets
504  ADD_FIELD32(upe,3,1); // Unicast Promiscuous enabled
505  ADD_FIELD32(mpe,4,1); // Multicast promiscuous enabled
506  ADD_FIELD32(lpe,5,1); // long packet reception enabled
507  ADD_FIELD32(lbm,6,2); //
508  ADD_FIELD32(rdmts,8,2); //
509  ADD_FIELD32(mo,12,2); //
510  ADD_FIELD32(mdr,14,1); //
511  ADD_FIELD32(bam,15,1); //
512  ADD_FIELD32(bsize,16,2); //
513  ADD_FIELD32(vfe,18,1); //
514  ADD_FIELD32(cfien,19,1); //
515  ADD_FIELD32(cfi,20,1); //
516  ADD_FIELD32(dpf,22,1); // discard pause frames
517  ADD_FIELD32(pmcf,23,1); // pass mac control frames
518  ADD_FIELD32(bsex,25,1); // buffer size extension
519  ADD_FIELD32(secrc,26,1); // strip ethernet crc from incoming packet
520  unsigned descSize()
521  {
522  switch(bsize()) {
523  case 0: return bsex() == 0 ? 2048 : 0;
524  case 1: return bsex() == 0 ? 1024 : 16384;
525  case 2: return bsex() == 0 ? 512 : 8192;
526  case 3: return bsex() == 0 ? 256 : 4096;
527  default:
528  return 0;
529  }
530  }
531  };
533 
534  struct FCTTV : public Reg<uint32_t>
535  {
536  // 0x0170 FCTTV
538  ADD_FIELD32(ttv,0,16); // Transmit Timer Value
539  };
541 
542  struct TCTL : public Reg<uint32_t>
543  {
544  // 0x0400 TCTL Register
546  ADD_FIELD32(rst,0,1); // Reset
547  ADD_FIELD32(en,1,1); // Enable
548  ADD_FIELD32(bce,2,1); // busy check enable
549  ADD_FIELD32(psp,3,1); // pad short packets
550  ADD_FIELD32(ct,4,8); // collision threshold
551  ADD_FIELD32(cold,12,10); // collision distance
552  ADD_FIELD32(swxoff,22,1); // software xoff transmission
553  ADD_FIELD32(pbe,23,1); // packet burst enable
554  ADD_FIELD32(rtlc,24,1); // retransmit late collisions
555  ADD_FIELD32(nrtu,25,1); // on underrun no TX
556  ADD_FIELD32(mulr,26,1); // multiple request
557  };
559 
560  struct PBA : public Reg<uint32_t>
561  {
562  // 0x1000 PBA Register
564  ADD_FIELD32(rxa,0,16);
565  ADD_FIELD32(txa,16,16);
566  };
568 
569  struct FCRTL : public Reg<uint32_t>
570  {
571  // 0x2160 FCRTL Register
573  ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have
574  // a larger buffer
575  ADD_FIELD32(xone, 31,1);
576  };
578 
579  struct FCRTH : public Reg<uint32_t>
580  {
581  // 0x2168 FCRTL Register
583  ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have
584  //a larger buffer
585  ADD_FIELD32(xfce, 31,1);
586  };
588 
589  struct RDBA : public Reg<uint64_t>
590  {
591  // 0x2800 RDBA Register
593  ADD_FIELD64(rdbal,0,32); // base address of rx descriptor ring
594  ADD_FIELD64(rdbah,32,32); // base address of rx descriptor ring
595  };
597 
598  struct RDLEN : public Reg<uint32_t>
599  {
600  // 0x2808 RDLEN Register
602  ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
603  };
605 
606  struct SRRCTL : public Reg<uint32_t>
607  {
608  // 0x280C SRRCTL Register
610  ADD_FIELD32(pktlen, 0, 8);
611  ADD_FIELD32(hdrlen, 8, 8); // guess based on header, not documented
612  ADD_FIELD32(desctype, 25,3); // type of descriptor 000 legacy, 001 adv,
613  //101 hdr split
614  unsigned bufLen() { return pktlen() << 10; }
615  unsigned hdrLen() { return hdrlen() << 6; }
616  };
618 
619  struct RDH : public Reg<uint32_t>
620  {
621  // 0x2810 RDH Register
623  ADD_FIELD32(rdh,0,16); // head of the descriptor ring
624  };
626 
627  struct RDT : public Reg<uint32_t>
628  {
629  // 0x2818 RDT Register
631  ADD_FIELD32(rdt,0,16); // tail of the descriptor ring
632  };
634 
635  struct RDTR : public Reg<uint32_t>
636  {
637  // 0x2820 RDTR Register
639  ADD_FIELD32(delay,0,16); // receive delay timer
640  ADD_FIELD32(fpd, 31,1); // flush partial descriptor block ??
641  };
643 
644  struct RXDCTL : public Reg<uint32_t>
645  {
646  // 0x2828 RXDCTL Register
648  ADD_FIELD32(pthresh,0,6); // prefetch threshold, less that this
649  // consider prefetch
650  ADD_FIELD32(hthresh,8,6); // number of descriptors in host mem to
651  // consider prefetch
652  ADD_FIELD32(wthresh,16,6); // writeback threshold
653  ADD_FIELD32(gran,24,1); // granularity 0 = desc, 1 = cacheline
654  };
656 
657  struct RADV : public Reg<uint32_t>
658  {
659  // 0x282C RADV Register
661  ADD_FIELD32(idv,0,16); // absolute interrupt delay
662  };
664 
665  struct RSRPD : public Reg<uint32_t>
666  {
667  // 0x2C00 RSRPD Register
669  ADD_FIELD32(idv,0,12); // size to interrutp on small packets
670  };
672 
673  struct TDBA : public Reg<uint64_t>
674  {
675  // 0x3800 TDBAL Register
677  ADD_FIELD64(tdbal,0,32); // base address of transmit descriptor ring
678  ADD_FIELD64(tdbah,32,32); // base address of transmit descriptor ring
679  };
681 
682  struct TDLEN : public Reg<uint32_t>
683  {
684  // 0x3808 TDLEN Register
686  ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
687  };
689 
690  struct TDH : public Reg<uint32_t>
691  {
692  // 0x3810 TDH Register
694  ADD_FIELD32(tdh,0,16); // head of the descriptor ring
695  };
697 
698  struct TXDCA_CTL : public Reg<uint32_t>
699  {
700  // 0x3814 TXDCA_CTL Register
702  ADD_FIELD32(cpu_mask, 0, 5);
703  ADD_FIELD32(enabled, 5,1);
704  ADD_FIELD32(relax_ordering, 6, 1);
705  };
707 
708  struct TDT : public Reg<uint32_t>
709  {
710  // 0x3818 TDT Register
712  ADD_FIELD32(tdt,0,16); // tail of the descriptor ring
713  };
715 
716  struct TIDV : public Reg<uint32_t>
717  {
718  // 0x3820 TIDV Register
720  ADD_FIELD32(idv,0,16); // interrupt delay
721  };
723 
724  struct TXDCTL : public Reg<uint32_t>
725  {
726  // 0x3828 TXDCTL Register
728  ADD_FIELD32(pthresh, 0,6); // if number of descriptors control has is
729  // below this number, a prefetch is considered
730  ADD_FIELD32(hthresh,8,8); // number of valid descriptors is host memory
731  // before a prefetch is considered
732  ADD_FIELD32(wthresh,16,6); // number of descriptors to keep until
733  // writeback is considered
734  ADD_FIELD32(gran, 24,1); // granulatiry of above values (0 = cacheline,
735  // 1 == desscriptor)
736  ADD_FIELD32(lwthresh,25,7); // xmit descriptor low thresh, interrupt
737  // below this level
738  };
740 
741  struct TADV : public Reg<uint32_t>
742  {
743  // 0x382C TADV Register
745  ADD_FIELD32(idv,0,16); // absolute interrupt delay
746  };
748 /*
749  struct TDWBA : public Reg<uint64_t>
750  {
751  // 0x3838 TDWBA Register
752  using Reg<uint64_t>::operator=;
753  ADD_FIELD64(en,0,1); // enable transmit description ring address writeback
754  ADD_FIELD64(tdwbal,2,32); // base address of transmit descriptor ring address writeback
755  ADD_FIELD64(tdwbah,32,32); // base address of transmit descriptor ring
756  };
757  TDWBA tdwba;*/
758  uint64_t tdwba;
759 
760  struct RXCSUM : public Reg<uint32_t>
761  {
762  // 0x5000 RXCSUM Register
764  ADD_FIELD32(pcss,0,8);
765  ADD_FIELD32(ipofld,8,1);
766  ADD_FIELD32(tuofld,9,1);
767  ADD_FIELD32(pcsd, 13,1);
768  };
770 
771  uint32_t rlpml; // 0x5004 RLPML probably maximum accepted packet size
772 
773  struct RFCTL : public Reg<uint32_t>
774  {
775  // 0x5008 RFCTL Register
777  ADD_FIELD32(iscsi_dis,0,1);
778  ADD_FIELD32(iscsi_dwc,1,5);
779  ADD_FIELD32(nfsw_dis,6,1);
780  ADD_FIELD32(nfsr_dis,7,1);
781  ADD_FIELD32(nfs_ver,8,2);
782  ADD_FIELD32(ipv6_dis,10,1);
783  ADD_FIELD32(ipv6xsum_dis,11,1);
784  ADD_FIELD32(ackdis,13,1);
785  ADD_FIELD32(ipfrsp_dis,14,1);
786  ADD_FIELD32(exsten,15,1);
787  };
789 
790  struct MANC : public Reg<uint32_t>
791  {
792  // 0x5820 MANC Register
794  ADD_FIELD32(smbus,0,1); // SMBus enabled #####
795  ADD_FIELD32(asf,1,1); // ASF enabled #####
796  ADD_FIELD32(ronforce,2,1); // reset of force
797  ADD_FIELD32(rsvd,3,5); // reserved
798  ADD_FIELD32(rmcp1,8,1); // rcmp1 filtering
799  ADD_FIELD32(rmcp2,9,1); // rcmp2 filtering
800  ADD_FIELD32(ipv4,10,1); // enable ipv4
801  ADD_FIELD32(ipv6,11,1); // enable ipv6
802  ADD_FIELD32(snap,12,1); // accept snap
803  ADD_FIELD32(arp,13,1); // filter arp #####
804  ADD_FIELD32(neighbor,14,1); // neighbor discovery
805  ADD_FIELD32(arp_resp,15,1); // arp response
806  ADD_FIELD32(tcorst,16,1); // tco reset happened
807  ADD_FIELD32(rcvtco,17,1); // receive tco enabled ######
808  ADD_FIELD32(blkphyrst,18,1);// block phy resets ########
809  ADD_FIELD32(rcvall,19,1); // receive all
810  ADD_FIELD32(macaddrfltr,20,1); // mac address filtering ######
811  ADD_FIELD32(mng2host,21,1); // mng2 host packets #######
812  ADD_FIELD32(ipaddrfltr,22,1); // ip address filtering
813  ADD_FIELD32(xsumfilter,23,1); // checksum filtering
814  ADD_FIELD32(brfilter,24,1); // broadcast filtering
815  ADD_FIELD32(smbreq,25,1); // smb request
816  ADD_FIELD32(smbgnt,26,1); // smb grant
817  ADD_FIELD32(smbclkin,27,1); // smbclkin
818  ADD_FIELD32(smbdatain,28,1); // smbdatain
819  ADD_FIELD32(smbdataout,29,1); // smb data out
820  ADD_FIELD32(smbclkout,30,1); // smb clock out
821  };
823 
824  struct SWSM : public Reg<uint32_t>
825  {
826  // 0x5B50 SWSM register
828  ADD_FIELD32(smbi,0,1); // Semaphone bit
829  ADD_FIELD32(swesmbi, 1,1); // Software eeporm semaphore
830  ADD_FIELD32(wmng, 2,1); // Wake MNG clock
831  ADD_FIELD32(reserved, 3, 29);
832  };
834 
835  struct FWSM : public Reg<uint32_t>
836  {
837  // 0x5B54 FWSM register
839  ADD_FIELD32(eep_fw_semaphore,0,1);
840  ADD_FIELD32(fw_mode, 1,3);
841  ADD_FIELD32(ide, 4,1);
842  ADD_FIELD32(sol, 5,1);
843  ADD_FIELD32(eep_roload, 6,1);
844  ADD_FIELD32(reserved, 7,8);
845  ADD_FIELD32(fw_val_bit, 15, 1);
846  ADD_FIELD32(reset_cnt, 16, 3);
847  ADD_FIELD32(ext_err_ind, 19, 6);
848  ADD_FIELD32(reserved2, 25, 7);
849  };
851 
852  uint32_t sw_fw_sync;
853 
854  void serialize(CheckpointOut &cp) const override
855  {
856  paramOut(cp, "ctrl", ctrl._data);
857  paramOut(cp, "sts", sts._data);
858  paramOut(cp, "eecd", eecd._data);
859  paramOut(cp, "eerd", eerd._data);
860  paramOut(cp, "ctrl_ext", ctrl_ext._data);
861  paramOut(cp, "mdic", mdic._data);
862  paramOut(cp, "icr", icr._data);
864  paramOut(cp, "itr", itr._data);
866  paramOut(cp, "rctl", rctl._data);
867  paramOut(cp, "fcttv", fcttv._data);
868  paramOut(cp, "tctl", tctl._data);
869  paramOut(cp, "pba", pba._data);
870  paramOut(cp, "fcrtl", fcrtl._data);
871  paramOut(cp, "fcrth", fcrth._data);
872  paramOut(cp, "rdba", rdba._data);
873  paramOut(cp, "rdlen", rdlen._data);
874  paramOut(cp, "srrctl", srrctl._data);
875  paramOut(cp, "rdh", rdh._data);
876  paramOut(cp, "rdt", rdt._data);
877  paramOut(cp, "rdtr", rdtr._data);
878  paramOut(cp, "rxdctl", rxdctl._data);
879  paramOut(cp, "radv", radv._data);
880  paramOut(cp, "rsrpd", rsrpd._data);
881  paramOut(cp, "tdba", tdba._data);
882  paramOut(cp, "tdlen", tdlen._data);
883  paramOut(cp, "tdh", tdh._data);
884  paramOut(cp, "txdca_ctl", txdca_ctl._data);
885  paramOut(cp, "tdt", tdt._data);
886  paramOut(cp, "tidv", tidv._data);
887  paramOut(cp, "txdctl", txdctl._data);
888  paramOut(cp, "tadv", tadv._data);
889  //paramOut(cp, "tdwba", tdwba._data);
891  paramOut(cp, "rxcsum", rxcsum._data);
893  paramOut(cp, "rfctl", rfctl._data);
894  paramOut(cp, "manc", manc._data);
895  paramOut(cp, "swsm", swsm._data);
896  paramOut(cp, "fwsm", fwsm._data);
898  }
899 
900  void unserialize(CheckpointIn &cp) override
901  {
902  paramIn(cp, "ctrl", ctrl._data);
903  paramIn(cp, "sts", sts._data);
904  paramIn(cp, "eecd", eecd._data);
905  paramIn(cp, "eerd", eerd._data);
906  paramIn(cp, "ctrl_ext", ctrl_ext._data);
907  paramIn(cp, "mdic", mdic._data);
908  paramIn(cp, "icr", icr._data);
910  paramIn(cp, "itr", itr._data);
912  paramIn(cp, "rctl", rctl._data);
913  paramIn(cp, "fcttv", fcttv._data);
914  paramIn(cp, "tctl", tctl._data);
915  paramIn(cp, "pba", pba._data);
916  paramIn(cp, "fcrtl", fcrtl._data);
917  paramIn(cp, "fcrth", fcrth._data);
918  paramIn(cp, "rdba", rdba._data);
919  paramIn(cp, "rdlen", rdlen._data);
920  paramIn(cp, "srrctl", srrctl._data);
921  paramIn(cp, "rdh", rdh._data);
922  paramIn(cp, "rdt", rdt._data);
923  paramIn(cp, "rdtr", rdtr._data);
924  paramIn(cp, "rxdctl", rxdctl._data);
925  paramIn(cp, "radv", radv._data);
926  paramIn(cp, "rsrpd", rsrpd._data);
927  paramIn(cp, "tdba", tdba._data);
928  paramIn(cp, "tdlen", tdlen._data);
929  paramIn(cp, "tdh", tdh._data);
930  paramIn(cp, "txdca_ctl", txdca_ctl._data);
931  paramIn(cp, "tdt", tdt._data);
932  paramIn(cp, "tidv", tidv._data);
933  paramIn(cp, "txdctl", txdctl._data);
934  paramIn(cp, "tadv", tadv._data);
936  //paramIn(cp, "tdwba", tdwba._data);
937  paramIn(cp, "rxcsum", rxcsum._data);
939  paramIn(cp, "rfctl", rfctl._data);
940  paramIn(cp, "manc", manc._data);
941  paramIn(cp, "swsm", swsm._data);
942  paramIn(cp, "fwsm", fwsm._data);
944  }
945 };
946 
947 } // namespace igbreg
948 } // namespace gem5
gem5::igbreg::Regs::TDBA::ADD_FIELD64
ADD_FIELD64(tdbal, 0, 32)
gem5::igbreg::RXDS_IPCS
const uint16_t RXDS_IPCS
Definition: i8254xGBe_defs.hh:131
gem5::igbreg::Regs::rctl
RCTL rctl
Definition: i8254xGBe_defs.hh:532
gem5::igbreg::RXDEE_PE
const uint16_t RXDEE_PE
Definition: i8254xGBe_defs.hh:151
gem5::igbreg::RXDE_SE
const uint8_t RXDE_SE
Definition: i8254xGBe_defs.hh:144
gem5::igbreg::Regs::Reg::Reg
Reg()
Definition: i8254xGBe_defs.hh:323
gem5::igbreg::REG_FCT
const uint32_t REG_FCT
Definition: i8254xGBe_defs.hh:51
gem5::igbreg::Regs::Reg::serialize
void serialize(CheckpointOut &cp) const
Definition: i8254xGBe_defs.hh:324
gem5::igbreg::txd_op::ipcss
int ipcss(TxDesc *d)
Definition: i8254xGBe_defs.hh:291
gem5::igbreg::RXDE_RXE
const uint8_t RXDE_RXE
Definition: i8254xGBe_defs.hh:140
gem5::igbreg::Regs::SRRCTL::bufLen
unsigned bufLen()
Definition: i8254xGBe_defs.hh:614
gem5::igbreg::Regs::RDBA
Definition: i8254xGBe_defs.hh:589
gem5::igbreg::Regs::TCTL
Definition: i8254xGBe_defs.hh:542
gem5::igbreg::txd_op::mss
int mss(TxDesc *d)
Definition: i8254xGBe_defs.hh:292
gem5::igbreg::REG_RDTR
const uint32_t REG_RDTR
Definition: i8254xGBe_defs.hh:75
gem5::igbreg::RxDesc::len
uint16_t len
Definition: i8254xGBe_defs.hh:201
gem5::igbreg::txd_op::tucso
int tucso(TxDesc *d)
Definition: i8254xGBe_defs.hh:287
gem5::igbreg::txd_op::isContext
bool isContext(TxDesc *d)
Definition: i8254xGBe_defs.hh:256
gem5::igbreg::RxDesc::adv_read
struct gem5::igbreg::RxDesc::@79::@82 adv_read
gem5::igbreg::REG_CRCERRS
const uint32_t REG_CRCERRS
Definition: i8254xGBe_defs.hh:90
gem5::igbreg::RxDesc::status
uint8_t status
Definition: i8254xGBe_defs.hh:203
gem5::igbreg::REG_PBA
const uint32_t REG_PBA
Definition: i8254xGBe_defs.hh:53
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:444
gem5::igbreg::Regs::RXCSUM::ADD_FIELD32
ADD_FIELD32(pcss, 0, 8)
gem5::igbreg::Regs::tadv
TADV tadv
Definition: i8254xGBe_defs.hh:747
gem5::igbreg::Regs::SRRCTL
Definition: i8254xGBe_defs.hh:606
gem5::igbreg::REG_WUFC
const uint32_t REG_WUFC
Definition: i8254xGBe_defs.hh:100
gem5::igbreg::REG_MTA
const uint32_t REG_MTA
Definition: i8254xGBe_defs.hh:94
gem5::igbreg::Regs::imr
uint32_t imr
Definition: i8254xGBe_defs.hh:481
gem5::igbreg::REG_VFTA
const uint32_t REG_VFTA
Definition: i8254xGBe_defs.hh:97
gem5::igbreg::Regs::pba
PBA pba
Definition: i8254xGBe_defs.hh:567
gem5::igbreg::Regs::txdctl
TXDCTL txdctl
Definition: i8254xGBe_defs.hh:739
gem5::igbreg::RxDesc::legacy
struct gem5::igbreg::RxDesc::@79::@81 legacy
gem5::igbreg::Regs::TDLEN::ADD_FIELD32
ADD_FIELD32(len, 7, 13)
gem5::igbreg::Regs::ITR::ADD_FIELD32
ADD_FIELD32(interval, 0, 16)
gem5::igbreg::txd_op::TXD_DATA
const uint8_t TXD_DATA
Definition: i8254xGBe_defs.hh:247
gem5::igbreg::RXDP_UDP
const uint16_t RXDP_UDP
Definition: i8254xGBe_defs.hh:169
gem5::igbreg::REG_RXDCTL
const uint32_t REG_RXDCTL
Definition: i8254xGBe_defs.hh:76
gem5::igbreg::REG_SWSM
const uint32_t REG_SWSM
Definition: i8254xGBe_defs.hh:103
gem5::igbreg::Regs::TDBA
Definition: i8254xGBe_defs.hh:673
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::igbreg::RXDS_UDPV
const uint16_t RXDS_UDPV
Definition: i8254xGBe_defs.hh:128
gem5::igbreg::txd_op::ic
bool ic(TxDesc *d)
Definition: i8254xGBe_defs.hh:266
gem5::igbreg::RXDEE_HBO
const uint16_t RXDEE_HBO
Definition: i8254xGBe_defs.hh:148
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::ArmISA::fd
Bitfield< 14, 12 > fd
Definition: types.hh:150
gem5::igbreg::Regs::TDH::ADD_FIELD32
ADD_FIELD32(tdh, 0, 16)
gem5::igbreg::RXDE_TCPE
const uint8_t RXDE_TCPE
Definition: i8254xGBe_defs.hh:142
gem5::igbreg::Regs::TDT
Definition: i8254xGBe_defs.hh:708
gem5::igbreg::Regs::FCRTH::ADD_FIELD32
ADD_FIELD32(rth, 3, 13)
gem5::igbreg::Regs::PBA::ADD_FIELD32
ADD_FIELD32(rxa, 0, 16)
gem5::igbreg::REG_CTRL
const uint32_t REG_CTRL
Definition: i8254xGBe_defs.hh:43
gem5::igbreg::TxDesc
Definition: i8254xGBe_defs.hh:236
gem5::igbreg::txd_op::eop
bool eop(TxDesc *d)
Definition: i8254xGBe_defs.hh:276
gem5::igbreg::Regs::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8254xGBe_defs.hh:854
gem5::igbreg::Regs::Reg::operator=
const Reg< T > & operator=(T d)
Definition: i8254xGBe_defs.hh:320
gem5::igbreg::REG_TDWBAL
const uint32_t REG_TDWBAL
Definition: i8254xGBe_defs.hh:88
gem5::igbreg::Regs::ctrl
CTRL ctrl
Definition: i8254xGBe_defs.hh:370
gem5::igbreg::Regs::RDT
Definition: i8254xGBe_defs.hh:627
gem5::igbreg::Regs::RDBA::ADD_FIELD64
ADD_FIELD64(rdbal, 0, 32)
gem5::igbreg::Regs::fcrth
FCRTH fcrth
Definition: i8254xGBe_defs.hh:587
gem5::igbreg::REG_TIDV
const uint32_t REG_TIDV
Definition: i8254xGBe_defs.hh:85
gem5::igbreg::txd_op::rs
bool rs(TxDesc *d)
Definition: i8254xGBe_defs.hh:265
gem5::igbreg::Regs::RXCSUM
Definition: i8254xGBe_defs.hh:760
gem5::igbreg::RxDesc::rss_type
uint16_t rss_type
Definition: i8254xGBe_defs.hh:214
gem5::igbreg::RXDE_SEQ
const uint8_t RXDE_SEQ
Definition: i8254xGBe_defs.hh:143
gem5::igbreg::REG_RLPML
const uint32_t REG_RLPML
Definition: i8254xGBe_defs.hh:92
gem5::igbreg::IT_TXDW
@ IT_TXDW
Definition: i8254xGBe_defs.hh:177
gem5::igbreg::Regs::RDT::ADD_FIELD32
ADD_FIELD32(rdt, 0, 16)
gem5::igbreg::Regs::TCTL::ADD_FIELD32
ADD_FIELD32(rst, 0, 1)
gem5::igbreg::txd_op::isAdvDesc
bool isAdvDesc(TxDesc *d)
Definition: i8254xGBe_defs.hh:255
gem5::igbreg::txd_op::isData
bool isData(TxDesc *d)
Definition: i8254xGBe_defs.hh:257
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::igbreg::VLAN_FILTER_TABLE_SIZE
const uint8_t VLAN_FILTER_TABLE_SIZE
Definition: i8254xGBe_defs.hh:112
gem5::igbreg::IT_GPI0
@ IT_GPI0
Definition: i8254xGBe_defs.hh:186
gem5::igbreg::REG_IAM
const uint32_t REG_IAM
Definition: i8254xGBe_defs.hh:59
gem5::igbreg::txd_op::tucse
int tucse(TxDesc *d)
Definition: i8254xGBe_defs.hh:286
gem5::igbreg::Regs::RDLEN::ADD_FIELD32
ADD_FIELD32(len, 7, 13)
gem5::igbreg::Regs::fcttv
FCTTV fcttv
Definition: i8254xGBe_defs.hh:540
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::igbreg::txd_op::getCss
uint8_t getCss(TxDesc *d)
Definition: i8254xGBe_defs.hh:281
gem5::igbreg::REG_ICS
const uint32_t REG_ICS
Definition: i8254xGBe_defs.hh:56
gem5::igbreg::Regs::EECD
Definition: i8254xGBe_defs.hh:391
gem5::igbreg::Regs::mdic
MDIC mdic
Definition: i8254xGBe_defs.hh:455
gem5::igbreg::REG_RCTL
const uint32_t REG_RCTL
Definition: i8254xGBe_defs.hh:60
gem5::igbreg::Regs::PBA
Definition: i8254xGBe_defs.hh:560
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::igbreg::Regs::MANC::ADD_FIELD32
ADD_FIELD32(smbus, 0, 1)
gem5::igbreg::txd_op::ipcse
int ipcse(TxDesc *d)
Definition: i8254xGBe_defs.hh:289
gem5::igbreg::RXDP_SCTP
const uint16_t RXDP_SCTP
Definition: i8254xGBe_defs.hh:170
gem5::igbreg::txd_op::isType
bool isType(TxDesc *d, uint8_t type)
Definition: i8254xGBe_defs.hh:253
gem5::igbreg::REG_RADV
const uint32_t REG_RADV
Definition: i8254xGBe_defs.hh:77
gem5::igbreg::IT_LSC
@ IT_LSC
Definition: i8254xGBe_defs.hh:179
gem5::igbreg::RCV_ADDRESS_TABLE_SIZE
const uint8_t RCV_ADDRESS_TABLE_SIZE
Definition: i8254xGBe_defs.hh:113
gem5::igbreg::RxDesc
Definition: i8254xGBe_defs.hh:194
gem5::igbreg::Regs::SWSM
Definition: i8254xGBe_defs.hh:824
gem5::igbreg::Regs::ITR
Definition: i8254xGBe_defs.hh:483
gem5::igbreg::Regs::sw_fw_sync
uint32_t sw_fw_sync
Definition: i8254xGBe_defs.hh:852
gem5::igbreg::Regs::tdlen
TDLEN tdlen
Definition: i8254xGBe_defs.hh:688
gem5::igbreg::Regs::STATUS
Definition: i8254xGBe_defs.hh:372
gem5::igbreg::EEPROM_CSUM
const uint16_t EEPROM_CSUM
Definition: i8254xGBe_defs.hh:110
gem5::igbreg::RxDesc::pkt_len
uint16_t pkt_len
Definition: i8254xGBe_defs.hh:230
gem5::igbreg::REG_EECD
const uint32_t REG_EECD
Definition: i8254xGBe_defs.hh:45
gem5::igbreg::Regs::STATUS::ADD_FIELD32
ADD_FIELD32(fd, 0, 1)
gem5::igbreg::REG_RDT
const uint32_t REG_RDT
Definition: i8254xGBe_defs.hh:74
gem5::igbreg::txd_op::ipcso
int ipcso(TxDesc *d)
Definition: i8254xGBe_defs.hh:290
gem5::igbreg::Regs::MDIC
Definition: i8254xGBe_defs.hh:443
gem5::igbreg::REG_IVAR0
const uint32_t REG_IVAR0
Definition: i8254xGBe_defs.hh:66
gem5::igbreg::txd_op::TXD_CNXT
const uint8_t TXD_CNXT
Definition: i8254xGBe_defs.hh:246
gem5::igbreg::IT_MADC
@ IT_MADC
Definition: i8254xGBe_defs.hh:184
gem5::igbreg::Regs::CTRL_EXT
Definition: i8254xGBe_defs.hh:421
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::igbreg::RXDEE_TCPE
const uint16_t RXDEE_TCPE
Definition: i8254xGBe_defs.hh:154
gem5::igbreg::txd_op::TXD_ADVDATA
const uint8_t TXD_ADVDATA
Definition: i8254xGBe_defs.hh:249
gem5::igbreg::txd_op::setDd
void setDd(TxDesc *d)
Definition: i8254xGBe_defs.hh:261
gem5::igbreg::Regs::rdh
RDH rdh
Definition: i8254xGBe_defs.hh:625
gem5::igbreg::Regs::CTRL_EXT::ADD_FIELD32
ADD_FIELD32(gpi_en, 0, 4)
gem5::igbreg::RxDesc::vlan_tag
uint16_t vlan_tag
Definition: i8254xGBe_defs.hh:231
gem5::igbreg::Regs::RFCTL::ADD_FIELD32
ADD_FIELD32(iscsi_dis, 0, 1)
gem5::igbreg::REG_FCAL
const uint32_t REG_FCAL
Definition: i8254xGBe_defs.hh:49
gem5::igbreg::IT_TXDLOW
@ IT_TXDLOW
Definition: i8254xGBe_defs.hh:188
gem5::igbreg::Regs::tdba
TDBA tdba
Definition: i8254xGBe_defs.hh:680
gem5::igbreg::Regs::FCRTH
Definition: i8254xGBe_defs.hh:579
gem5::igbreg::Regs::eecd
EECD eecd
Definition: i8254xGBe_defs.hh:408
gem5::igbreg::Regs::TDT::ADD_FIELD32
ADD_FIELD32(tdt, 0, 16)
gem5::igbreg::Regs::EERD::ADD_FIELD32
ADD_FIELD32(start, 0, 1)
gem5::igbreg::IT_RXDMT
@ IT_RXDMT
Definition: i8254xGBe_defs.hh:181
gem5::igbreg::txd_op::getBuf
Addr getBuf(TxDesc *d)
Definition: i8254xGBe_defs.hh:259
gem5::ArmISA::t1
Bitfield< 1 > t1
Definition: misc_types.hh:232
gem5::igbreg::REG_TXDCA_CTL
const uint32_t REG_TXDCA_CTL
Definition: i8254xGBe_defs.hh:83
gem5::igbreg::Regs::radv
RADV radv
Definition: i8254xGBe_defs.hh:663
gem5::igbreg::txd_op::utcmd
int utcmd(TxDesc *d)
Definition: i8254xGBe_defs.hh:301
gem5::igbreg::RXDP_IPV6E
const uint16_t RXDP_IPV6E
Definition: i8254xGBe_defs.hh:167
reserved
reserved
Definition: pcireg.h:54
gem5::igbreg::RxDesc::csum
uint16_t csum
Definition: i8254xGBe_defs.hh:202
gem5::igbreg::RxDesc::pkt
Addr pkt
Definition: i8254xGBe_defs.hh:209
gem5::igbreg::REG_STATUS
const uint32_t REG_STATUS
Definition: i8254xGBe_defs.hh:44
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::igbreg::Regs::rxdctl
RXDCTL rxdctl
Definition: i8254xGBe_defs.hh:655
gem5::igbreg::REG_ICR
const uint32_t REG_ICR
Definition: i8254xGBe_defs.hh:54
gem5::igbreg::Regs::tctl
TCTL tctl
Definition: i8254xGBe_defs.hh:558
gem5::igbreg::IntTypes
IntTypes
Definition: i8254xGBe_defs.hh:174
gem5::igbreg::REG_EERD
const uint32_t REG_EERD
Definition: i8254xGBe_defs.hh:46
gem5::igbreg::Regs::itr
ITR itr
Definition: i8254xGBe_defs.hh:490
gem5::igbreg::RXDP_IPV6
const uint16_t RXDP_IPV6
Definition: i8254xGBe_defs.hh:166
gem5::igbreg::REG_FCRTL
const uint32_t REG_FCRTL
Definition: i8254xGBe_defs.hh:67
gem5::igbreg::txd_op::tucss
int tucss(TxDesc *d)
Definition: i8254xGBe_defs.hh:288
gem5::igbreg::RXDEE_OSE
const uint16_t RXDEE_OSE
Definition: i8254xGBe_defs.hh:152
gem5::igbreg::Regs::RDH::ADD_FIELD32
ADD_FIELD32(rdh, 0, 16)
gem5::igbreg::REG_TCTL
const uint32_t REG_TCTL
Definition: i8254xGBe_defs.hh:78
gem5::igbreg::IT_GPI1
@ IT_GPI1
Definition: i8254xGBe_defs.hh:187
gem5::igbreg::Regs::Reg::operator()
T operator()()
Definition: i8254xGBe_defs.hh:319
gem5::igbreg::Regs::ICR::ADD_FIELD32
ADD_FIELD32(txdw, 0, 1) ADD_FIELD32(txqe
bitfield.hh
gem5::igbreg::Regs::FWSM::ADD_FIELD32
ADD_FIELD32(eep_fw_semaphore, 0, 1)
gem5::igbreg::Regs::SWSM::ADD_FIELD32
ADD_FIELD32(smbi, 0, 1)
gem5::igbreg::Regs::FCTTV::ADD_FIELD32
ADD_FIELD32(ttv, 0, 16)
gem5::igbreg::RxDesc::hdr
Addr hdr
Definition: i8254xGBe_defs.hh:210
gem5::igbreg::RXDEE_CE
const uint16_t RXDEE_CE
Definition: i8254xGBe_defs.hh:149
gem5::igbreg::Regs::TXDCA_CTL::ADD_FIELD32
ADD_FIELD32(cpu_mask, 0, 5)
gem5::igbreg::REG_IMC
const uint32_t REG_IMC
Definition: i8254xGBe_defs.hh:58
gem5::ArmISA::rxo
Bitfield< 27 > rxo
Definition: misc_types.hh:734
gem5::igbreg::txd_op::isTypes
bool isTypes(TxDesc *d, uint8_t t1, uint8_t t2)
Definition: i8254xGBe_defs.hh:254
gem5::igbreg::Regs::RCTL::ADD_FIELD32
ADD_FIELD32(rst, 0, 1)
gem5::igbreg::Regs::tdwba
uint64_t tdwba
Definition: i8254xGBe_defs.hh:758
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:63
gem5::igbreg::REG_RDLEN
const uint32_t REG_RDLEN
Definition: i8254xGBe_defs.hh:71
gem5::igbreg::REG_FCTTV
const uint32_t REG_FCTTV
Definition: i8254xGBe_defs.hh:61
gem5::igbreg::REG_RDBAH
const uint32_t REG_RDBAH
Definition: i8254xGBe_defs.hh:70
gem5::igbreg::txd_op::hdrlen
int hdrlen(TxDesc *d)
Definition: i8254xGBe_defs.hh:293
gem5::igbreg::RXDT_ADV_SPLIT_A
const uint8_t RXDT_ADV_SPLIT_A
Definition: i8254xGBe_defs.hh:161
gem5::igbreg::RXDP_IPV4E
const uint16_t RXDP_IPV4E
Definition: i8254xGBe_defs.hh:165
gem5::igbreg::EEPROM_RDSR_OPCODE_SPI
const uint8_t EEPROM_RDSR_OPCODE_SPI
Definition: i8254xGBe_defs.hh:108
gem5::igbreg::RXDEE_USE
const uint16_t RXDEE_USE
Definition: i8254xGBe_defs.hh:153
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::igbreg::Regs::RXDCTL::ADD_FIELD32
ADD_FIELD32(pthresh, 0, 6)
gem5::X86ISA::vme
Bitfield< 0 > vme
Definition: misc.hh:644
gem5::igbreg::txd_op::txsm
bool txsm(TxDesc *d)
Definition: i8254xGBe_defs.hh:284
gem5::igbreg::Regs::tdh
TDH tdh
Definition: i8254xGBe_defs.hh:696
gem5::igbreg::PHY_GSTATUS
const uint8_t PHY_GSTATUS
Definition: i8254xGBe_defs.hh:122
gem5::igbreg::Regs::Reg::operator()
void operator()(T d)
Definition: i8254xGBe_defs.hh:322
gem5::igbreg::REG_WUC
const uint32_t REG_WUC
Definition: i8254xGBe_defs.hh:99
gem5::igbreg::RXDS_DYNINT
const uint16_t RXDS_DYNINT
Definition: i8254xGBe_defs.hh:127
gem5::igbreg::txd_op::getCso
uint8_t getCso(TxDesc *d)
Definition: i8254xGBe_defs.hh:280
gem5::igbreg::Regs::MANC
Definition: i8254xGBe_defs.hh:790
gem5::igbreg::Regs::srrctl
SRRCTL srrctl
Definition: i8254xGBe_defs.hh:617
gem5::igbreg::REG_MANC
const uint32_t REG_MANC
Definition: i8254xGBe_defs.hh:102
gem5::igbreg::RXDS_IXSM
const uint16_t RXDS_IXSM
Definition: i8254xGBe_defs.hh:135
gem5::igbreg::Regs::TDH
Definition: i8254xGBe_defs.hh:690
gem5::igbreg::Regs::CTRL
Definition: i8254xGBe_defs.hh:334
gem5::igbreg::MULTICAST_TABLE_SIZE
const uint8_t MULTICAST_TABLE_SIZE
Definition: i8254xGBe_defs.hh:114
gem5::igbreg::txd_op::ixsm
bool ixsm(TxDesc *d)
Definition: i8254xGBe_defs.hh:283
gem5::igbreg::REG_FWSM
const uint32_t REG_FWSM
Definition: i8254xGBe_defs.hh:104
gem5::igbreg::txd_op::ifcs
bool ifcs(TxDesc *d)
Definition: i8254xGBe_defs.hh:275
gem5::igbreg::Regs::RFCTL
Definition: i8254xGBe_defs.hh:773
gem5::igbreg::RxDesc::id
uint16_t id
Definition: i8254xGBe_defs.hh:223
gem5::igbreg::RxDesc::buf
Addr buf
Definition: i8254xGBe_defs.hh:200
gem5::igbreg::RXDP_NFS
const uint16_t RXDP_NFS
Definition: i8254xGBe_defs.hh:171
gem5::igbreg::Regs::TADV::ADD_FIELD32
ADD_FIELD32(idv, 0, 16)
gem5::igbreg::Regs::RDH
Definition: i8254xGBe_defs.hh:619
gem5::igbreg::REG_AIFS
const uint32_t REG_AIFS
Definition: i8254xGBe_defs.hh:63
gem5::igbreg::Regs::sts
STATUS sts
Definition: i8254xGBe_defs.hh:389
gem5::igbreg::IT_RXCFG
@ IT_RXCFG
Definition: i8254xGBe_defs.hh:185
gem5::igbreg::REG_RDBAL
const uint32_t REG_RDBAL
Definition: i8254xGBe_defs.hh:69
gem5::igbreg::REG_RDH
const uint32_t REG_RDH
Definition: i8254xGBe_defs.hh:73
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::igbreg::REG_WUS
const uint32_t REG_WUS
Definition: i8254xGBe_defs.hh:101
gem5::igbreg::REG_ITR
const uint32_t REG_ITR
Definition: i8254xGBe_defs.hh:55
gem5::igbreg::Regs::Reg::operator==
bool operator==(T d)
Definition: i8254xGBe_defs.hh:321
gem5::ArmISA::en
Bitfield< 30 > en
Definition: misc_types.hh:460
gem5::igbreg::Regs::rxcsum
RXCSUM rxcsum
Definition: i8254xGBe_defs.hh:769
gem5::igbreg::EEPROM_SIZE
const uint8_t EEPROM_SIZE
Definition: i8254xGBe_defs.hh:109
gem5::igbreg::REG_LEDCTL
const uint32_t REG_LEDCTL
Definition: i8254xGBe_defs.hh:64
gem5::igbreg::Regs::RSRPD::ADD_FIELD32
ADD_FIELD32(idv, 0, 12)
gem5::igbreg::REG_RAH
const uint32_t REG_RAH
Definition: i8254xGBe_defs.hh:96
gem5::igbreg::REG_RFCTL
const uint32_t REG_RFCTL
Definition: i8254xGBe_defs.hh:93
gem5::igbreg::REG_TDLEN
const uint32_t REG_TDLEN
Definition: i8254xGBe_defs.hh:81
gem5::igbreg::RXDS_UDPCS
const uint16_t RXDS_UDPCS
Definition: i8254xGBe_defs.hh:133
gem5::igbreg::RXDE_IPE
const uint8_t RXDE_IPE
Definition: i8254xGBe_defs.hh:141
gem5::igbreg::Regs::FCTTV
Definition: i8254xGBe_defs.hh:534
gem5::igbreg::RXDT_LEGACY
const uint8_t RXDT_LEGACY
Definition: i8254xGBe_defs.hh:159
gem5::igbreg::Regs::rlpml
uint32_t rlpml
Definition: i8254xGBe_defs.hh:771
gem5::igbreg::Regs::manc
MANC manc
Definition: i8254xGBe_defs.hh:822
gem5::igbreg::EEPROM_READ_OPCODE_SPI
const uint8_t EEPROM_READ_OPCODE_SPI
Definition: i8254xGBe_defs.hh:107
gem5::igbreg::RXDT_ADV_ONEBUF
const uint8_t RXDT_ADV_ONEBUF
Definition: i8254xGBe_defs.hh:160
gem5::igbreg::Regs::SRRCTL::hdrLen
unsigned hdrLen()
Definition: i8254xGBe_defs.hh:615
gem5::igbreg::txd_op::getType
uint8_t getType(TxDesc *d)
Definition: i8254xGBe_defs.hh:252
gem5::igbreg::RXDS_VP
const uint16_t RXDS_VP
Definition: i8254xGBe_defs.hh:134
gem5::igbreg::Regs::rdtr
RDTR rdtr
Definition: i8254xGBe_defs.hh:642
gem5::igbreg::txd_op::ip
bool ip(TxDesc *d)
Definition: i8254xGBe_defs.hh:277
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::igbreg::RXDS_PIF
const uint16_t RXDS_PIF
Definition: i8254xGBe_defs.hh:130
gem5::ArmISA::rsvd
Bitfield< 29, 28 > rsvd
Definition: misc_types.hh:414
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::igbreg::RXDP_IPV4
const uint16_t RXDP_IPV4
Definition: i8254xGBe_defs.hh:164
gem5::igbreg::Regs::icr
ICR icr
Definition: i8254xGBe_defs.hh:479
gem5::igbreg::IT_TXQE
@ IT_TXQE
Definition: i8254xGBe_defs.hh:178
gem5::igbreg::REG_SWFWSYNC
const uint32_t REG_SWFWSYNC
Definition: i8254xGBe_defs.hh:105
gem5::igbreg::Regs::RADV::ADD_FIELD32
ADD_FIELD32(idv, 0, 16)
gem5::ArmISA::t2
Bitfield< 2 > t2
Definition: misc_types.hh:231
gem5::igbreg::IT_RXO
@ IT_RXO
Definition: i8254xGBe_defs.hh:182
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::igbreg::RxDesc::pkt_type
uint16_t pkt_type
Definition: i8254xGBe_defs.hh:215
gem5::igbreg::RXDE_CE
const uint8_t RXDE_CE
Definition: i8254xGBe_defs.hh:145
gem5::igbreg::REG_TXDCTL
const uint32_t REG_TXDCTL
Definition: i8254xGBe_defs.hh:86
gem5::statistics::enabled
bool enabled()
Definition: statistics.cc:280
gem5::igbreg::RxDesc::header_len
uint16_t header_len
Definition: i8254xGBe_defs.hh:217
gem5::igbreg::REG_TADV
const uint32_t REG_TADV
Definition: i8254xGBe_defs.hh:87
gem5::igbreg::Regs::Reg
Definition: i8254xGBe_defs.hh:316
gem5::igbreg::RxDesc::errors
uint8_t errors
Definition: i8254xGBe_defs.hh:204
gem5::igbreg::REG_TDT
const uint32_t REG_TDT
Definition: i8254xGBe_defs.hh:84
gem5::igbreg::RxDesc::rss_hash
uint32_t rss_hash
Definition: i8254xGBe_defs.hh:226
gem5::igbreg::Regs::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8254xGBe_defs.hh:900
gem5::igbreg::REG_VET
const uint32_t REG_VET
Definition: i8254xGBe_defs.hh:52
gem5::igbreg::PHY_AGC
const uint8_t PHY_AGC
Definition: i8254xGBe_defs.hh:124
gem5::igbreg::Regs::ctrl_ext
CTRL_EXT ctrl_ext
Definition: i8254xGBe_defs.hh:441
gem5::igbreg::REG_TDWBAH
const uint32_t REG_TDWBAH
Definition: i8254xGBe_defs.hh:89
gem5::igbreg::IT_NONE
@ IT_NONE
Definition: i8254xGBe_defs.hh:176
gem5::igbreg::Regs::rsrpd
RSRPD rsrpd
Definition: i8254xGBe_defs.hh:671
gem5::igbreg::Regs::Reg::unserialize
void unserialize(CheckpointIn &cp)
Definition: i8254xGBe_defs.hh:328
gem5::igbreg::Regs::FWSM
Definition: i8254xGBe_defs.hh:835
gem5::igbreg::PHY_PID
const uint8_t PHY_PID
Definition: i8254xGBe_defs.hh:120
gem5::igbreg::Regs::RDLEN
Definition: i8254xGBe_defs.hh:598
gem5::igbreg::Regs::fcrtl
FCRTL fcrtl
Definition: i8254xGBe_defs.hh:577
gem5::igbreg::REG_MDIC
const uint32_t REG_MDIC
Definition: i8254xGBe_defs.hh:48
gem5::igbreg::IT_RXT
@ IT_RXT
Definition: i8254xGBe_defs.hh:183
gem5::igbreg::txd_op::TXD_ADVCNXT
const uint8_t TXD_ADVCNXT
Definition: i8254xGBe_defs.hh:248
gem5::igbreg::RXDS_DD
const uint16_t RXDS_DD
Definition: i8254xGBe_defs.hh:137
gem5::igbreg::Regs::EERD
Definition: i8254xGBe_defs.hh:410
gem5::igbreg::Regs::FCRTL
Definition: i8254xGBe_defs.hh:569
gem5::paramOut
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
gem5::igbreg::REG_EICR
const uint32_t REG_EICR
Definition: i8254xGBe_defs.hh:65
gem5::igbreg::RXDS_CRCV
const uint16_t RXDS_CRCV
Definition: i8254xGBe_defs.hh:129
gem5::igbreg::PHY_PSTATUS
const uint8_t PHY_PSTATUS
Definition: i8254xGBe_defs.hh:119
gem5::igbreg::Regs::FCRTL::ADD_FIELD32
ADD_FIELD32(rtl, 3, 28)
gem5::igbreg::STATS_REGS_SIZE
const uint32_t STATS_REGS_SIZE
Definition: i8254xGBe_defs.hh:115
gem5::igbreg::txd_op::isLegacy
bool isLegacy(TxDesc *d)
Definition: i8254xGBe_defs.hh:251
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Definition: i8254xGBe_defs.hh:833
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Definition: i8254xGBe_defs.hh:260
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Definition: i8254xGBe_defs.hh:82
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Definition: i8254xGBe_defs.hh:457
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Definition: i8254xGBe_defs.hh:318
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gem5::igbreg::IT_SRPD
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Definition: i8254xGBe_defs.hh:189
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Definition: i8254xGBe_defs.hh:239
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Definition: types.cc:72
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Definition: i8254xGBe_defs.hh:604
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Definition: i8254xGBe_defs.hh:300
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Definition: i8254xGBe_defs.hh:263
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Definition: i8254xGBe_defs.hh:68
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Definition: i8254xGBe_defs.hh:657
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Definition: i8254xGBe_defs.hh:155
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Definition: i8254xGBe_defs.hh:79
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Definition: i8254xGBe_defs.hh:714
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Definition: i8254xGBe_defs.hh:313
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Definition: i8254xGBe_defs.hh:72
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Definition: i8254xGBe_defs.hh:267
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Definition: i8254xGBe_defs.hh:229
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Definition: i8254xGBe_defs.hh:123
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Definition: i8254xGBe_defs.hh:682
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Definition: i8254xGBe_defs.hh:216
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Definition: i8254xGBe_defs.hh:91
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Definition: i8254xGBe_defs.hh:238
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Definition: i8254xGBe_defs.hh:706
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Definition: i8254xGBe_defs.hh:150
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Definition: serialize.hh:66
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Definition: i8254xGBe_defs.hh:180
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Definition: i8254xGBe_defs.hh:168
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Definition: i8254xGBe_defs.hh:95
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Definition: i8254xGBe_defs.hh:495
gem5::igbreg::Regs::TADV
Definition: i8254xGBe_defs.hh:741
gem5::igbreg::REG_IMS
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Definition: i8254xGBe_defs.hh:57
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Definition: i8254xGBe_defs.hh:80
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Definition: i8254xGBe_defs.hh:724
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Definition: i8254xGBe_defs.hh:47
gem5::igbreg::Regs::TIDV
Definition: i8254xGBe_defs.hh:716
gem5::igbreg::Regs::tidv
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Definition: i8254xGBe_defs.hh:722
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Definition: i8254xGBe_defs.hh:218
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Definition: i8254xGBe_defs.hh:850
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Definition: i8254xGBe_defs.hh:132
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Definition: i8254xGBe_defs.hh:50
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Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
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Definition: i8254xGBe_defs.hh:633
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Definition: i8254xGBe_defs.hh:136
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Definition: i8254xGBe_defs.hh:264
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Definition: i8254xGBe_defs.hh:788
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Definition: i8254xGBe_defs.hh:205
gem5::igbreg::Regs::TXDCA_CTL
Definition: i8254xGBe_defs.hh:698
gem5::igbreg::Regs::RDTR
Definition: i8254xGBe_defs.hh:635
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Definition: i8254xGBe_defs.hh:419
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Definition: types.hh:83
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Definition: i8254xGBe_defs.hh:190
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Definition: i8254xGBe_defs.hh:644
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Definition: i8254xGBe_defs.hh:121
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Definition: i8254xGBe_defs.hh:278
gem5::igbreg::REG_TIPG
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Definition: i8254xGBe_defs.hh:62
gem5::igbreg::Regs::RCTL::descSize
unsigned descSize()
Definition: i8254xGBe_defs.hh:520
gem5::igbreg::RxDesc::status
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Definition: i8254xGBe_defs.hh:228
gem5::igbreg::Regs::RSRPD
Definition: i8254xGBe_defs.hh:665
gem5::igbreg::Regs::RCTL
Definition: i8254xGBe_defs.hh:497
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Bitfield< 3 > addr
Definition: types.hh:84
gem5::igbreg::Regs::TIDV::ADD_FIELD32
ADD_FIELD32(idv, 0, 16)
gem5::igbreg::Regs::MDIC::ADD_FIELD32
ADD_FIELD32(data, 0, 16)
gem5::igbreg::Regs::rdba
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Definition: i8254xGBe_defs.hh:596
gem5::igbreg::Regs::TXDCTL::ADD_FIELD32
ADD_FIELD32(pthresh, 0, 6)

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