gem5 v24.0.0.0
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isa_device.hh
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1/*
2 * Copyright (c) 2014, 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __ARCH_ARM_ISA_DEVICE_HH__
39#define __ARCH_ARM_ISA_DEVICE_HH__
40
41#include "base/compiler.hh"
42#include "base/types.hh"
43
44namespace gem5
45{
46
47class ThreadContext;
48
49namespace ArmISA
50{
51
52class ISA;
53
62{
63 public:
65 virtual ~BaseISADevice() {}
66
67 virtual void setISA(ISA *isa);
68 virtual void setThreadContext(ThreadContext *tc) {}
69
76 virtual void setMiscReg(int misc_reg, RegVal val) = 0;
77
84 virtual RegVal readMiscReg(int misc_reg) = 0;
85
86 protected:
88};
89
98{
99 public:
103
104 void setMiscReg(int misc_reg, RegVal val) override;
105 RegVal readMiscReg(int misc_reg) override;
106};
107
108} // namespace ArmISA
109} // namespace gem5
110
111#endif // __ARCH_ARM_ISA_DEVICE_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
Base class for devices that use the MiscReg interfaces.
Definition isa_device.hh:62
virtual void setMiscReg(int misc_reg, RegVal val)=0
Write to a system register belonging to this device.
virtual void setISA(ISA *isa)
Definition isa_device.cc:55
virtual void setThreadContext(ThreadContext *tc)
Definition isa_device.hh:68
virtual RegVal readMiscReg(int misc_reg)=0
Read a system register belonging to this device.
Dummy device that prints a warning when it is accessed.
Definition isa_device.hh:98
RegVal readMiscReg(int misc_reg) override
Read a system register belonging to this device.
Definition isa_device.cc:71
void setMiscReg(int misc_reg, RegVal val) override
Write to a system register belonging to this device.
Definition isa_device.cc:63
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Bitfield< 63 > val
Definition misc.hh:804
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t RegVal
Definition types.hh:173

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