gem5
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arch
arm
isa_device.hh
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/*
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* Copyright (c) 2014, 2017 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ARM_ISA_DEVICE_HH__
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#define __ARCH_ARM_ISA_DEVICE_HH__
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#include "
base/compiler.hh
"
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#include "
base/types.hh
"
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namespace
gem5
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{
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class
ThreadContext;
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namespace
ArmISA
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{
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class
ISA;
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class
BaseISADevice
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{
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public
:
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BaseISADevice
();
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virtual
~BaseISADevice
() {}
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virtual
void
setISA
(
ISA
*
isa
);
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virtual
void
setThreadContext
(
ThreadContext
*tc) {}
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virtual
void
setMiscReg
(
int
misc_reg,
RegVal
val
) = 0;
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virtual
RegVal
readMiscReg
(
int
misc_reg) = 0;
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protected
:
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ISA
*
isa
;
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};
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class
DummyISADevice
:
public
BaseISADevice
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{
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public
:
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DummyISADevice
()
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:
BaseISADevice
() {}
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~DummyISADevice
() {}
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void
setMiscReg
(
int
misc_reg,
RegVal
val
)
override
;
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RegVal
readMiscReg
(
int
misc_reg)
override
;
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};
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}
// namespace ArmISA
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}
// namespace gem5
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#endif
// __ARCH_ARM_ISA_DEVICE_HH__
types.hh
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
gem5::ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition
isa_device.hh:62
gem5::ArmISA::BaseISADevice::setMiscReg
virtual void setMiscReg(int misc_reg, RegVal val)=0
Write to a system register belonging to this device.
gem5::ArmISA::BaseISADevice::BaseISADevice
BaseISADevice()
Definition
isa_device.cc:49
gem5::ArmISA::BaseISADevice::setISA
virtual void setISA(ISA *isa)
Definition
isa_device.cc:55
gem5::ArmISA::BaseISADevice::setThreadContext
virtual void setThreadContext(ThreadContext *tc)
Definition
isa_device.hh:68
gem5::ArmISA::BaseISADevice::~BaseISADevice
virtual ~BaseISADevice()
Definition
isa_device.hh:65
gem5::ArmISA::BaseISADevice::isa
ISA * isa
Definition
isa_device.hh:87
gem5::ArmISA::BaseISADevice::readMiscReg
virtual RegVal readMiscReg(int misc_reg)=0
Read a system register belonging to this device.
gem5::ArmISA::DummyISADevice
Dummy device that prints a warning when it is accessed.
Definition
isa_device.hh:98
gem5::ArmISA::DummyISADevice::DummyISADevice
DummyISADevice()
Definition
isa_device.hh:100
gem5::ArmISA::DummyISADevice::readMiscReg
RegVal readMiscReg(int misc_reg) override
Read a system register belonging to this device.
Definition
isa_device.cc:71
gem5::ArmISA::DummyISADevice::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Write to a system register belonging to this device.
Definition
isa_device.cc:63
gem5::ArmISA::DummyISADevice::~DummyISADevice
~DummyISADevice()
Definition
isa_device.hh:102
gem5::ArmISA::ISA
Definition
isa.hh:71
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
guest_abi.test.cc:41
compiler.hh
gem5::X86ISA::val
Bitfield< 63 > val
Definition
misc.hh:804
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::RegVal
uint64_t RegVal
Definition
types.hh:173
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