gem5  v22.1.0.0
isa_device.hh
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37 
38 #ifndef __ARCH_ARM_ISA_DEVICE_HH__
39 #define __ARCH_ARM_ISA_DEVICE_HH__
40 
41 #include "base/compiler.hh"
42 #include "base/types.hh"
43 
44 namespace gem5
45 {
46 
47 class ThreadContext;
48 
49 namespace ArmISA
50 {
51 
52 class ISA;
53 
62 {
63  public:
64  BaseISADevice();
65  virtual ~BaseISADevice() {}
66 
67  virtual void setISA(ISA *isa);
68  virtual void setThreadContext(ThreadContext *tc) {}
69 
76  virtual void setMiscReg(int misc_reg, RegVal val) = 0;
77 
84  virtual RegVal readMiscReg(int misc_reg) = 0;
85 
86  protected:
87  ISA *isa;
88 };
89 
98 {
99  public:
101  : BaseISADevice() {}
103 
104  void setMiscReg(int misc_reg, RegVal val) override;
105  RegVal readMiscReg(int misc_reg) override;
106 };
107 
108 } // namespace ArmISA
109 } // namespace gem5
110 
111 #endif // __ARCH_ARM_ISA_DEVICE_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:62
virtual void setMiscReg(int misc_reg, RegVal val)=0
Write to a system register belonging to this device.
virtual void setISA(ISA *isa)
Definition: isa_device.cc:55
virtual void setThreadContext(ThreadContext *tc)
Definition: isa_device.hh:68
virtual RegVal readMiscReg(int misc_reg)=0
Read a system register belonging to this device.
Dummy device that prints a warning when it is accessed.
Definition: isa_device.hh:98
RegVal readMiscReg(int misc_reg) override
Read a system register belonging to this device.
Definition: isa_device.cc:71
void setMiscReg(int misc_reg, RegVal val) override
Write to a system register belonging to this device.
Definition: isa_device.cc:63
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Bitfield< 63 > val
Definition: misc.hh:776
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t RegVal
Definition: types.hh:173

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