gem5 v24.0.0.0
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isa_device.cc
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1/*
2 * Copyright (c) 2014,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
39
40#include "arch/arm/regs/misc.hh"
41#include "base/logging.hh"
42
43namespace gem5
44{
45
46namespace ArmISA
47{
48
50 : isa(nullptr)
51{
52}
53
54void
56{
57 assert(_isa);
58
59 isa = _isa;
60}
61
62void
64{
65 warn("Ignoring write of 0x%lx to miscreg %s\n",
66 val,
67 miscRegName[misc_reg]);
68}
69
72{
73 warn("Returning zero for read from miscreg %s\n", miscRegName[misc_reg]);
74
75 return 0;
76}
77
78} // namespace ArmISA
79} // namespace gem5
virtual void setISA(ISA *isa)
Definition isa_device.cc:55
RegVal readMiscReg(int misc_reg) override
Read a system register belonging to this device.
Definition isa_device.cc:71
void setMiscReg(int misc_reg, RegVal val) override
Write to a system register belonging to this device.
Definition isa_device.cc:63
#define warn(...)
Definition logging.hh:256
const char *const miscRegName[]
Definition misc.hh:1815
Bitfield< 63 > val
Definition misc.hh:804
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t RegVal
Definition types.hh:173

Generated on Tue Jun 18 2024 16:23:56 for gem5 by doxygen 1.11.0