gem5  v21.2.1.1
isa.hh
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40 
41 #ifndef __ARCH_ARM_ISA_HH__
42 #define __ARCH_ARM_ISA_HH__
43 
44 #include "arch/arm/isa_device.hh"
45 #include "arch/arm/mmu.hh"
46 #include "arch/arm/pcstate.hh"
47 #include "arch/arm/regs/int.hh"
48 #include "arch/arm/regs/misc.hh"
49 #include "arch/arm/self_debug.hh"
50 #include "arch/arm/system.hh"
51 #include "arch/arm/types.hh"
52 #include "arch/arm/utility.hh"
53 #include "arch/generic/isa.hh"
54 #include "debug/Checkpoint.hh"
55 #include "enums/DecoderFlavor.hh"
56 #include "sim/sim_object.hh"
57 
58 namespace gem5
59 {
60 
61 struct ArmISAParams;
62 struct DummyArmISADeviceParams;
63 class Checkpoint;
64 class EventManager;
65 
66 namespace ArmISA
67 {
68  class ISA : public BaseISA
69  {
70  protected:
71  // Parent system
73 
74  // Micro Architecture
75  const enums::DecoderFlavor _decoderFlavor;
76 
79 
80  // PMU belonging to this ISA
82 
83  // Generic timer interface belonging to this ISA
84  std::unique_ptr<BaseISADevice> timer;
85 
86  // GICv3 CPU interface belonging to this ISA
87  std::unique_ptr<BaseISADevice> gicv3CpuInterface;
88 
89  // Cached copies of system-level properties
92  uint8_t physAddrRange;
93 
95  unsigned sveVL;
96 
99 
105 
107 
109 
112  {
113  uint32_t lower; // Lower half mapped to this register
114  uint32_t upper; // Upper half mapped to this register
115  uint64_t _reset; // value taken on reset (i.e. initialization)
116  uint64_t _res0; // reserved
117  uint64_t _res1; // reserved
118  uint64_t _raz; // read as zero (fixed at 0)
119  uint64_t _rao; // read as one (fixed at 1)
120  public:
122  lower(0), upper(0),
123  _reset(0), _res0(0), _res1(0), _raz(0), _rao(0) {}
124  uint64_t reset() const { return _reset; }
125  uint64_t res0() const { return _res0; }
126  uint64_t res1() const { return _res1; }
127  uint64_t raz() const { return _raz; }
128  uint64_t rao() const { return _rao; }
129  // raz/rao implies writes ignored
130  uint64_t wi() const { return _raz | _rao; }
131  };
132 
135 
137  {
139  std::bitset<NUM_MISCREG_INFOS> &info;
141  public:
142  chain
143  mapsTo(uint32_t l, uint32_t u = 0) const
144  {
145  entry.lower = l;
146  entry.upper = u;
147  return *this;
148  }
149  chain
150  res0(uint64_t mask) const
151  {
152  entry._res0 = mask;
153  return *this;
154  }
155  chain
156  res1(uint64_t mask) const
157  {
158  entry._res1 = mask;
159  return *this;
160  }
161  chain
162  raz(uint64_t mask) const
163  {
164  entry._raz = mask;
165  return *this;
166  }
167  chain
168  rao(uint64_t mask) const
169  {
170  entry._rao = mask;
171  return *this;
172  }
173  chain
174  implemented(bool v = true) const
175  {
177  return *this;
178  }
179  chain
181  {
182  return implemented(false);
183  }
184  chain
185  unverifiable(bool v = true) const
186  {
188  return *this;
189  }
190  chain
191  warnNotFail(bool v = true) const
192  {
194  return *this;
195  }
196  chain
197  mutex(bool v = true) const
198  {
199  info[MISCREG_MUTEX] = v;
200  return *this;
201  }
202  chain
203  banked(bool v = true) const
204  {
205  info[MISCREG_BANKED] = v;
206  return *this;
207  }
208  chain
209  banked64(bool v = true) const
210  {
212  return *this;
213  }
214  chain
215  bankedChild(bool v = true) const
216  {
218  return *this;
219  }
220  chain
221  userNonSecureRead(bool v = true) const
222  {
224  return *this;
225  }
226  chain
227  userNonSecureWrite(bool v = true) const
228  {
230  return *this;
231  }
232  chain
233  userSecureRead(bool v = true) const
234  {
236  return *this;
237  }
238  chain
239  userSecureWrite(bool v = true) const
240  {
242  return *this;
243  }
244  chain
245  user(bool v = true) const
246  {
249  userSecureRead(v);
251  return *this;
252  }
253  chain
254  privNonSecureRead(bool v = true) const
255  {
257  return *this;
258  }
259  chain
260  privNonSecureWrite(bool v = true) const
261  {
263  return *this;
264  }
265  chain
266  privNonSecure(bool v = true) const
267  {
270  return *this;
271  }
272  chain
273  privSecureRead(bool v = true) const
274  {
276  return *this;
277  }
278  chain
279  privSecureWrite(bool v = true) const
280  {
282  return *this;
283  }
284  chain
285  privSecure(bool v = true) const
286  {
287  privSecureRead(v);
289  return *this;
290  }
291  chain
292  priv(bool v = true) const
293  {
294  privSecure(v);
295  privNonSecure(v);
296  return *this;
297  }
298  chain
299  privRead(bool v = true) const
300  {
301  privSecureRead(v);
303  return *this;
304  }
305  chain
306  hypE2HSecureRead(bool v = true) const
307  {
309  return *this;
310  }
311  chain
312  hypE2HNonSecureRead(bool v = true) const
313  {
315  return *this;
316  }
317  chain
318  hypE2HRead(bool v = true) const
319  {
322  return *this;
323  }
324  chain
325  hypE2HSecureWrite(bool v = true) const
326  {
328  return *this;
329  }
330  chain
331  hypE2HNonSecureWrite(bool v = true) const
332  {
334  return *this;
335  }
336  chain
337  hypE2HWrite(bool v = true) const
338  {
341  return *this;
342  }
343  chain
344  hypE2H(bool v = true) const
345  {
346  hypE2HRead(v);
347  hypE2HWrite(v);
348  return *this;
349  }
350  chain
351  hypSecureRead(bool v = true) const
352  {
354  return *this;
355  }
356  chain
357  hypNonSecureRead(bool v = true) const
358  {
360  return *this;
361  }
362  chain
363  hypRead(bool v = true) const
364  {
365  hypE2HRead(v);
366  hypSecureRead(v);
368  return *this;
369  }
370  chain
371  hypSecureWrite(bool v = true) const
372  {
374  return *this;
375  }
376  chain
377  hypNonSecureWrite(bool v = true) const
378  {
380  return *this;
381  }
382  chain
383  hypWrite(bool v = true) const
384  {
385  hypE2HWrite(v);
386  hypSecureWrite(v);
388  return *this;
389  }
390  chain
391  hypSecure(bool v = true) const
392  {
395  hypSecureRead(v);
396  hypSecureWrite(v);
397  return *this;
398  }
399  chain
400  hyp(bool v = true) const
401  {
402  hypRead(v);
403  hypWrite(v);
404  return *this;
405  }
406  chain
407  monE2HRead(bool v = true) const
408  {
410  return *this;
411  }
412  chain
413  monE2HWrite(bool v = true) const
414  {
416  return *this;
417  }
418  chain
419  monE2H(bool v = true) const
420  {
421  monE2HRead(v);
422  monE2HWrite(v);
423  return *this;
424  }
425  chain
426  monSecureRead(bool v = true) const
427  {
428  monE2HRead(v);
430  return *this;
431  }
432  chain
433  monSecureWrite(bool v = true) const
434  {
435  monE2HWrite(v);
437  return *this;
438  }
439  chain
440  monNonSecureRead(bool v = true) const
441  {
442  monE2HRead(v);
444  return *this;
445  }
446  chain
447  monNonSecureWrite(bool v = true) const
448  {
449  monE2HWrite(v);
451  return *this;
452  }
453  chain
454  mon(bool v = true) const
455  {
456  monSecureRead(v);
457  monSecureWrite(v);
460  return *this;
461  }
462  chain
463  monSecure(bool v = true) const
464  {
465  monSecureRead(v);
466  monSecureWrite(v);
467  return *this;
468  }
469  chain
470  monNonSecure(bool v = true) const
471  {
474  return *this;
475  }
476  chain
477  allPrivileges(bool v = true) const
478  {
481  userSecureRead(v);
485  privSecureRead(v);
487  hypRead(v);
488  hypWrite(v);
489  monSecureRead(v);
490  monSecureWrite(v);
493  return *this;
494  }
495  chain
496  nonSecure(bool v = true) const
497  {
502  hypRead(v);
503  hypWrite(v);
506  return *this;
507  }
508  chain
509  secure(bool v = true) const
510  {
511  userSecureRead(v);
513  privSecureRead(v);
515  monSecureRead(v);
516  monSecureWrite(v);
517  return *this;
518  }
519  chain
520  reads(bool v) const
521  {
523  userSecureRead(v);
525  privSecureRead(v);
526  hypRead(v);
527  monSecureRead(v);
529  return *this;
530  }
531  chain
532  writes(bool v) const
533  {
538  hypWrite(v);
539  monSecureWrite(v);
541  return *this;
542  }
543  chain
545  {
546  user(0);
547  return *this;
548  }
549  chain highest(ArmSystem *const sys) const;
551  std::bitset<NUM_MISCREG_INFOS> &i)
552  : entry(e),
553  info(i)
554  {
555  // force unimplemented registers to be thusly declared
556  implemented(1);
557  }
558  };
559 
560  const MiscRegLUTEntryInitializer
561  InitReg(uint32_t reg)
562  {
564  miscRegInfo[reg]);
565  }
566 
568 
570  const IntRegIndex *intRegMap;
571 
572  void
573  updateRegMap(CPSR cpsr)
574  {
575  if (cpsr.width == 0) {
577  } else {
578  switch (cpsr.mode) {
579  case MODE_USER:
580  case MODE_SYSTEM:
582  break;
583  case MODE_FIQ:
585  break;
586  case MODE_IRQ:
588  break;
589  case MODE_SVC:
591  break;
592  case MODE_MON:
594  break;
595  case MODE_ABORT:
597  break;
598  case MODE_HYP:
600  break;
601  case MODE_UNDEFINED:
603  break;
604  default:
605  panic("Unrecognized mode setting in CPSR.\n");
606  }
607  }
608  }
609 
612 
613  private:
614  void assert32() { assert(((CPSR)readMiscReg(MISCREG_CPSR)).width); }
615  void assert64() { assert(!((CPSR)readMiscReg(MISCREG_CPSR)).width); }
616 
617  public:
618  void clear();
619 
620  protected:
621  void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst);
622  void clear64(const ArmISAParams &p);
623  void initID32(const ArmISAParams &p);
624  void initID64(const ArmISAParams &p);
625 
630 
631  public:
632  SelfDebug*
633  getSelfDebug() const
634  {
635  return selfDebug;
636  }
637 
638  static SelfDebug*
640  {
641  auto *arm_isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
642  return arm_isa->getSelfDebug();
643  }
644 
645  RegVal readMiscRegNoEffect(int misc_reg) const;
646  RegVal readMiscReg(int misc_reg);
647  void setMiscRegNoEffect(int misc_reg, RegVal val);
648  void setMiscReg(int misc_reg, RegVal val);
649 
650  RegId
651  flattenRegId(const RegId& regId) const
652  {
653  switch (regId.classValue()) {
654  case IntRegClass:
655  return RegId(IntRegClass, flattenIntIndex(regId.index()));
656  case FloatRegClass:
657  return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
658  case VecRegClass:
659  return RegId(VecRegClass, flattenVecIndex(regId.index()));
660  case VecElemClass:
661  return RegId(VecElemClass, flattenVecElemIndex(regId.index()),
662  regId.elemIndex());
663  case VecPredRegClass:
664  return RegId(VecPredRegClass,
665  flattenVecPredIndex(regId.index()));
666  case CCRegClass:
667  return RegId(CCRegClass, flattenCCIndex(regId.index()));
668  case MiscRegClass:
669  return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
670  }
671  return RegId();
672  }
673 
674  int
675  flattenIntIndex(int reg) const
676  {
677  assert(reg >= 0);
678  if (reg < NUM_ARCH_INTREGS) {
679  return intRegMap[reg];
680  } else if (reg < NUM_INTREGS) {
681  return reg;
682  } else if (reg == INTREG_SPX) {
683  CPSR cpsr = miscRegs[MISCREG_CPSR];
685  (OperatingMode) (uint8_t) cpsr.mode);
686  if (!cpsr.sp && el != EL0)
687  return INTREG_SP0;
688  switch (el) {
689  case EL3:
690  return INTREG_SP3;
691  case EL2:
692  return INTREG_SP2;
693  case EL1:
694  return INTREG_SP1;
695  case EL0:
696  return INTREG_SP0;
697  default:
698  panic("Invalid exception level");
699  return 0; // Never happens.
700  }
701  } else {
702  return flattenIntRegModeIndex(reg);
703  }
704  }
705 
706  int
708  {
709  assert(reg >= 0);
710  return reg;
711  }
712 
713  int
714  flattenVecIndex(int reg) const
715  {
716  assert(reg >= 0);
717  return reg;
718  }
719 
720  int
722  {
723  assert(reg >= 0);
724  return reg;
725  }
726 
727  int
729  {
730  assert(reg >= 0);
731  return reg;
732  }
733 
734  int
735  flattenCCIndex(int reg) const
736  {
737  assert(reg >= 0);
738  return reg;
739  }
740 
741  int
743  {
744  assert(reg >= 0);
745  int flat_idx = reg;
746 
747  if (reg == MISCREG_SPSR) {
748  CPSR cpsr = miscRegs[MISCREG_CPSR];
749  switch (cpsr.mode) {
750  case MODE_EL0T:
751  warn("User mode does not have SPSR\n");
752  flat_idx = MISCREG_SPSR;
753  break;
754  case MODE_EL1T:
755  case MODE_EL1H:
756  flat_idx = MISCREG_SPSR_EL1;
757  break;
758  case MODE_EL2T:
759  case MODE_EL2H:
760  flat_idx = MISCREG_SPSR_EL2;
761  break;
762  case MODE_EL3T:
763  case MODE_EL3H:
764  flat_idx = MISCREG_SPSR_EL3;
765  break;
766  case MODE_USER:
767  warn("User mode does not have SPSR\n");
768  flat_idx = MISCREG_SPSR;
769  break;
770  case MODE_FIQ:
771  flat_idx = MISCREG_SPSR_FIQ;
772  break;
773  case MODE_IRQ:
774  flat_idx = MISCREG_SPSR_IRQ;
775  break;
776  case MODE_SVC:
777  flat_idx = MISCREG_SPSR_SVC;
778  break;
779  case MODE_MON:
780  flat_idx = MISCREG_SPSR_MON;
781  break;
782  case MODE_ABORT:
783  flat_idx = MISCREG_SPSR_ABT;
784  break;
785  case MODE_HYP:
786  flat_idx = MISCREG_SPSR_HYP;
787  break;
788  case MODE_UNDEFINED:
789  flat_idx = MISCREG_SPSR_UND;
790  break;
791  default:
792  warn("Trying to access SPSR in an invalid mode: %d\n",
793  cpsr.mode);
794  flat_idx = MISCREG_SPSR;
795  break;
796  }
797  } else if (miscRegInfo[reg][MISCREG_MUTEX]) {
798  // Mutually exclusive CP15 register
799  switch (reg) {
800  case MISCREG_PRRR_MAIR0:
803  {
804  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
805  // If the muxed reg has been flattened, work out the
806  // offset and apply it to the unmuxed reg
807  int idxOffset = reg - MISCREG_PRRR_MAIR0;
808  if (ttbcr.eae)
809  flat_idx = flattenMiscIndex(MISCREG_MAIR0 +
810  idxOffset);
811  else
812  flat_idx = flattenMiscIndex(MISCREG_PRRR +
813  idxOffset);
814  }
815  break;
816  case MISCREG_NMRR_MAIR1:
819  {
820  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
821  // If the muxed reg has been flattened, work out the
822  // offset and apply it to the unmuxed reg
823  int idxOffset = reg - MISCREG_NMRR_MAIR1;
824  if (ttbcr.eae)
825  flat_idx = flattenMiscIndex(MISCREG_MAIR1 +
826  idxOffset);
827  else
828  flat_idx = flattenMiscIndex(MISCREG_NMRR +
829  idxOffset);
830  }
831  break;
833  {
834  PMSELR pmselr = miscRegs[MISCREG_PMSELR];
835  if (pmselr.sel == 31)
837  else
839  }
840  break;
841  default:
842  panic("Unrecognized misc. register.\n");
843  break;
844  }
845  } else {
847  bool secure_reg = !highestELIs64 && inSecureState();
848  flat_idx += secure_reg ? 2 : 1;
849  } else {
850  flat_idx = snsBankedIndex64((MiscRegIndex)reg,
851  !inSecureState());
852  }
853  }
854  return flat_idx;
855  }
856 
861  int
862  redirectRegVHE(int misc_reg)
863  {
864  const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
865  if (hcr.e2h == 0x0 || currEL() != EL2)
866  return misc_reg;
868  bool sec_el2 = scr.eel2 && release->has(ArmExtension::FEAT_SEL2);
869  switch(misc_reg) {
870  case MISCREG_SPSR_EL1:
871  return MISCREG_SPSR_EL2;
872  case MISCREG_ELR_EL1:
873  return MISCREG_ELR_EL2;
874  case MISCREG_SCTLR_EL1:
875  return MISCREG_SCTLR_EL2;
876  case MISCREG_CPACR_EL1:
877  return MISCREG_CPTR_EL2;
878  // case :
879  // return MISCREG_TRFCR_EL2;
880  case MISCREG_TTBR0_EL1:
881  return MISCREG_TTBR0_EL2;
882  case MISCREG_TTBR1_EL1:
883  return MISCREG_TTBR1_EL2;
884  case MISCREG_TCR_EL1:
885  return MISCREG_TCR_EL2;
886  case MISCREG_AFSR0_EL1:
887  return MISCREG_AFSR0_EL2;
888  case MISCREG_AFSR1_EL1:
889  return MISCREG_AFSR1_EL2;
890  case MISCREG_ESR_EL1:
891  return MISCREG_ESR_EL2;
892  case MISCREG_FAR_EL1:
893  return MISCREG_FAR_EL2;
894  case MISCREG_MAIR_EL1:
895  return MISCREG_MAIR_EL2;
896  case MISCREG_AMAIR_EL1:
897  return MISCREG_AMAIR_EL2;
898  case MISCREG_VBAR_EL1:
899  return MISCREG_VBAR_EL2;
901  return MISCREG_CONTEXTIDR_EL2;
902  case MISCREG_CNTKCTL_EL1:
903  return MISCREG_CNTHCTL_EL2;
905  return sec_el2? MISCREG_CNTHPS_TVAL_EL2:
908  return sec_el2? MISCREG_CNTHPS_CTL_EL2:
911  return sec_el2? MISCREG_CNTHPS_CVAL_EL2:
914  return sec_el2? MISCREG_CNTHVS_TVAL_EL2:
917  return sec_el2? MISCREG_CNTHVS_CTL_EL2:
920  return sec_el2? MISCREG_CNTHVS_CVAL_EL2:
922  default:
923  return misc_reg;
924  }
925  /*should not be accessible */
926  return misc_reg;
927  }
928 
929  int
931  {
932  int reg_as_int = static_cast<int>(reg);
934  reg_as_int += (release->has(ArmExtension::SECURITY) && !ns) ?
935  2 : 1;
936  }
937  return reg_as_int;
938  }
939 
941  getMiscIndices(int misc_reg) const
942  {
943  // Note: indexes of AArch64 registers are left unchanged
944  int flat_idx = flattenMiscIndex(misc_reg);
945 
946  if (lookUpMiscReg[flat_idx].lower == 0) {
947  return std::make_pair(flat_idx, 0);
948  }
949 
950  // do additional S/NS flattenings if mapped to NS while in S
951  bool S = !highestELIs64 && inSecureState();
952 
953  int lower = lookUpMiscReg[flat_idx].lower;
954  int upper = lookUpMiscReg[flat_idx].upper;
955  // upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op)
956  lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD];
957  upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD];
958  return std::make_pair(lower, upper);
959  }
960 
962  bool inSecureState() const;
963 
967  ExceptionLevel currEL() const;
968 
969  unsigned getCurSveVecLenInBits() const;
970 
971  unsigned getCurSveVecLenInBitsAtReset() const { return sveVL * 128; }
972 
973  template <typename Elem>
974  static void
975  zeroSveVecRegUpperPart(Elem *v, unsigned eCount)
976  {
977  static_assert(sizeof(Elem) <= sizeof(uint64_t),
978  "Elem type is too large.");
979  eCount *= (sizeof(uint64_t) / sizeof(Elem));
980  for (int i = 16 / sizeof(Elem); i < eCount; ++i) {
981  v[i] = 0;
982  }
983  }
984 
985  void serialize(CheckpointOut &cp) const override;
986  void unserialize(CheckpointIn &cp) override;
987 
988  void startup() override;
989 
990  void setupThreadContext();
991 
992  PCStateBase *
993  newPCState(Addr new_inst_addr=0) const override
994  {
995  return new PCState(new_inst_addr);
996  }
997 
998  void takeOverFrom(ThreadContext *new_tc,
999  ThreadContext *old_tc) override;
1000 
1001  enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; }
1002 
1004  bool
1006  {
1007  // gicv3CpuInterface is initialized at startup time, hence
1008  // trying to read its value before the startup stage will lead
1009  // to an error
1010  assert(afterStartup);
1011  return gicv3CpuInterface != nullptr;
1012  }
1013 
1014  PARAMS(ArmISA);
1015 
1016  ISA(const Params &p);
1017 
1018  uint64_t
1019  getExecutingAsid() const override
1020  {
1022  }
1023 
1024  bool
1025  inUserMode() const override
1026  {
1027  CPSR cpsr = miscRegs[MISCREG_CPSR];
1028  return ArmISA::inUserMode(cpsr);
1029  }
1030 
1031  void copyRegsFrom(ThreadContext *src) override;
1032 
1033  void handleLockedRead(const RequestPtr &req) override;
1034  void handleLockedRead(ExecContext *xc, const RequestPtr &req) override;
1035 
1036  bool handleLockedWrite(const RequestPtr &req,
1037  Addr cacheBlockMask) override;
1038  bool handleLockedWrite(ExecContext *xc, const RequestPtr &req,
1039  Addr cacheBlockMask) override;
1040 
1041  void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override;
1042  void handleLockedSnoop(ExecContext *xc, PacketPtr pkt,
1043  Addr cacheBlockMask) override;
1044  void handleLockedSnoopHit() override;
1045  void handleLockedSnoopHit(ExecContext *xc) override;
1046 
1047  void globalClearExclusive() override;
1048  void globalClearExclusive(ExecContext *xc) override;
1049  };
1050 
1051 } // namespace ArmISA
1052 } // namespace gem5
1053 
1054 #endif
gem5::ArmISA::MISCREG_USR_NS_RD
@ MISCREG_USR_NS_RD
Definition: misc.hh:1122
isa_device.hh
gem5::ArmISA::MISCREG_PRI_S_WR
@ MISCREG_PRI_S_WR
Definition: misc.hh:1130
gem5::ArmISA::MODE_EL2H
@ MODE_EL2H
Definition: types.hh:278
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:649
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:588
gem5::ArmISA::ISA::newPCState
PCStateBase * newPCState(Addr new_inst_addr=0) const override
Definition: isa.hh:993
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HWrite
chain hypE2HWrite(bool v=true) const
Definition: isa.hh:337
gem5::ArmISA::ISA::PARAMS
PARAMS(ArmISA)
gem5::ArmISA::MISCREG_USR_NS_WR
@ MISCREG_USR_NS_WR
Definition: misc.hh:1123
gem5::ArmISA::MISCREG_PMCCFILTR
@ MISCREG_PMCCFILTR
Definition: misc.hh:361
gem5::ArmISA::ISA::addressTranslation64
void addressTranslation64(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2627
gem5::ArmISA::ISA::dummyDevice
DummyISADevice dummyDevice
Dummy device for to handle non-existing ISA devices.
Definition: isa.hh:78
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: misc.hh:603
gem5::ArmISA::ISA::zeroSveVecRegUpperPart
static void zeroSveVecRegUpperPart(Elem *v, unsigned eCount)
Definition: isa.hh:975
gem5::ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition: misc.hh:728
gem5::ArmISA::ISA::MiscRegLUTEntry::lower
uint32_t lower
Definition: isa.hh:113
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monE2H
chain monE2H(bool v=true) const
Definition: isa.hh:419
gem5::ArmISA::ISA::getSelfDebug
static SelfDebug * getSelfDebug(ThreadContext *tc)
Definition: isa.hh:639
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:284
gem5::ArmISA::MISCREG_CNTHVS_TVAL_EL2
@ MISCREG_CNTHVS_TVAL_EL2
Definition: misc.hh:786
gem5::ArmISA::ISA::currEL
ExceptionLevel currEL() const
Returns the current Exception Level (EL) of the ISA object.
Definition: isa.cc:2559
gem5::ArmISA::MISCREG_PRI_S_RD
@ MISCREG_PRI_S_RD
Definition: misc.hh:1129
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:65
warn
#define warn(...)
Definition: logging.hh:246
gem5::ArmISA::ISA::selfDebug
SelfDebug * selfDebug
Definition: isa.hh:108
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::MISCREG_BANKED64
@ MISCREG_BANKED64
Definition: misc.hh:1113
gem5::ArmISA::ISA::MiscRegLUTEntry::_raz
uint64_t _raz
Definition: isa.hh:118
gem5::ArmISA::ISA::getCurSveVecLenInBits
unsigned getCurSveVecLenInBits() const
Definition: isa.cc:2567
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:282
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privNonSecureWrite
chain privNonSecureWrite(bool v=true) const
Definition: isa.hh:260
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:675
gem5::ArmISA::ISA::gicv3CpuInterface
std::unique_ptr< BaseISADevice > gicv3CpuInterface
Definition: isa.hh:87
gem5::ArmISA::MISCREG_PRRR_MAIR0_S
@ MISCREG_PRRR_MAIR0_S
Definition: misc.hh:86
gem5::ArmISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:585
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::warnNotFail
chain warnNotFail(bool v=true) const
Definition: isa.hh:191
gem5::ArmISA::ISA::clear
void clear()
Definition: isa.cc:135
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:399
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mutex
chain mutex(bool v=true) const
Definition: isa.hh:197
gem5::ArmISA::MISCREG_CNTHPS_TVAL_EL2
@ MISCREG_CNTHPS_TVAL_EL2
Definition: misc.hh:779
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:759
gem5::ArmISA::MISCREG_CNTHVS_CVAL_EL2
@ MISCREG_CNTHVS_CVAL_EL2
Definition: misc.hh:785
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::ArmISA::MISCREG_PRRR_MAIR0_NS
@ MISCREG_PRRR_MAIR0_NS
Definition: misc.hh:85
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:756
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::allPrivileges
chain allPrivileges(bool v=true) const
Definition: isa.hh:477
gem5::ArmISA::ISA::haveLargeAsid64
bool haveLargeAsid64
Definition: isa.hh:91
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::priv
chain priv(bool v=true) const
Definition: isa.hh:292
gem5::ArmISA::MODE_EL2T
@ MODE_EL2T
Definition: types.hh:277
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::ArmISA::ISA::takeOverFrom
void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override
Definition: isa.cc:546
gem5::ArmISA::ISA::handleLockedSnoop
void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override
Definition: isa.cc:2788
gem5::ArmISA::ISA::initID32
void initID32(const ArmISAParams &p)
Definition: isa.cc:328
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::ArmISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:1025
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::ArmISA::MODE_EL1H
@ MODE_EL1H
Definition: types.hh:276
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:283
gem5::ArmISA::MISCREG_MON_NS0_WR
@ MISCREG_MON_NS0_WR
Definition: misc.hh:1143
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::ArmISA::ISA::updateRegMap
void updateRegMap(CPSR cpsr)
Definition: isa.hh:573
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::ArmISA::ISA::release
const ArmRelease * release
This could be either a FS or a SE release.
Definition: isa.hh:98
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privNonSecureRead
chain privNonSecureRead(bool v=true) const
Definition: isa.hh:254
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::secure
chain secure(bool v=true) const
Definition: isa.hh:509
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypWrite
chain hypWrite(bool v=true) const
Definition: isa.hh:383
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmISA::ISA::timer
std::unique_ptr< BaseISADevice > timer
Definition: isa.hh:84
gem5::ArmISA::ISA::MiscRegLUTEntry::MiscRegLUTEntry
MiscRegLUTEntry()
Definition: isa.hh:121
gem5::ArmISA::MISCREG_HYP_E2H_NS_RD
@ MISCREG_HYP_E2H_NS_RD
Definition: misc.hh:1137
gem5::ArmISA::MISCREG_PRI_NS_WR
@ MISCREG_PRI_NS_WR
Definition: misc.hh:1128
gem5::ArmISA::ISA::MiscRegLUTEntry
MiscReg metadata.
Definition: isa.hh:111
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypSecureRead
chain hypSecureRead(bool v=true) const
Definition: isa.hh:351
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::info
std::bitset< NUM_MISCREG_INFOS > & info
Definition: isa.hh:139
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: misc.hh:599
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:740
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: misc.hh:260
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition: misc.hh:643
gem5::ArmISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:728
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:644
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HNonSecureWrite
chain hypE2HNonSecureWrite(bool v=true) const
Definition: isa.hh:331
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::ISA::MiscRegLUTEntry::upper
uint32_t upper
Definition: isa.hh:114
gem5::ArmISA::ISA::MiscRegLUTEntry::_rao
uint64_t _rao
Definition: isa.hh:119
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::res0
chain res0(uint64_t mask) const
Definition: isa.hh:150
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypNonSecureRead
chain hypNonSecureRead(bool v=true) const
Definition: isa.hh:357
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privSecure
chain privSecure(bool v=true) const
Definition: isa.hh:285
gem5::ArmISA::ISA::MiscRegLUTEntry::_reset
uint64_t _reset
Definition: isa.hh:115
gem5::ArmISA::IntRegFiqMap
const IntRegMap IntRegFiqMap
Definition: int.hh:454
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:745
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition: misc_types.hh:332
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecureWrite
chain monNonSecureWrite(bool v=true) const
Definition: isa.hh:447
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::IntRegUsrMap
const IntRegMap IntRegUsrMap
Definition: int.hh:328
gem5::ArmISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:553
gem5::ArmISA::MISCREG_NMRR_MAIR1
@ MISCREG_NMRR_MAIR1
Definition: misc.hh:87
gem5::ArmISA::MISCREG_PRRR_MAIR0
@ MISCREG_PRRR_MAIR0
Definition: misc.hh:84
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:383
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: misc.hh:66
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmISA::ISA::getCurSveVecLenInBitsAtReset
unsigned getCurSveVecLenInBitsAtReset() const
Definition: isa.hh:971
gem5::ArmISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:2611
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition: misc.hh:726
gem5::ArmISA::ISA::MiscRegLUTEntry::rao
uint64_t rao() const
Definition: isa.hh:128
gem5::ArmISA::ISA::sveVL
unsigned sveVL
SVE vector length in quadwords.
Definition: isa.hh:95
gem5::ArmISA::MISCREG_NMRR_MAIR1_NS
@ MISCREG_NMRR_MAIR1_NS
Definition: misc.hh:88
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::chain
const typedef MiscRegLUTEntryInitializer & chain
Definition: isa.hh:140
system.hh
gem5::ArmISA::MISCREG_IMPLEMENTED
@ MISCREG_IMPLEMENTED
Definition: misc.hh:1102
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ArmISA::MISCREG_USR_S_WR
@ MISCREG_USR_S_WR
Definition: misc.hh:1125
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::userSecureWrite
chain userSecureWrite(bool v=true) const
Definition: isa.hh:239
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HNonSecureRead
chain hypE2HNonSecureRead(bool v=true) const
Definition: isa.hh:312
gem5::ArmISA::MODE_EL3H
@ MODE_EL3H
Definition: types.hh:280
types.hh
gem5::RegId::index
RegIndex index() const
Index accessors.
Definition: reg_class.hh:180
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HSecureWrite
chain hypE2HSecureWrite(bool v=true) const
Definition: isa.hh:325
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2H
chain hypE2H(bool v=true) const
Definition: isa.hh:344
gem5::ArmISA::ISA::intRegMap
const IntRegIndex * intRegMap
Definition: isa.hh:570
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::ArmISA::miscRegInfo
std::bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: misc.cc:3399
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypNonSecureWrite
chain hypNonSecureWrite(bool v=true) const
Definition: isa.hh:377
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privRead
chain privRead(bool v=true) const
Definition: isa.hh:299
gem5::ArmISA::IntReg64Map
const IntRegMap IntReg64Map
Definition: int.hh:317
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:768
gem5::ArmISA::ISA::MiscRegLUTEntry::_res1
uint64_t _res1
Definition: isa.hh:117
gem5::ArmISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:921
gem5::ArmISA::ISA::initID64
void initID64(const ArmISAParams &p)
Definition: isa.cc:381
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition: misc.hh:730
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
mmu.hh
gem5::ArmISA::ISA::handleLockedRead
void handleLockedRead(const RequestPtr &req) override
Definition: isa.cc:2800
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2
@ MISCREG_CNTHP_TVAL_EL2
Definition: misc.hh:776
gem5::ArmRelease::has
bool has(ArmExtension ext) const
Definition: system.hh:75
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:773
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::unverifiable
chain unverifiable(bool v=true) const
Definition: isa.hh:185
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypSecureWrite
chain hypSecureWrite(bool v=true) const
Definition: isa.hh:371
gem5::Flags< FlagsType >
gem5::ArmISA::MODE_EL3T
@ MODE_EL3T
Definition: types.hh:279
gem5::ArmISA::ISA::pmu
BaseISADevice * pmu
Definition: isa.hh:81
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:614
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::userNonSecureWrite
chain userNonSecureWrite(bool v=true) const
Definition: isa.hh:227
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privSecureRead
chain privSecureRead(bool v=true) const
Definition: isa.hh:273
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: misc.hh:369
gem5::ArmISA::MODE_EL1T
@ MODE_EL1T
Definition: types.hh:275
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::writes
chain writes(bool v) const
Definition: isa.hh:532
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::banked64
chain banked64(bool v=true) const
Definition: isa.hh:209
gem5::ArmISA::ISA::handleLockedSnoopHit
void handleLockedSnoopHit() override
Definition: isa.cc:2818
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::ArmISA::ISA::clear64
void clear64(const ArmISAParams &p)
Definition: isa.cc:279
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::banked
chain banked(bool v=true) const
Definition: isa.hh:203
sim_object.hh
gem5::ArmISA::width
Bitfield< 4 > width
Definition: misc_types.hh:72
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monSecureWrite
chain monSecureWrite(bool v=true) const
Definition: isa.hh:433
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ArmISA::MISCREG_PMSELR
@ MISCREG_PMSELR
Definition: misc.hh:356
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: misc.hh:378
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::ISA::snsBankedIndex64
int snsBankedIndex64(MiscRegIndex reg, bool ns) const
Definition: isa.hh:930
gem5::ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition: misc.hh:731
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::ISA::globalClearExclusive
void globalClearExclusive() override
Definition: isa.cc:2890
gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2
@ MISCREG_CNTHP_CVAL_EL2
Definition: misc.hh:775
gem5::ArmISA::IntRegSvcMap
const IntRegMap IntRegSvcMap
Definition: int.hh:364
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:584
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::ISA::getMiscIndices
std::pair< int, int > getMiscIndices(int misc_reg) const
Definition: isa.hh:941
gem5::ArmISA::ISA::MiscRegLUTEntry::res0
uint64_t res0() const
Definition: isa.hh:125
gem5::ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:1097
gem5::ArmISA::MISCREG_CNTHVS_CTL_EL2
@ MISCREG_CNTHVS_CTL_EL2
Definition: misc.hh:784
gem5::ArmISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:2618
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mapsTo
chain mapsTo(uint32_t l, uint32_t u=0) const
Definition: isa.hh:143
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::ArmISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:83
gem5::ArmISA::MISCREG_SPSR
@ MISCREG_SPSR
Definition: misc.hh:62
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::MISCREG_MON_NS1_WR
@ MISCREG_MON_NS1_WR
Definition: misc.hh:1146
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition: isa.hh:454
gem5::ArmISA::MISCREG_MUTEX
@ MISCREG_MUTEX
Definition: misc.hh:1108
gem5::ArmISA::ISA::addressTranslation
void addressTranslation(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2678
gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: misc.hh:90
gem5::ArmISA::MISCREG_HYP_E2H_S_RD
@ MISCREG_HYP_E2H_S_RD
Definition: misc.hh:1139
gem5::ArmISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:721
gem5::ArmISA::MISCREG_MON_NS1_RD
@ MISCREG_MON_NS1_RD
Definition: misc.hh:1145
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:582
gem5::ArmISA::MISCREG_HYP_S_RD
@ MISCREG_HYP_S_RD
Definition: misc.hh:1134
gem5::MipsISA::l
Bitfield< 5 > l
Definition: pra_constants.hh:323
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:625
gem5::ArmISA::ISA::assert32
void assert32()
Definition: isa.hh:614
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:714
gem5::ArmISA::ISA::handleLockedWrite
bool handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask) override
Definition: isa.cc:2877
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monSecureRead
chain monSecureRead(bool v=true) const
Definition: isa.hh:426
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::nonSecure
chain nonSecure(bool v=true) const
Definition: isa.hh:496
gem5::ArmISA::ISA::getGICv3CPUInterface
BaseISADevice & getGICv3CPUInterface()
Definition: isa.cc:2528
gem5::ArmISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:609
gem5::ArmISA::MISCREG_BANKED
@ MISCREG_BANKED
Definition: misc.hh:1110
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::MISCREG_CNTHP_CTL_EL2
@ MISCREG_CNTHP_CTL_EL2
Definition: misc.hh:774
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecure
chain monNonSecure(bool v=true) const
Definition: isa.hh:470
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypSecure
chain hypSecure(bool v=true) const
Definition: isa.hh:391
gem5::ArmISA::ISA::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: isa.cc:508
gem5::RegId::classValue
RegClassType classValue() const
Class accessor.
Definition: reg_class.hh:206
std::pair< int, int >
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypRead
chain hypRead(bool v=true) const
Definition: isa.hh:363
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::bankedChild
chain bankedChild(bool v=true) const
Definition: isa.hh:215
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::implemented
chain implemented(bool v=true) const
Definition: isa.hh:174
gem5::ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition: misc.hh:760
gem5::ArmISA::ISA::getGenericTimer
BaseISADevice & getGenericTimer()
Definition: isa.cc:2507
gem5::ArmISA::IntRegUndMap
const IntRegMap IntRegUndMap
Definition: int.hh:418
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:612
gem5::ArmISA::MISCREG_PRI_NS_RD
@ MISCREG_PRI_NS_RD
Definition: misc.hh:1127
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_HYP_E2H_NS_WR
@ MISCREG_HYP_E2H_NS_WR
Definition: misc.hh:1138
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: misc.hh:375
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::unimplemented
chain unimplemented() const
Definition: isa.hh:180
gem5::ArmISA::ISA::decoderFlavor
enums::DecoderFlavor decoderFlavor() const
Definition: isa.hh:1001
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: misc.hh:758
pcstate.hh
gem5::ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition: misc.hh:642
gem5::ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: misc.cc:3402
gem5::ArmISA::IntRegAbtMap
const IntRegMap IntRegAbtMap
Definition: int.hh:400
utility.hh
gem5::ArmISA::ISA::highestELIs64
bool highestELIs64
Definition: isa.hh:90
gem5::ArmISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:651
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: misc.hh:372
gem5::ArmRelease
Definition: system.hh:68
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::reads
chain reads(bool v) const
Definition: isa.hh:520
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::entry
struct MiscRegLUTEntry & entry
Definition: isa.hh:138
gem5::ArmISA::MISCREG_HYP_S_WR
@ MISCREG_HYP_S_WR
Definition: misc.hh:1135
gem5::ArmISA::ISA::MiscRegLUTEntry::raz
uint64_t raz() const
Definition: isa.hh:127
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ArmISA::MISCREG_MON_NS0_RD
@ MISCREG_MON_NS0_RD
Definition: misc.hh:1142
gem5::ArmISA::ISA::setupThreadContext
void setupThreadContext()
Definition: isa.cc:525
gem5::ArmISA::ISA::lookUpMiscReg
static std::vector< struct MiscRegLUTEntry > lookUpMiscReg
Metadata table accessible via the value of the register.
Definition: isa.hh:134
gem5::ArmISA::ISA::MiscRegLUTEntry::wi
uint64_t wi() const
Definition: isa.hh:130
gem5::ArmISA::MISCREG_UNVERIFIABLE
@ MISCREG_UNVERIFIABLE
Definition: misc.hh:1103
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: misc.hh:632
gem5::ArmISA::u
Bitfield< 22 > u
Definition: misc_types.hh:353
isa.hh
gem5::ArmISA::ISA::_decoderFlavor
const enums::DecoderFlavor _decoderFlavor
Definition: isa.hh:75
gem5::RegId::elemIndex
RegIndex elemIndex() const
Elem accessor.
Definition: reg_class.hh:204
gem5::ArmISA::MMU::ArmTranslationType
ArmTranslationType
Definition: mmu.hh:113
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::ArmSystem
Definition: system.hh:91
gem5::ArmISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:707
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition: isa.cc:2746
gem5::ArmISA::MODE_EL0T
@ MODE_EL0T
Definition: types.hh:274
gem5::ArmISA::IntRegIrqMap
const IntRegMap IntRegIrqMap
Definition: int.hh:436
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monE2HRead
chain monE2HRead(bool v=true) const
Definition: isa.hh:407
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: misc.hh:65
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::ArmISA::ISA::InitReg
const MiscRegLUTEntryInitializer InitReg(uint32_t reg)
Definition: isa.hh:561
gem5::ArmISA::MISCREG_CNTP_CVAL_EL0
@ MISCREG_CNTP_CVAL_EL0
Definition: misc.hh:757
gem5::ArmISA::MISCREG_CNTHV_TVAL_EL2
@ MISCREG_CNTHV_TVAL_EL2
Definition: misc.hh:783
gem5::ArmISA::ISA::miscRegs
RegVal miscRegs[NUM_MISCREGS]
Definition: isa.hh:569
gem5::ArmISA::ISA::MiscRegLUTEntry::reset
uint64_t reset() const
Definition: isa.hh:124
misc.hh
gem5::ArmISA::DummyISADevice
Dummy device that prints a warning when it is accessed.
Definition: isa_device.hh:97
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::exceptUserMode
chain exceptUserMode() const
Definition: isa.hh:544
gem5::ArmISA::ISA::getSelfDebug
SelfDebug * getSelfDebug() const
Definition: isa.hh:633
gem5::ArmISA::ISA::system
ArmSystem * system
Definition: isa.hh:72
gem5::ArmISA::MISCREG_CNTHPS_CTL_EL2
@ MISCREG_CNTHPS_CTL_EL2
Definition: misc.hh:777
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:626
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:289
gem5::ArmISA::inUserMode
static bool inUserMode(CPSR cpsr)
Definition: utility.hh:96
gem5::ArmISA::flattenIntRegModeIndex
static int flattenIntRegModeIndex(int reg)
Definition: int.hh:482
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::MiscRegLUTEntryInitializer
MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e, std::bitset< NUM_MISCREG_INFOS > &i)
Definition: isa.hh:550
gem5::ArmISA::MISCREG_CNTHPS_CVAL_EL2
@ MISCREG_CNTHPS_CVAL_EL2
Definition: misc.hh:778
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:943
gem5::ArmISA::ISA::getExecutingAsid
uint64_t getExecutingAsid() const override
Definition: isa.hh:1019
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HRead
chain hypE2HRead(bool v=true) const
Definition: isa.hh:318
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer
Definition: isa.hh:136
gem5::ArmISA::IntRegHypMap
const IntRegMap IntRegHypMap
Definition: int.hh:346
gem5::ArmISA::MISCREG_USR_S_RD
@ MISCREG_USR_S_RD
Definition: misc.hh:1124
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition: misc.hh:635
gem5::ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition: misc.hh:360
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monE2HWrite
chain monE2HWrite(bool v=true) const
Definition: isa.hh:413
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monSecure
chain monSecure(bool v=true) const
Definition: isa.hh:463
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:817
gem5::ArmISA::ISA::MiscRegLUTEntry::_res0
uint64_t _res0
Definition: isa.hh:116
gem5::ArmISA::MISCREG_HYP_E2H_S_WR
@ MISCREG_HYP_E2H_S_WR
Definition: misc.hh:1140
gem5::ArmISA::MISCREG_CNTHV_CVAL_EL2
@ MISCREG_CNTHV_CVAL_EL2
Definition: misc.hh:782
gem5::ArmISA::ISA::physAddrRange
uint8_t physAddrRange
Definition: isa.hh:92
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ArmISA::ISA::redirectRegVHE
int redirectRegVHE(int misc_reg)
Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at ...
Definition: isa.hh:862
self_debug.hh
gem5::BaseISA
Definition: isa.hh:57
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition: isa.hh:400
gem5::ArmISA::ISA::afterStartup
bool afterStartup
Definition: isa.hh:106
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::userNonSecureRead
chain userNonSecureRead(bool v=true) const
Definition: isa.hh:221
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:286
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5::ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition: misc.hh:637
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: misc.hh:597
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privSecureWrite
chain privSecureWrite(bool v=true) const
Definition: isa.hh:279
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:651
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::user
chain user(bool v=true) const
Definition: isa.hh:245
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::raz
chain raz(uint64_t mask) const
Definition: isa.hh:162
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HSecureRead
chain hypE2HSecureRead(bool v=true) const
Definition: isa.hh:306
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::res1
chain res1(uint64_t mask) const
Definition: isa.hh:156
gem5::ArmISA::MISCREG_NMRR_MAIR1_S
@ MISCREG_NMRR_MAIR1_S
Definition: misc.hh:89
gem5::ArmISA::MISCREG_CNTHV_CTL_EL2
@ MISCREG_CNTHV_CTL_EL2
Definition: misc.hh:781
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:639
int.hh
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:736
gem5::ArmISA::IntRegMonMap
const IntRegMap IntRegMonMap
Definition: int.hh:382
gem5::ArmISA::MISCREG_MON_E2H_RD
@ MISCREG_MON_E2H_RD
Definition: misc.hh:1148
gem5::ArmISA::MISCREG_MON_E2H_WR
@ MISCREG_MON_E2H_WR
Definition: misc.hh:1149
gem5::ArmISA::ISA::MiscRegLUTEntry::res1
uint64_t res1() const
Definition: isa.hh:126
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: misc.hh:68
gem5::ArmISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:735
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecureRead
chain monNonSecureRead(bool v=true) const
Definition: isa.hh:440
gem5::ArmISA::MISCREG_BANKED_CHILD
@ MISCREG_BANKED_CHILD
Definition: misc.hh:1116
gem5::ArmISA::MISCREG_HYP_NS_RD
@ MISCREG_HYP_NS_RD
Definition: misc.hh:1132
gem5::ArmISA::ISA::clear32
void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
Definition: isa.cc:227
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: misc.hh:820
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::rao
chain rao(uint64_t mask) const
Definition: isa.hh:168
gem5::ArmISA::ISA::inSecureState
bool inSecureState() const
Return true if the PE is in Secure state.
Definition: isa.cc:2535
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privNonSecure
chain privNonSecure(bool v=true) const
Definition: isa.hh:266
gem5::ArmISA::ISA::haveGICv3CpuIfc
bool haveGICv3CpuIfc() const
Returns true if the ISA has a GICv3 cpu interface.
Definition: isa.hh:1005
gem5::ArmISA::ISA::assert64
void assert64()
Definition: isa.hh:615
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:601
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
gem5::ArmISA::ISA::impdefAsNop
bool impdefAsNop
If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED ...
Definition: isa.hh:104
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:61
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::ArmISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:742
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: misc.hh:761
gem5::ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition: misc.hh:1105
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::userSecureRead
chain userSecureRead(bool v=true) const
Definition: isa.hh:233
gem5::ArmISA::MISCREG_HYP_NS_WR
@ MISCREG_HYP_NS_WR
Definition: misc.hh:1133

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