gem5  v22.0.0.2
isa.hh
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40 
41 #ifndef __ARCH_ARM_ISA_HH__
42 #define __ARCH_ARM_ISA_HH__
43 
44 #include "arch/arm/isa_device.hh"
45 #include "arch/arm/mmu.hh"
46 #include "arch/arm/pcstate.hh"
47 #include "arch/arm/regs/int.hh"
48 #include "arch/arm/regs/misc.hh"
49 #include "arch/arm/self_debug.hh"
50 #include "arch/arm/system.hh"
51 #include "arch/arm/types.hh"
52 #include "arch/arm/utility.hh"
53 #include "arch/generic/isa.hh"
54 #include "debug/Checkpoint.hh"
55 #include "enums/DecoderFlavor.hh"
56 #include "sim/sim_object.hh"
57 
58 namespace gem5
59 {
60 
61 struct ArmISAParams;
62 struct DummyArmISADeviceParams;
63 class Checkpoint;
64 class EventManager;
65 
66 namespace ArmISA
67 {
68  class ISA : public BaseISA
69  {
70  protected:
71  // Parent system
73 
74  // Micro Architecture
75  const enums::DecoderFlavor _decoderFlavor;
76 
79 
80  // PMU belonging to this ISA
82 
83  // Generic timer interface belonging to this ISA
84  std::unique_ptr<BaseISADevice> timer;
85 
86  // GICv3 CPU interface belonging to this ISA
87  std::unique_ptr<BaseISADevice> gicv3CpuInterface;
88 
89  // Cached copies of system-level properties
92  uint8_t physAddrRange;
93 
95  unsigned sveVL;
96 
99 
105 
107 
109 
112  {
113  uint32_t lower; // Lower half mapped to this register
114  uint32_t upper; // Upper half mapped to this register
115  uint64_t _reset; // value taken on reset (i.e. initialization)
116  uint64_t _res0; // reserved
117  uint64_t _res1; // reserved
118  uint64_t _raz; // read as zero (fixed at 0)
119  uint64_t _rao; // read as one (fixed at 1)
120  public:
122  lower(0), upper(0),
123  _reset(0), _res0(0), _res1(0), _raz(0), _rao(0) {}
124  uint64_t reset() const { return _reset; }
125  uint64_t res0() const { return _res0; }
126  uint64_t res1() const { return _res1; }
127  uint64_t raz() const { return _raz; }
128  uint64_t rao() const { return _rao; }
129  // raz/rao implies writes ignored
130  uint64_t wi() const { return _raz | _rao; }
131  };
132 
135 
137  {
139  std::bitset<NUM_MISCREG_INFOS> &info;
141  public:
142  chain
143  mapsTo(uint32_t l, uint32_t u = 0) const
144  {
145  entry.lower = l;
146  entry.upper = u;
147  return *this;
148  }
149  chain
150  res0(uint64_t mask) const
151  {
152  entry._res0 = mask;
153  return *this;
154  }
155  chain
156  res1(uint64_t mask) const
157  {
158  entry._res1 = mask;
159  return *this;
160  }
161  chain
162  raz(uint64_t mask) const
163  {
164  entry._raz = mask;
165  return *this;
166  }
167  chain
168  rao(uint64_t mask) const
169  {
170  entry._rao = mask;
171  return *this;
172  }
173  chain
174  implemented(bool v = true) const
175  {
177  return *this;
178  }
179  chain
181  {
182  return implemented(false);
183  }
184  chain
185  unverifiable(bool v = true) const
186  {
188  return *this;
189  }
190  chain
191  warnNotFail(bool v = true) const
192  {
194  return *this;
195  }
196  chain
197  mutex(bool v = true) const
198  {
199  info[MISCREG_MUTEX] = v;
200  return *this;
201  }
202  chain
203  banked(bool v = true) const
204  {
205  info[MISCREG_BANKED] = v;
206  return *this;
207  }
208  chain
209  banked64(bool v = true) const
210  {
212  return *this;
213  }
214  chain
215  bankedChild(bool v = true) const
216  {
218  return *this;
219  }
220  chain
221  userNonSecureRead(bool v = true) const
222  {
224  return *this;
225  }
226  chain
227  userNonSecureWrite(bool v = true) const
228  {
230  return *this;
231  }
232  chain
233  userSecureRead(bool v = true) const
234  {
236  return *this;
237  }
238  chain
239  userSecureWrite(bool v = true) const
240  {
242  return *this;
243  }
244  chain
245  user(bool v = true) const
246  {
249  userSecureRead(v);
251  return *this;
252  }
253  chain
254  privNonSecureRead(bool v = true) const
255  {
257  return *this;
258  }
259  chain
260  privNonSecureWrite(bool v = true) const
261  {
263  return *this;
264  }
265  chain
266  privNonSecure(bool v = true) const
267  {
270  return *this;
271  }
272  chain
273  privSecureRead(bool v = true) const
274  {
276  return *this;
277  }
278  chain
279  privSecureWrite(bool v = true) const
280  {
282  return *this;
283  }
284  chain
285  privSecure(bool v = true) const
286  {
287  privSecureRead(v);
289  return *this;
290  }
291  chain
292  priv(bool v = true) const
293  {
294  privSecure(v);
295  privNonSecure(v);
296  return *this;
297  }
298  chain
299  privRead(bool v = true) const
300  {
301  privSecureRead(v);
303  return *this;
304  }
305  chain
306  hypE2HSecureRead(bool v = true) const
307  {
309  return *this;
310  }
311  chain
312  hypE2HNonSecureRead(bool v = true) const
313  {
315  return *this;
316  }
317  chain
318  hypE2HRead(bool v = true) const
319  {
322  return *this;
323  }
324  chain
325  hypE2HSecureWrite(bool v = true) const
326  {
328  return *this;
329  }
330  chain
331  hypE2HNonSecureWrite(bool v = true) const
332  {
334  return *this;
335  }
336  chain
337  hypE2HWrite(bool v = true) const
338  {
341  return *this;
342  }
343  chain
344  hypE2H(bool v = true) const
345  {
346  hypE2HRead(v);
347  hypE2HWrite(v);
348  return *this;
349  }
350  chain
351  hypSecureRead(bool v = true) const
352  {
354  return *this;
355  }
356  chain
357  hypNonSecureRead(bool v = true) const
358  {
360  return *this;
361  }
362  chain
363  hypRead(bool v = true) const
364  {
365  hypE2HRead(v);
366  hypSecureRead(v);
368  return *this;
369  }
370  chain
371  hypSecureWrite(bool v = true) const
372  {
374  return *this;
375  }
376  chain
377  hypNonSecureWrite(bool v = true) const
378  {
380  return *this;
381  }
382  chain
383  hypWrite(bool v = true) const
384  {
385  hypE2HWrite(v);
386  hypSecureWrite(v);
388  return *this;
389  }
390  chain
391  hypSecure(bool v = true) const
392  {
395  hypSecureRead(v);
396  hypSecureWrite(v);
397  return *this;
398  }
399  chain
400  hyp(bool v = true) const
401  {
402  hypRead(v);
403  hypWrite(v);
404  return *this;
405  }
406  chain
407  monE2HRead(bool v = true) const
408  {
410  return *this;
411  }
412  chain
413  monE2HWrite(bool v = true) const
414  {
416  return *this;
417  }
418  chain
419  monE2H(bool v = true) const
420  {
421  monE2HRead(v);
422  monE2HWrite(v);
423  return *this;
424  }
425  chain
426  monSecureRead(bool v = true) const
427  {
428  monE2HRead(v);
430  return *this;
431  }
432  chain
433  monSecureWrite(bool v = true) const
434  {
435  monE2HWrite(v);
437  return *this;
438  }
439  chain
440  monNonSecureRead(bool v = true) const
441  {
442  monE2HRead(v);
444  return *this;
445  }
446  chain
447  monNonSecureWrite(bool v = true) const
448  {
449  monE2HWrite(v);
451  return *this;
452  }
453  chain
454  mon(bool v = true) const
455  {
456  monSecureRead(v);
457  monSecureWrite(v);
460  return *this;
461  }
462  chain
463  monSecure(bool v = true) const
464  {
465  monSecureRead(v);
466  monSecureWrite(v);
467  return *this;
468  }
469  chain
470  monNonSecure(bool v = true) const
471  {
474  return *this;
475  }
476  chain
477  allPrivileges(bool v = true) const
478  {
481  userSecureRead(v);
485  privSecureRead(v);
487  hypRead(v);
488  hypWrite(v);
489  monSecureRead(v);
490  monSecureWrite(v);
493  return *this;
494  }
495  chain
496  nonSecure(bool v = true) const
497  {
502  hypRead(v);
503  hypWrite(v);
506  return *this;
507  }
508  chain
509  secure(bool v = true) const
510  {
511  userSecureRead(v);
513  privSecureRead(v);
515  monSecureRead(v);
516  monSecureWrite(v);
517  return *this;
518  }
519  chain
520  reads(bool v) const
521  {
523  userSecureRead(v);
525  privSecureRead(v);
526  hypRead(v);
527  monSecureRead(v);
529  return *this;
530  }
531  chain
532  writes(bool v) const
533  {
538  hypWrite(v);
539  monSecureWrite(v);
541  return *this;
542  }
543  chain
545  {
546  user(0);
547  return *this;
548  }
549  chain highest(ArmSystem *const sys) const;
551  std::bitset<NUM_MISCREG_INFOS> &i)
552  : entry(e),
553  info(i)
554  {
555  // force unimplemented registers to be thusly declared
556  implemented(1);
557  }
558  };
559 
560  const MiscRegLUTEntryInitializer
561  InitReg(uint32_t reg)
562  {
564  miscRegInfo[reg]);
565  }
566 
568 
570  const RegId *intRegMap;
571 
572  void
573  updateRegMap(CPSR cpsr)
574  {
575  if (cpsr.width == 0) {
576  intRegMap = int_reg::Reg64Map;
577  } else {
578  switch (cpsr.mode) {
579  case MODE_USER:
580  case MODE_SYSTEM:
581  intRegMap = int_reg::RegUsrMap;
582  break;
583  case MODE_FIQ:
584  intRegMap = int_reg::RegFiqMap;
585  break;
586  case MODE_IRQ:
587  intRegMap = int_reg::RegIrqMap;
588  break;
589  case MODE_SVC:
590  intRegMap = int_reg::RegSvcMap;
591  break;
592  case MODE_MON:
593  intRegMap = int_reg::RegMonMap;
594  break;
595  case MODE_ABORT:
596  intRegMap = int_reg::RegAbtMap;
597  break;
598  case MODE_HYP:
599  intRegMap = int_reg::RegHypMap;
600  break;
601  case MODE_UNDEFINED:
602  intRegMap = int_reg::RegUndMap;
603  break;
604  default:
605  panic("Unrecognized mode setting in CPSR.\n");
606  }
607  }
608  }
609 
612 
613  public:
614  void clear();
615 
616  protected:
617  void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst);
618  void clear64(const ArmISAParams &p);
619  void initID32(const ArmISAParams &p);
620  void initID64(const ArmISAParams &p);
621 
626 
627  public:
628  SelfDebug*
629  getSelfDebug() const
630  {
631  return selfDebug;
632  }
633 
634  static SelfDebug*
636  {
637  auto *arm_isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
638  return arm_isa->getSelfDebug();
639  }
640 
641  const ArmRelease* getRelease() const { return release; }
642 
643  RegVal readMiscRegNoEffect(int misc_reg) const;
644  RegVal readMiscReg(int misc_reg);
645  void setMiscRegNoEffect(int misc_reg, RegVal val);
646  void setMiscReg(int misc_reg, RegVal val);
647 
648  RegId
649  flattenRegId(const RegId& regId) const
650  {
651  switch (regId.classValue()) {
652  case IntRegClass:
653  return RegId(IntRegClass, flattenIntIndex(regId.index()));
654  case FloatRegClass:
655  return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
656  case VecRegClass:
657  return RegId(VecRegClass, flattenVecIndex(regId.index()));
658  case VecElemClass:
659  return RegId(VecElemClass, flattenVecElemIndex(regId.index()));
660  case VecPredRegClass:
661  return RegId(VecPredRegClass,
662  flattenVecPredIndex(regId.index()));
663  case CCRegClass:
664  return RegId(CCRegClass, flattenCCIndex(regId.index()));
665  case MiscRegClass:
666  return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
667  case InvalidRegClass:
668  return RegId();
669  }
670  panic("Unrecognized register class %d.", regId.classValue());
671  }
672 
673  int
674  flattenIntIndex(int reg) const
675  {
676  assert(reg >= 0);
677  if (reg < int_reg::NumArchRegs) {
678  return intRegMap[reg];
679  } else if (reg < int_reg::NumRegs) {
680  return reg;
681  } else if (reg == int_reg::Spx) {
682  CPSR cpsr = miscRegs[MISCREG_CPSR];
684  (OperatingMode) (uint8_t) cpsr.mode);
685  if (!cpsr.sp && el != EL0)
686  return int_reg::Sp0;
687  switch (el) {
688  case EL3:
689  return int_reg::Sp3;
690  case EL2:
691  return int_reg::Sp2;
692  case EL1:
693  return int_reg::Sp1;
694  case EL0:
695  return int_reg::Sp0;
696  default:
697  panic("Invalid exception level");
698  return 0; // Never happens.
699  }
700  } else {
701  return flattenIntRegModeIndex(reg);
702  }
703  }
704 
705  int
707  {
708  assert(reg >= 0);
709  return reg;
710  }
711 
712  int
713  flattenVecIndex(int reg) const
714  {
715  assert(reg >= 0);
716  return reg;
717  }
718 
719  int
721  {
722  assert(reg >= 0);
723  return reg;
724  }
725 
726  int
728  {
729  assert(reg >= 0);
730  return reg;
731  }
732 
733  int
734  flattenCCIndex(int reg) const
735  {
736  assert(reg >= 0);
737  return reg;
738  }
739 
740  int
742  {
743  assert(reg >= 0);
744  int flat_idx = reg;
745 
746  if (reg == MISCREG_SPSR) {
747  CPSR cpsr = miscRegs[MISCREG_CPSR];
748  switch (cpsr.mode) {
749  case MODE_EL0T:
750  warn("User mode does not have SPSR\n");
751  flat_idx = MISCREG_SPSR;
752  break;
753  case MODE_EL1T:
754  case MODE_EL1H:
755  flat_idx = MISCREG_SPSR_EL1;
756  break;
757  case MODE_EL2T:
758  case MODE_EL2H:
759  flat_idx = MISCREG_SPSR_EL2;
760  break;
761  case MODE_EL3T:
762  case MODE_EL3H:
763  flat_idx = MISCREG_SPSR_EL3;
764  break;
765  case MODE_USER:
766  warn("User mode does not have SPSR\n");
767  flat_idx = MISCREG_SPSR;
768  break;
769  case MODE_FIQ:
770  flat_idx = MISCREG_SPSR_FIQ;
771  break;
772  case MODE_IRQ:
773  flat_idx = MISCREG_SPSR_IRQ;
774  break;
775  case MODE_SVC:
776  flat_idx = MISCREG_SPSR_SVC;
777  break;
778  case MODE_MON:
779  flat_idx = MISCREG_SPSR_MON;
780  break;
781  case MODE_ABORT:
782  flat_idx = MISCREG_SPSR_ABT;
783  break;
784  case MODE_HYP:
785  flat_idx = MISCREG_SPSR_HYP;
786  break;
787  case MODE_UNDEFINED:
788  flat_idx = MISCREG_SPSR_UND;
789  break;
790  default:
791  warn("Trying to access SPSR in an invalid mode: %d\n",
792  cpsr.mode);
793  flat_idx = MISCREG_SPSR;
794  break;
795  }
796  } else if (miscRegInfo[reg][MISCREG_MUTEX]) {
797  // Mutually exclusive CP15 register
798  switch (reg) {
799  case MISCREG_PRRR_MAIR0:
802  {
803  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
804  // If the muxed reg has been flattened, work out the
805  // offset and apply it to the unmuxed reg
806  int idxOffset = reg - MISCREG_PRRR_MAIR0;
807  if (ttbcr.eae)
808  flat_idx = flattenMiscIndex(MISCREG_MAIR0 +
809  idxOffset);
810  else
811  flat_idx = flattenMiscIndex(MISCREG_PRRR +
812  idxOffset);
813  }
814  break;
815  case MISCREG_NMRR_MAIR1:
818  {
819  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
820  // If the muxed reg has been flattened, work out the
821  // offset and apply it to the unmuxed reg
822  int idxOffset = reg - MISCREG_NMRR_MAIR1;
823  if (ttbcr.eae)
824  flat_idx = flattenMiscIndex(MISCREG_MAIR1 +
825  idxOffset);
826  else
827  flat_idx = flattenMiscIndex(MISCREG_NMRR +
828  idxOffset);
829  }
830  break;
832  {
833  PMSELR pmselr = miscRegs[MISCREG_PMSELR];
834  if (pmselr.sel == 31)
836  else
838  }
839  break;
840  default:
841  panic("Unrecognized misc. register.\n");
842  break;
843  }
844  } else {
846  bool secure_reg = !highestELIs64 && inSecureState();
847  flat_idx += secure_reg ? 2 : 1;
848  } else {
849  flat_idx = snsBankedIndex64((MiscRegIndex)reg,
850  !inSecureState());
851  }
852  }
853  return flat_idx;
854  }
855 
860  int redirectRegVHE(int misc_reg);
861 
862  int
864  {
865  int reg_as_int = static_cast<int>(reg);
867  reg_as_int += (release->has(ArmExtension::SECURITY) && !ns) ?
868  2 : 1;
869  }
870  return reg_as_int;
871  }
872 
874  getMiscIndices(int misc_reg) const
875  {
876  // Note: indexes of AArch64 registers are left unchanged
877  int flat_idx = flattenMiscIndex(misc_reg);
878 
879  if (lookUpMiscReg[flat_idx].lower == 0) {
880  return std::make_pair(flat_idx, 0);
881  }
882 
883  // do additional S/NS flattenings if mapped to NS while in S
884  bool S = !highestELIs64 && inSecureState();
885 
886  int lower = lookUpMiscReg[flat_idx].lower;
887  int upper = lookUpMiscReg[flat_idx].upper;
888  // upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op)
889  lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD];
890  upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD];
891  return std::make_pair(lower, upper);
892  }
893 
895  bool inSecureState() const;
896 
900  ExceptionLevel currEL() const;
901 
902  unsigned getCurSveVecLenInBits() const;
903 
904  unsigned getCurSveVecLenInBitsAtReset() const { return sveVL * 128; }
905 
906  template <typename Elem>
907  static void
908  zeroSveVecRegUpperPart(Elem *v, unsigned eCount)
909  {
910  static_assert(sizeof(Elem) <= sizeof(uint64_t),
911  "Elem type is too large.");
912  eCount *= (sizeof(uint64_t) / sizeof(Elem));
913  for (int i = 16 / sizeof(Elem); i < eCount; ++i) {
914  v[i] = 0;
915  }
916  }
917 
918  void serialize(CheckpointOut &cp) const override;
919  void unserialize(CheckpointIn &cp) override;
920 
921  void startup() override;
922 
923  void setupThreadContext();
924 
925  PCStateBase *
926  newPCState(Addr new_inst_addr=0) const override
927  {
928  return new PCState(new_inst_addr);
929  }
930 
931  void takeOverFrom(ThreadContext *new_tc,
932  ThreadContext *old_tc) override;
933 
934  enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; }
935 
937  bool
939  {
940  // gicv3CpuInterface is initialized at startup time, hence
941  // trying to read its value before the startup stage will lead
942  // to an error
943  assert(afterStartup);
944  return gicv3CpuInterface != nullptr;
945  }
946 
947  PARAMS(ArmISA);
948 
949  ISA(const Params &p);
950 
951  uint64_t
952  getExecutingAsid() const override
953  {
955  }
956 
957  bool
958  inUserMode() const override
959  {
960  CPSR cpsr = miscRegs[MISCREG_CPSR];
961  return ArmISA::inUserMode(cpsr);
962  }
963 
964  void copyRegsFrom(ThreadContext *src) override;
965 
966  void handleLockedRead(const RequestPtr &req) override;
967  void handleLockedRead(ExecContext *xc, const RequestPtr &req) override;
968 
969  bool handleLockedWrite(const RequestPtr &req,
970  Addr cacheBlockMask) override;
971  bool handleLockedWrite(ExecContext *xc, const RequestPtr &req,
972  Addr cacheBlockMask) override;
973 
974  void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override;
976  Addr cacheBlockMask) override;
977  void handleLockedSnoopHit() override;
978  void handleLockedSnoopHit(ExecContext *xc) override;
979 
980  void globalClearExclusive() override;
981  void globalClearExclusive(ExecContext *xc) override;
982  };
983 
984 } // namespace ArmISA
985 } // namespace gem5
986 
987 #endif
gem5::ArmISA::MISCREG_USR_NS_RD
@ MISCREG_USR_NS_RD
Definition: misc.hh:1121
isa_device.hh
gem5::ArmISA::MISCREG_PRI_S_WR
@ MISCREG_PRI_S_WR
Definition: misc.hh:1129
gem5::ArmISA::MODE_EL2H
@ MODE_EL2H
Definition: types.hh:285
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::ISA::newPCState
PCStateBase * newPCState(Addr new_inst_addr=0) const override
Definition: isa.hh:926
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HWrite
chain hypE2HWrite(bool v=true) const
Definition: isa.hh:337
gem5::ArmISA::ISA::PARAMS
PARAMS(ArmISA)
gem5::ArmISA::MISCREG_USR_NS_WR
@ MISCREG_USR_NS_WR
Definition: misc.hh:1122
gem5::ArmISA::MISCREG_PMCCFILTR
@ MISCREG_PMCCFILTR
Definition: misc.hh:362
gem5::ArmISA::ISA::addressTranslation64
void addressTranslation64(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2135
gem5::ArmISA::ISA::dummyDevice
DummyISADevice dummyDevice
Dummy device for to handle non-existing ISA devices.
Definition: isa.hh:78
gem5::ArmISA::ISA::zeroSveVecRegUpperPart
static void zeroSveVecRegUpperPart(Elem *v, unsigned eCount)
Definition: isa.hh:908
gem5::ArmISA::ISA::MiscRegLUTEntry::lower
uint32_t lower
Definition: isa.hh:113
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monE2H
chain monE2H(bool v=true) const
Definition: isa.hh:419
gem5::ArmISA::ISA::getSelfDebug
static SelfDebug * getSelfDebug(ThreadContext *tc)
Definition: isa.hh:635
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:291
gem5::ArmISA::ISA::currEL
ExceptionLevel currEL() const
Returns the current Exception Level (EL) of the ISA object.
Definition: isa.cc:2067
gem5::ArmISA::MISCREG_PRI_S_RD
@ MISCREG_PRI_S_RD
Definition: misc.hh:1128
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:292
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:65
warn
#define warn(...)
Definition: logging.hh:246
gem5::ArmISA::ISA::selfDebug
SelfDebug * selfDebug
Definition: isa.hh:108
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::MISCREG_BANKED64
@ MISCREG_BANKED64
Definition: misc.hh:1112
gem5::ArmISA::ISA::MiscRegLUTEntry::_raz
uint64_t _raz
Definition: isa.hh:118
gem5::ArmISA::ISA::getCurSveVecLenInBits
unsigned getCurSveVecLenInBits() const
Definition: isa.cc:2075
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:289
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privNonSecureWrite
chain privNonSecureWrite(bool v=true) const
Definition: isa.hh:260
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:674
gem5::ArmISA::ISA::gicv3CpuInterface
std::unique_ptr< BaseISADevice > gicv3CpuInterface
Definition: isa.hh:87
gem5::ArmISA::MISCREG_PRRR_MAIR0_S
@ MISCREG_PRRR_MAIR0_S
Definition: misc.hh:86
gem5::ArmISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:753
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::warnNotFail
chain warnNotFail(bool v=true) const
Definition: isa.hh:191
gem5::ArmISA::ISA::clear
void clear()
Definition: isa.cc:146
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:400
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mutex
chain mutex(bool v=true) const
Definition: isa.hh:197
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::ArmISA::MISCREG_PRRR_MAIR0_NS
@ MISCREG_PRRR_MAIR0_NS
Definition: misc.hh:85
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::InvalidRegClass
@ InvalidRegClass
Definition: reg_class.hh:67
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::allPrivileges
chain allPrivileges(bool v=true) const
Definition: isa.hh:477
gem5::ArmISA::ISA::haveLargeAsid64
bool haveLargeAsid64
Definition: isa.hh:91
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::priv
chain priv(bool v=true) const
Definition: isa.hh:292
gem5::ArmISA::MODE_EL2T
@ MODE_EL2T
Definition: types.hh:284
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::ArmISA::ISA::takeOverFrom
void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override
Definition: isa.cc:557
gem5::ArmISA::ISA::handleLockedSnoop
void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override
Definition: isa.cc:2296
gem5::ArmISA::ISA::initID32
void initID32(const ArmISAParams &p)
Definition: isa.cc:339
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:295
gem5::ArmISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:958
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::ArmISA::MODE_EL1H
@ MODE_EL1H
Definition: types.hh:283
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:290
gem5::ArmISA::MISCREG_MON_NS0_WR
@ MISCREG_MON_NS0_WR
Definition: misc.hh:1142
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::ArmISA::ISA::updateRegMap
void updateRegMap(CPSR cpsr)
Definition: isa.hh:573
gem5::ArmISA::ISA::release
const ArmRelease * release
This could be either a FS or a SE release.
Definition: isa.hh:98
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privNonSecureRead
chain privNonSecureRead(bool v=true) const
Definition: isa.hh:254
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::secure
chain secure(bool v=true) const
Definition: isa.hh:509
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypWrite
chain hypWrite(bool v=true) const
Definition: isa.hh:383
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmISA::ISA::timer
std::unique_ptr< BaseISADevice > timer
Definition: isa.hh:84
gem5::ArmISA::ISA::MiscRegLUTEntry::MiscRegLUTEntry
MiscRegLUTEntry()
Definition: isa.hh:121
gem5::ArmISA::MISCREG_HYP_E2H_NS_RD
@ MISCREG_HYP_E2H_NS_RD
Definition: misc.hh:1136
gem5::ArmISA::MISCREG_PRI_NS_WR
@ MISCREG_PRI_NS_WR
Definition: misc.hh:1127
gem5::ArmISA::ISA::MiscRegLUTEntry
MiscReg metadata.
Definition: isa.hh:111
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypSecureRead
chain hypSecureRead(bool v=true) const
Definition: isa.hh:351
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::info
std::bitset< NUM_MISCREG_INFOS > & info
Definition: isa.hh:139
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: misc.hh:261
gem5::ArmISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:727
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HNonSecureWrite
chain hypE2HNonSecureWrite(bool v=true) const
Definition: isa.hh:331
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ArmISA::ISA::MiscRegLUTEntry::upper
uint32_t upper
Definition: isa.hh:114
gem5::ArmISA::ISA::MiscRegLUTEntry::_rao
uint64_t _rao
Definition: isa.hh:119
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::res0
chain res0(uint64_t mask) const
Definition: isa.hh:150
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypNonSecureRead
chain hypNonSecureRead(bool v=true) const
Definition: isa.hh:357
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privSecure
chain privSecure(bool v=true) const
Definition: isa.hh:285
gem5::ArmISA::ISA::MiscRegLUTEntry::_reset
uint64_t _reset
Definition: isa.hh:115
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition: misc_types.hh:332
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecureWrite
chain monNonSecureWrite(bool v=true) const
Definition: isa.hh:447
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:274
gem5::ArmISA::ISA::intRegMap
const RegId * intRegMap
Definition: isa.hh:570
gem5::ArmISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:564
gem5::ArmISA::MISCREG_NMRR_MAIR1
@ MISCREG_NMRR_MAIR1
Definition: misc.hh:87
gem5::ArmISA::MISCREG_PRRR_MAIR0
@ MISCREG_PRRR_MAIR0
Definition: misc.hh:84
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:390
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: misc.hh:66
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmISA::ISA::getCurSveVecLenInBitsAtReset
unsigned getCurSveVecLenInBitsAtReset() const
Definition: isa.hh:904
gem5::ArmISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:2119
gem5::ArmISA::ISA::MiscRegLUTEntry::rao
uint64_t rao() const
Definition: isa.hh:128
gem5::ArmISA::ISA::sveVL
unsigned sveVL
SVE vector length in quadwords.
Definition: isa.hh:95
gem5::ArmISA::MISCREG_NMRR_MAIR1_NS
@ MISCREG_NMRR_MAIR1_NS
Definition: misc.hh:88
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::chain
const typedef MiscRegLUTEntryInitializer & chain
Definition: isa.hh:140
system.hh
gem5::ArmISA::MISCREG_IMPLEMENTED
@ MISCREG_IMPLEMENTED
Definition: misc.hh:1101
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ArmISA::MISCREG_USR_S_WR
@ MISCREG_USR_S_WR
Definition: misc.hh:1124
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::userSecureWrite
chain userSecureWrite(bool v=true) const
Definition: isa.hh:239
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HNonSecureRead
chain hypE2HNonSecureRead(bool v=true) const
Definition: isa.hh:312
gem5::ArmISA::MODE_EL3H
@ MODE_EL3H
Definition: types.hh:287
types.hh
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HSecureWrite
chain hypE2HSecureWrite(bool v=true) const
Definition: isa.hh:325
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2H
chain hypE2H(bool v=true) const
Definition: isa.hh:344
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::ArmISA::miscRegInfo
std::bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: misc.cc:806
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypNonSecureWrite
chain hypNonSecureWrite(bool v=true) const
Definition: isa.hh:377
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privRead
chain privRead(bool v=true) const
Definition: isa.hh:299
gem5::ArmISA::ISA::MiscRegLUTEntry::_res1
uint64_t _res1
Definition: isa.hh:117
gem5::ArmISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:1089
gem5::ArmISA::ISA::initID64
void initID64(const ArmISAParams &p)
Definition: isa.cc:392
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
mmu.hh
gem5::ArmISA::ISA::handleLockedRead
void handleLockedRead(const RequestPtr &req) override
Definition: isa.cc:2308
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::ArmRelease::has
bool has(ArmExtension ext) const
Definition: system.hh:75
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::unverifiable
chain unverifiable(bool v=true) const
Definition: isa.hh:185
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypSecureWrite
chain hypSecureWrite(bool v=true) const
Definition: isa.hh:371
gem5::Flags< FlagsType >
gem5::ArmISA::MODE_EL3T
@ MODE_EL3T
Definition: types.hh:286
gem5::ArmISA::ISA::pmu
BaseISADevice * pmu
Definition: isa.hh:81
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::userNonSecureWrite
chain userNonSecureWrite(bool v=true) const
Definition: isa.hh:227
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privSecureRead
chain privSecureRead(bool v=true) const
Definition: isa.hh:273
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: misc.hh:370
gem5::ArmISA::MODE_EL1T
@ MODE_EL1T
Definition: types.hh:282
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::writes
chain writes(bool v) const
Definition: isa.hh:532
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::banked64
chain banked64(bool v=true) const
Definition: isa.hh:209
gem5::ArmISA::ISA::handleLockedSnoopHit
void handleLockedSnoopHit() override
Definition: isa.cc:2326
gem5::ArmISA::cc_reg::NumRegs
@ NumRegs
Definition: cc.hh:60
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:294
gem5::ArmISA::ISA::clear64
void clear64(const ArmISAParams &p)
Definition: isa.cc:290
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::banked
chain banked(bool v=true) const
Definition: isa.hh:203
sim_object.hh
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monSecureWrite
chain monSecureWrite(bool v=true) const
Definition: isa.hh:433
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::ArmISA::MISCREG_PMSELR
@ MISCREG_PMSELR
Definition: misc.hh:357
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: misc.hh:379
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::ArmISA::ISA::snsBankedIndex64
int snsBankedIndex64(MiscRegIndex reg, bool ns) const
Definition: isa.hh:863
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::ISA::globalClearExclusive
void globalClearExclusive() override
Definition: isa.cc:2398
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::ArmISA::ISA::getMiscIndices
std::pair< int, int > getMiscIndices(int misc_reg) const
Definition: isa.hh:874
gem5::ArmISA::ISA::MiscRegLUTEntry::res0
uint64_t res0() const
Definition: isa.hh:125
gem5::ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:1096
gem5::ArmISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:2126
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mapsTo
chain mapsTo(uint32_t l, uint32_t u=0) const
Definition: isa.hh:143
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::ArmISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:91
gem5::ArmISA::MISCREG_SPSR
@ MISCREG_SPSR
Definition: misc.hh:62
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::MISCREG_MON_NS1_WR
@ MISCREG_MON_NS1_WR
Definition: misc.hh:1145
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition: isa.hh:454
gem5::ArmISA::MISCREG_MUTEX
@ MISCREG_MUTEX
Definition: misc.hh:1107
gem5::ArmISA::ISA::addressTranslation
void addressTranslation(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2186
gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: misc.hh:90
gem5::ArmISA::MISCREG_HYP_E2H_S_RD
@ MISCREG_HYP_E2H_S_RD
Definition: misc.hh:1138
gem5::ArmISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:720
gem5::ArmISA::MISCREG_MON_NS1_RD
@ MISCREG_MON_NS1_RD
Definition: misc.hh:1144
gem5::ArmISA::MISCREG_HYP_S_RD
@ MISCREG_HYP_S_RD
Definition: misc.hh:1133
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:626
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:713
gem5::ArmISA::ISA::handleLockedWrite
bool handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask) override
Definition: isa.cc:2385
flags
uint8_t flags
Definition: helpers.cc:66
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monSecureRead
chain monSecureRead(bool v=true) const
Definition: isa.hh:426
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:276
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::nonSecure
chain nonSecure(bool v=true) const
Definition: isa.hh:496
gem5::ArmISA::ISA::getGICv3CPUInterface
BaseISADevice & getGICv3CPUInterface()
Definition: isa.cc:2036
gem5::ArmISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:777
gem5::ArmISA::MISCREG_BANKED
@ MISCREG_BANKED
Definition: misc.hh:1109
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:288
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecure
chain monNonSecure(bool v=true) const
Definition: isa.hh:470
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypSecure
chain hypSecure(bool v=true) const
Definition: isa.hh:391
gem5::ArmISA::ISA::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: isa.cc:519
std::pair< int, int >
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypRead
chain hypRead(bool v=true) const
Definition: isa.hh:363
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::bankedChild
chain bankedChild(bool v=true) const
Definition: isa.hh:215
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::implemented
chain implemented(bool v=true) const
Definition: isa.hh:174
gem5::ArmISA::ISA::getGenericTimer
BaseISADevice & getGenericTimer()
Definition: isa.cc:2015
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:613
gem5::ArmISA::MISCREG_PRI_NS_RD
@ MISCREG_PRI_NS_RD
Definition: misc.hh:1126
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_HYP_E2H_NS_WR
@ MISCREG_HYP_E2H_NS_WR
Definition: misc.hh:1137
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: misc.hh:376
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::unimplemented
chain unimplemented() const
Definition: isa.hh:180
gem5::ArmISA::ISA::decoderFlavor
enums::DecoderFlavor decoderFlavor() const
Definition: isa.hh:934
pcstate.hh
gem5::ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: misc.cc:1325
utility.hh
gem5::ArmISA::ISA::highestELIs64
bool highestELIs64
Definition: isa.hh:90
gem5::ArmISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:649
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: misc.hh:373
gem5::ArmRelease
Definition: system.hh:68
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::reads
chain reads(bool v) const
Definition: isa.hh:520
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::entry
struct MiscRegLUTEntry & entry
Definition: isa.hh:138
gem5::ArmISA::MISCREG_HYP_S_WR
@ MISCREG_HYP_S_WR
Definition: misc.hh:1134
gem5::ArmISA::ISA::MiscRegLUTEntry::raz
uint64_t raz() const
Definition: isa.hh:127
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ArmISA::MISCREG_MON_NS0_RD
@ MISCREG_MON_NS0_RD
Definition: misc.hh:1141
gem5::ArmISA::ISA::setupThreadContext
void setupThreadContext()
Definition: isa.cc:536
gem5::ArmISA::ISA::lookUpMiscReg
static std::vector< struct MiscRegLUTEntry > lookUpMiscReg
Metadata table accessible via the value of the register.
Definition: isa.hh:134
gem5::ArmISA::ISA::MiscRegLUTEntry::wi
uint64_t wi() const
Definition: isa.hh:130
gem5::ArmISA::MISCREG_UNVERIFIABLE
@ MISCREG_UNVERIFIABLE
Definition: misc.hh:1102
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: misc.hh:633
gem5::ArmISA::u
Bitfield< 22 > u
Definition: misc_types.hh:353
isa.hh
gem5::ArmISA::ISA::_decoderFlavor
const enums::DecoderFlavor _decoderFlavor
Definition: isa.hh:75
gem5::ArmISA::MMU::ArmTranslationType
ArmTranslationType
Definition: mmu.hh:114
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:273
gem5::ArmSystem
Definition: system.hh:91
gem5::ArmISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:706
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition: isa.cc:2254
gem5::ArmISA::MODE_EL0T
@ MODE_EL0T
Definition: types.hh:281
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monE2HRead
chain monE2HRead(bool v=true) const
Definition: isa.hh:407
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: misc.hh:65
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::ArmISA::ISA::InitReg
const MiscRegLUTEntryInitializer InitReg(uint32_t reg)
Definition: isa.hh:561
gem5::PowerISA::float_reg::NumArchRegs
const int NumArchRegs
Definition: float.hh:41
gem5::ArmISA::ISA::miscRegs
RegVal miscRegs[NUM_MISCREGS]
Definition: isa.hh:569
gem5::ArmISA::ISA::MiscRegLUTEntry::reset
uint64_t reset() const
Definition: isa.hh:124
misc.hh
gem5::ArmISA::DummyISADevice
Dummy device that prints a warning when it is accessed.
Definition: isa_device.hh:97
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::exceptUserMode
chain exceptUserMode() const
Definition: isa.hh:544
gem5::ArmISA::ISA::getSelfDebug
SelfDebug * getSelfDebug() const
Definition: isa.hh:629
gem5::ArmISA::ISA::system
ArmSystem * system
Definition: isa.hh:72
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:296
gem5::ArmISA::inUserMode
static bool inUserMode(CPSR cpsr)
Definition: utility.hh:97
gem5::ArmISA::flattenIntRegModeIndex
static int flattenIntRegModeIndex(int reg)
Definition: int.hh:554
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::MiscRegLUTEntryInitializer
MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e, std::bitset< NUM_MISCREG_INFOS > &i)
Definition: isa.hh:550
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:1111
gem5::VegaISA::l
Bitfield< 55 > l
Definition: pagetable.hh:54
gem5::ArmISA::ISA::getExecutingAsid
uint64_t getExecutingAsid() const override
Definition: isa.hh:952
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HRead
chain hypE2HRead(bool v=true) const
Definition: isa.hh:318
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer
Definition: isa.hh:136
gem5::ArmISA::MISCREG_USR_S_RD
@ MISCREG_USR_S_RD
Definition: misc.hh:1123
gem5::ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition: misc.hh:361
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monE2HWrite
chain monE2HWrite(bool v=true) const
Definition: isa.hh:413
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monSecure
chain monSecure(bool v=true) const
Definition: isa.hh:463
gem5::ArmISA::ISA::MiscRegLUTEntry::_res0
uint64_t _res0
Definition: isa.hh:116
gem5::ArmISA::MISCREG_HYP_E2H_S_WR
@ MISCREG_HYP_E2H_S_WR
Definition: misc.hh:1139
gem5::ArmISA::ISA::physAddrRange
uint8_t physAddrRange
Definition: isa.hh:92
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ArmISA::ISA::redirectRegVHE
int redirectRegVHE(int misc_reg)
Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at ...
Definition: isa.cc:607
gem5::RegId::index
constexpr RegIndex index() const
Index accessors.
Definition: reg_class.hh:188
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr() const =0
self_debug.hh
gem5::BaseISA
Definition: isa.hh:57
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition: isa.hh:400
gem5::ArmISA::ISA::afterStartup
bool afterStartup
Definition: isa.hh:106
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::userNonSecureRead
chain userNonSecureRead(bool v=true) const
Definition: isa.hh:221
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:293
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privSecureWrite
chain privSecureWrite(bool v=true) const
Definition: isa.hh:279
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::user
chain user(bool v=true) const
Definition: isa.hh:245
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::raz
chain raz(uint64_t mask) const
Definition: isa.hh:162
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HSecureRead
chain hypE2HSecureRead(bool v=true) const
Definition: isa.hh:306
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RegId::classValue
constexpr RegClassType classValue() const
Class accessor.
Definition: reg_class.hh:191
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::res1
chain res1(uint64_t mask) const
Definition: isa.hh:156
gem5::ArmISA::MISCREG_NMRR_MAIR1_S
@ MISCREG_NMRR_MAIR1_S
Definition: misc.hh:89
gem5::ArmISA::ISA::getRelease
const ArmRelease * getRelease() const
Definition: isa.hh:641
int.hh
gem5::ArmISA::MISCREG_MON_E2H_RD
@ MISCREG_MON_E2H_RD
Definition: misc.hh:1147
gem5::ArmISA::MISCREG_MON_E2H_WR
@ MISCREG_MON_E2H_WR
Definition: misc.hh:1148
gem5::ArmISA::ISA::MiscRegLUTEntry::res1
uint64_t res1() const
Definition: isa.hh:126
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: misc.hh:68
gem5::ArmISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:734
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecureRead
chain monNonSecureRead(bool v=true) const
Definition: isa.hh:440
gem5::ArmISA::MISCREG_BANKED_CHILD
@ MISCREG_BANKED_CHILD
Definition: misc.hh:1115
gem5::ArmISA::MISCREG_HYP_NS_RD
@ MISCREG_HYP_NS_RD
Definition: misc.hh:1131
gem5::ArmISA::ISA::clear32
void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
Definition: isa.cc:238
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:279
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::rao
chain rao(uint64_t mask) const
Definition: isa.hh:168
gem5::ArmISA::ISA::inSecureState
bool inSecureState() const
Return true if the PE is in Secure state.
Definition: isa.cc:2043
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privNonSecure
chain privNonSecure(bool v=true) const
Definition: isa.hh:266
gem5::ArmISA::ISA::haveGICv3CpuIfc
bool haveGICv3CpuIfc() const
Returns true if the ISA has a GICv3 cpu interface.
Definition: isa.hh:938
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::ArmISA::ISA::impdefAsNop
bool impdefAsNop
If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED ...
Definition: isa.hh:104
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:61
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::ArmISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:741
gem5::ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition: misc.hh:1104
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::userSecureRead
chain userSecureRead(bool v=true) const
Definition: isa.hh:233
gem5::ArmISA::MISCREG_HYP_NS_WR
@ MISCREG_HYP_NS_WR
Definition: misc.hh:1132

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