41 #ifndef __ARCH_ARM_ISA_HH__
42 #define __ARCH_ARM_ISA_HH__
55 #include "debug/Checkpoint.hh"
56 #include "enums/DecoderFlavor.hh"
63 struct DummyArmISADeviceParams;
85 std::unique_ptr<BaseISADevice>
timer;
127 if (cpsr.width == 0) {
157 panic(
"Unrecognized mode setting in CPSR.\n");
166 void clear()
override;
169 void clear32(
const ArmISAParams &
p,
const SCTLR &sctlr_rst);
170 void clear64(
const ArmISAParams &
p);
210 warn(
"User mode does not have SPSR\n");
226 warn(
"User mode does not have SPSR\n");
251 warn(
"Trying to access SPSR in an invalid mode: %d\n",
294 if (pmselr.sel == 31)
301 panic(
"Unrecognized misc. register.\n");
307 flat_idx += secure_reg ? 2 : 1;
325 int reg_as_int =
static_cast<int>(
reg);
327 reg_as_int += (
release->
has(ArmExtension::SECURITY) && !
ns) ?
340 return std::make_pair(flat_idx, 0);
351 return std::make_pair(lower, upper);
366 template <
typename Elem>
370 static_assert(
sizeof(Elem) <=
sizeof(uint64_t),
371 "Elem type is too large.");
372 eCount *= (
sizeof(uint64_t) /
sizeof(Elem));
373 for (
int i = 16 /
sizeof(Elem);
i < eCount; ++
i) {
388 return new PCState(new_inst_addr);
419 Addr cacheBlockMask)
override;
421 Addr cacheBlockMask)
override;
425 Addr cacheBlockMask)
override;
Base class for devices that use the MiscReg interfaces.
Dummy device that prints a warning when it is accessed.
bool inSecureState() const
Return true if the PE is in Secure state.
void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
SelfDebug * getSelfDebug() const
unsigned getCurSveVecLenInBits() const
std::pair< int, int > getMiscIndices(int misc_reg) const
ExceptionLevel currEL() const
Returns the current Exception Level (EL) of the ISA object.
void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override
void serialize(CheckpointOut &cp) const override
Serialize an object.
static SelfDebug * getSelfDebug(ThreadContext *tc)
void copyRegsFrom(ThreadContext *src) override
unsigned getCurSveVecLenInBitsAtReset() const
const enums::DecoderFlavor _decoderFlavor
void initID64(const ArmISAParams &p)
DummyISADevice dummyDevice
Dummy device for to handle non-existing ISA devices.
void setupThreadContext()
void setMiscRegNoEffect(RegIndex idx, RegVal val) override
void addressTranslation64(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
int snsBankedIndex64(MiscRegIndex reg, bool ns) const
void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override
void initID32(const ArmISAParams &p)
int flattenMiscIndex(int reg) const
RegVal miscRegs[NUM_MISCREGS]
void clear64(const ArmISAParams &p)
static void zeroSveVecRegUpperPart(Elem *v, unsigned eCount)
PCStateBase * newPCState(Addr new_inst_addr=0) const override
std::unique_ptr< BaseISADevice > timer
bool handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask) override
uint64_t getExecutingAsid() const override
void globalClearExclusive() override
void unserialize(CheckpointIn &cp) override
Unserialize an object.
void updateRegMap(CPSR cpsr)
void startup() override
startup() is the final initialization call before simulation.
int redirectRegVHE(int misc_reg)
Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at ...
BaseISADevice & getGICv3CPUInterface()
BaseISADevice & getGenericTimer()
RegVal readMiscRegNoEffect(RegIndex idx) const override
bool impdefAsNop
If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED ...
void setMiscReg(RegIndex, RegVal val) override
const ArmRelease * getRelease() const
unsigned sveVL
SVE vector length in quadwords.
const MiscRegLUTEntryInitializer InitReg(uint32_t reg)
void handleLockedRead(const RequestPtr &req) override
enums::DecoderFlavor decoderFlavor() const
void addressTranslation(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
void initializeMiscRegMetadata()
const RegId & mapIntRegId(RegIndex idx) const
const ArmRelease * release
This could be either a FS or a SE release.
RegVal readMiscReg(RegIndex idx) override
void handleLockedSnoopHit() override
std::unique_ptr< BaseISADevice > gicv3CpuInterface
bool inUserMode() const override
Metadata table accessible via the value of the register.
bool has(ArmExtension ext) const
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Register ID: describe an architectural register with its class and index.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual BaseISA * getIsaPtr() const =0
#define panic(...)
This implements a cprintf based panic() function.
@ MISCREG_PMXEVTYPER_PMCCFILTR
static bool inUserMode(CPSR cpsr)
std::vector< struct MiscRegLUTEntry > lookUpMiscReg(NUM_MISCREGS)
GenericISA::DelaySlotPCState< 4 > PCState
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< Request > RequestPtr
std::ostream CheckpointOut
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.