gem5  v21.1.0.2
isa.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010, 2012-2021 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2009 The Regents of The University of Michigan
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #ifndef __ARCH_ARM_ISA_HH__
42 #define __ARCH_ARM_ISA_HH__
43 
44 #include "arch/arm/isa_device.hh"
45 #include "arch/arm/regs/int.hh"
46 #include "arch/arm/regs/misc.hh"
47 #include "arch/arm/self_debug.hh"
48 #include "arch/arm/system.hh"
49 #include "arch/arm/tlb.hh"
50 #include "arch/arm/types.hh"
51 #include "arch/arm/utility.hh"
52 #include "arch/generic/isa.hh"
53 #include "debug/Checkpoint.hh"
54 #include "enums/DecoderFlavor.hh"
55 #include "enums/VecRegRenameMode.hh"
56 #include "sim/sim_object.hh"
57 
58 namespace gem5
59 {
60 
61 struct ArmISAParams;
62 struct DummyArmISADeviceParams;
63 class Checkpoint;
64 class EventManager;
65 
66 namespace ArmISA
67 {
68  class ISA : public BaseISA
69  {
70  protected:
71  // Parent system
73 
74  // Micro Architecture
75  const enums::DecoderFlavor _decoderFlavor;
76 
79 
80  // PMU belonging to this ISA
82 
83  // Generic timer interface belonging to this ISA
84  std::unique_ptr<BaseISADevice> timer;
85 
86  // GICv3 CPU interface belonging to this ISA
87  std::unique_ptr<BaseISADevice> gicv3CpuInterface;
88 
89  // Cached copies of system-level properties
92  bool haveLPAE;
94  bool haveCrypto;
96  uint8_t physAddrRange;
97  bool haveSVE;
98  bool haveLSE;
99  bool haveVHE;
100  bool havePAN;
102  bool haveTME;
103 
105  unsigned sveVL;
106 
112 
114 
116 
119  {
120  uint32_t lower; // Lower half mapped to this register
121  uint32_t upper; // Upper half mapped to this register
122  uint64_t _reset; // value taken on reset (i.e. initialization)
123  uint64_t _res0; // reserved
124  uint64_t _res1; // reserved
125  uint64_t _raz; // read as zero (fixed at 0)
126  uint64_t _rao; // read as one (fixed at 1)
127  public:
129  lower(0), upper(0),
130  _reset(0), _res0(0), _res1(0), _raz(0), _rao(0) {}
131  uint64_t reset() const { return _reset; }
132  uint64_t res0() const { return _res0; }
133  uint64_t res1() const { return _res1; }
134  uint64_t raz() const { return _raz; }
135  uint64_t rao() const { return _rao; }
136  // raz/rao implies writes ignored
137  uint64_t wi() const { return _raz | _rao; }
138  };
139 
142 
144  {
146  std::bitset<NUM_MISCREG_INFOS> &info;
148  public:
149  chain mapsTo(uint32_t l, uint32_t u = 0) const {
150  entry.lower = l;
151  entry.upper = u;
152  return *this;
153  }
154  chain res0(uint64_t mask) const {
155  entry._res0 = mask;
156  return *this;
157  }
158  chain res1(uint64_t mask) const {
159  entry._res1 = mask;
160  return *this;
161  }
162  chain raz(uint64_t mask) const {
163  entry._raz = mask;
164  return *this;
165  }
166  chain rao(uint64_t mask) const {
167  entry._rao = mask;
168  return *this;
169  }
170  chain implemented(bool v = true) const {
172  return *this;
173  }
175  return implemented(false);
176  }
177  chain unverifiable(bool v = true) const {
179  return *this;
180  }
181  chain warnNotFail(bool v = true) const {
183  return *this;
184  }
185  chain mutex(bool v = true) const {
186  info[MISCREG_MUTEX] = v;
187  return *this;
188  }
189  chain banked(bool v = true) const {
190  info[MISCREG_BANKED] = v;
191  return *this;
192  }
193  chain banked64(bool v = true) const {
195  return *this;
196  }
197  chain bankedChild(bool v = true) const {
199  return *this;
200  }
201  chain userNonSecureRead(bool v = true) const {
203  return *this;
204  }
205  chain userNonSecureWrite(bool v = true) const {
207  return *this;
208  }
209  chain userSecureRead(bool v = true) const {
211  return *this;
212  }
213  chain userSecureWrite(bool v = true) const {
215  return *this;
216  }
217  chain user(bool v = true) const {
220  userSecureRead(v);
222  return *this;
223  }
224  chain privNonSecureRead(bool v = true) const {
226  return *this;
227  }
228  chain privNonSecureWrite(bool v = true) const {
230  return *this;
231  }
232  chain privNonSecure(bool v = true) const {
235  return *this;
236  }
237  chain privSecureRead(bool v = true) const {
239  return *this;
240  }
241  chain privSecureWrite(bool v = true) const {
243  return *this;
244  }
245  chain privSecure(bool v = true) const {
246  privSecureRead(v);
248  return *this;
249  }
250  chain priv(bool v = true) const {
251  privSecure(v);
252  privNonSecure(v);
253  return *this;
254  }
255  chain privRead(bool v = true) const {
256  privSecureRead(v);
258  return *this;
259  }
260  chain hypE2HSecureRead(bool v = true) const {
262  return *this;
263  }
264  chain hypE2HNonSecureRead(bool v = true) const {
266  return *this;
267  }
268  chain hypE2HRead(bool v = true) const {
271  return *this;
272  }
273  chain hypE2HSecureWrite(bool v = true) const {
275  return *this;
276  }
277  chain hypE2HNonSecureWrite(bool v = true) const {
279  return *this;
280  }
281  chain hypE2HWrite(bool v = true) const {
284  return *this;
285  }
286  chain hypE2H(bool v = true) const {
287  hypE2HRead(v);
288  hypE2HWrite(v);
289  return *this;
290  }
291  chain hypSecureRead(bool v = true) const {
293  return *this;
294  }
295  chain hypNonSecureRead(bool v = true) const {
297  return *this;
298  }
299  chain hypRead(bool v = true) const {
300  hypE2HRead(v);
301  hypSecureRead(v);
303  return *this;
304  }
305  chain hypSecureWrite(bool v = true) const {
307  return *this;
308  }
309  chain hypNonSecureWrite(bool v = true) const {
311  return *this;
312  }
313  chain hypWrite(bool v = true) const {
314  hypE2HWrite(v);
315  hypSecureWrite(v);
317  return *this;
318  }
319  chain hypSecure(bool v = true) const {
322  hypSecureRead(v);
323  hypSecureWrite(v);
324  return *this;
325  }
326  chain hyp(bool v = true) const {
327  hypRead(v);
328  hypWrite(v);
329  return *this;
330  }
331  chain monE2HRead(bool v = true) const {
333  return *this;
334  }
335  chain monE2HWrite(bool v = true) const {
337  return *this;
338  }
339  chain monE2H(bool v = true) const {
340  monE2HRead(v);
341  monE2HWrite(v);
342  return *this;
343  }
344  chain monSecureRead(bool v = true) const {
345  monE2HRead(v);
347  return *this;
348  }
349  chain monSecureWrite(bool v = true) const {
350  monE2HWrite(v);
352  return *this;
353  }
354  chain monNonSecureRead(bool v = true) const {
355  monE2HRead(v);
357  return *this;
358  }
359  chain monNonSecureWrite(bool v = true) const {
360  monE2HWrite(v);
362  return *this;
363  }
364  chain mon(bool v = true) const {
365  monSecureRead(v);
366  monSecureWrite(v);
369  return *this;
370  }
371  chain monSecure(bool v = true) const {
372  monSecureRead(v);
373  monSecureWrite(v);
374  return *this;
375  }
376  chain monNonSecure(bool v = true) const {
379  return *this;
380  }
381  chain allPrivileges(bool v = true) const {
384  userSecureRead(v);
388  privSecureRead(v);
390  hypRead(v);
391  hypWrite(v);
392  monSecureRead(v);
393  monSecureWrite(v);
396  return *this;
397  }
398  chain nonSecure(bool v = true) const {
403  hypRead(v);
404  hypWrite(v);
407  return *this;
408  }
409  chain secure(bool v = true) const {
410  userSecureRead(v);
412  privSecureRead(v);
414  monSecureRead(v);
415  monSecureWrite(v);
416  return *this;
417  }
418  chain reads(bool v) const {
420  userSecureRead(v);
422  privSecureRead(v);
423  hypRead(v);
424  monSecureRead(v);
426  return *this;
427  }
428  chain writes(bool v) const {
433  hypWrite(v);
434  monSecureWrite(v);
436  return *this;
437  }
439  user(0);
440  return *this;
441  }
442  chain highest(ArmSystem *const sys) const;
444  std::bitset<NUM_MISCREG_INFOS> &i)
445  : entry(e),
446  info(i)
447  {
448  // force unimplemented registers to be thusly declared
449  implemented(1);
450  }
451  };
452 
455  miscRegInfo[reg]);
456  }
457 
459 
461  const IntRegIndex *intRegMap;
462 
463  void
464  updateRegMap(CPSR cpsr)
465  {
466  if (cpsr.width == 0) {
468  } else {
469  switch (cpsr.mode) {
470  case MODE_USER:
471  case MODE_SYSTEM:
473  break;
474  case MODE_FIQ:
476  break;
477  case MODE_IRQ:
479  break;
480  case MODE_SVC:
482  break;
483  case MODE_MON:
485  break;
486  case MODE_ABORT:
488  break;
489  case MODE_HYP:
491  break;
492  case MODE_UNDEFINED:
494  break;
495  default:
496  panic("Unrecognized mode setting in CPSR.\n");
497  }
498  }
499  }
500 
503 
504  private:
505  void assert32() { assert(((CPSR)readMiscReg(MISCREG_CPSR)).width); }
506  void assert64() { assert(!((CPSR)readMiscReg(MISCREG_CPSR)).width); }
507 
508  public:
509  void clear();
510 
511  protected:
512  void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst);
513  void clear64(const ArmISAParams &p);
514  void initID32(const ArmISAParams &p);
515  void initID64(const ArmISAParams &p);
516 
521 
522  public:
523  SelfDebug*
524  getSelfDebug() const
525  {
526  return selfDebug;
527  }
528 
529  static SelfDebug*
531  {
532  auto *arm_isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
533  return arm_isa->getSelfDebug();
534  }
535 
536  RegVal readMiscRegNoEffect(int misc_reg) const;
537  RegVal readMiscReg(int misc_reg);
538  void setMiscRegNoEffect(int misc_reg, RegVal val);
539  void setMiscReg(int misc_reg, RegVal val);
540 
541  RegId
542  flattenRegId(const RegId& regId) const
543  {
544  switch (regId.classValue()) {
545  case IntRegClass:
546  return RegId(IntRegClass, flattenIntIndex(regId.index()));
547  case FloatRegClass:
548  return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
549  case VecRegClass:
550  return RegId(VecRegClass, flattenVecIndex(regId.index()));
551  case VecElemClass:
552  return RegId(VecElemClass, flattenVecElemIndex(regId.index()),
553  regId.elemIndex());
554  case VecPredRegClass:
555  return RegId(VecPredRegClass,
556  flattenVecPredIndex(regId.index()));
557  case CCRegClass:
558  return RegId(CCRegClass, flattenCCIndex(regId.index()));
559  case MiscRegClass:
560  return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
561  }
562  return RegId();
563  }
564 
565  int
566  flattenIntIndex(int reg) const
567  {
568  assert(reg >= 0);
569  if (reg < NUM_ARCH_INTREGS) {
570  return intRegMap[reg];
571  } else if (reg < NUM_INTREGS) {
572  return reg;
573  } else if (reg == INTREG_SPX) {
574  CPSR cpsr = miscRegs[MISCREG_CPSR];
576  (OperatingMode) (uint8_t) cpsr.mode);
577  if (!cpsr.sp && el != EL0)
578  return INTREG_SP0;
579  switch (el) {
580  case EL3:
581  return INTREG_SP3;
582  case EL2:
583  return INTREG_SP2;
584  case EL1:
585  return INTREG_SP1;
586  case EL0:
587  return INTREG_SP0;
588  default:
589  panic("Invalid exception level");
590  return 0; // Never happens.
591  }
592  } else {
593  return flattenIntRegModeIndex(reg);
594  }
595  }
596 
597  int
599  {
600  assert(reg >= 0);
601  return reg;
602  }
603 
604  int
605  flattenVecIndex(int reg) const
606  {
607  assert(reg >= 0);
608  return reg;
609  }
610 
611  int
613  {
614  assert(reg >= 0);
615  return reg;
616  }
617 
618  int
620  {
621  assert(reg >= 0);
622  return reg;
623  }
624 
625  int
626  flattenCCIndex(int reg) const
627  {
628  assert(reg >= 0);
629  return reg;
630  }
631 
632  int
634  {
635  assert(reg >= 0);
636  int flat_idx = reg;
637 
638  if (reg == MISCREG_SPSR) {
639  CPSR cpsr = miscRegs[MISCREG_CPSR];
640  switch (cpsr.mode) {
641  case MODE_EL0T:
642  warn("User mode does not have SPSR\n");
643  flat_idx = MISCREG_SPSR;
644  break;
645  case MODE_EL1T:
646  case MODE_EL1H:
647  flat_idx = MISCREG_SPSR_EL1;
648  break;
649  case MODE_EL2T:
650  case MODE_EL2H:
651  flat_idx = MISCREG_SPSR_EL2;
652  break;
653  case MODE_EL3T:
654  case MODE_EL3H:
655  flat_idx = MISCREG_SPSR_EL3;
656  break;
657  case MODE_USER:
658  warn("User mode does not have SPSR\n");
659  flat_idx = MISCREG_SPSR;
660  break;
661  case MODE_FIQ:
662  flat_idx = MISCREG_SPSR_FIQ;
663  break;
664  case MODE_IRQ:
665  flat_idx = MISCREG_SPSR_IRQ;
666  break;
667  case MODE_SVC:
668  flat_idx = MISCREG_SPSR_SVC;
669  break;
670  case MODE_MON:
671  flat_idx = MISCREG_SPSR_MON;
672  break;
673  case MODE_ABORT:
674  flat_idx = MISCREG_SPSR_ABT;
675  break;
676  case MODE_HYP:
677  flat_idx = MISCREG_SPSR_HYP;
678  break;
679  case MODE_UNDEFINED:
680  flat_idx = MISCREG_SPSR_UND;
681  break;
682  default:
683  warn("Trying to access SPSR in an invalid mode: %d\n",
684  cpsr.mode);
685  flat_idx = MISCREG_SPSR;
686  break;
687  }
688  } else if (miscRegInfo[reg][MISCREG_MUTEX]) {
689  // Mutually exclusive CP15 register
690  switch (reg) {
691  case MISCREG_PRRR_MAIR0:
694  {
695  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
696  // If the muxed reg has been flattened, work out the
697  // offset and apply it to the unmuxed reg
698  int idxOffset = reg - MISCREG_PRRR_MAIR0;
699  if (ttbcr.eae)
700  flat_idx = flattenMiscIndex(MISCREG_MAIR0 +
701  idxOffset);
702  else
703  flat_idx = flattenMiscIndex(MISCREG_PRRR +
704  idxOffset);
705  }
706  break;
707  case MISCREG_NMRR_MAIR1:
710  {
711  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
712  // If the muxed reg has been flattened, work out the
713  // offset and apply it to the unmuxed reg
714  int idxOffset = reg - MISCREG_NMRR_MAIR1;
715  if (ttbcr.eae)
716  flat_idx = flattenMiscIndex(MISCREG_MAIR1 +
717  idxOffset);
718  else
719  flat_idx = flattenMiscIndex(MISCREG_NMRR +
720  idxOffset);
721  }
722  break;
724  {
725  PMSELR pmselr = miscRegs[MISCREG_PMSELR];
726  if (pmselr.sel == 31)
728  else
730  }
731  break;
732  default:
733  panic("Unrecognized misc. register.\n");
734  break;
735  }
736  } else {
738  bool secureReg = haveSecurity && !highestELIs64 &&
741  flat_idx += secureReg ? 2 : 1;
742  } else {
743  flat_idx = snsBankedIndex64((MiscRegIndex)reg,
746  }
747  }
748  return flat_idx;
749  }
750 
755  int
756  redirectRegVHE(ThreadContext * tc, int misc_reg)
757  {
758  const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
759  if (hcr.e2h == 0x0 || currEL(tc) != EL2)
760  return misc_reg;
762  bool sec_el2 = scr.eel2 && haveSecEL2;
763  switch(misc_reg) {
764  case MISCREG_SPSR_EL1:
765  return MISCREG_SPSR_EL2;
766  case MISCREG_ELR_EL1:
767  return MISCREG_ELR_EL2;
768  case MISCREG_SCTLR_EL1:
769  return MISCREG_SCTLR_EL2;
770  case MISCREG_CPACR_EL1:
771  return MISCREG_CPTR_EL2;
772  // case :
773  // return MISCREG_TRFCR_EL2;
774  case MISCREG_TTBR0_EL1:
775  return MISCREG_TTBR0_EL2;
776  case MISCREG_TTBR1_EL1:
777  return MISCREG_TTBR1_EL2;
778  case MISCREG_TCR_EL1:
779  return MISCREG_TCR_EL2;
780  case MISCREG_AFSR0_EL1:
781  return MISCREG_AFSR0_EL2;
782  case MISCREG_AFSR1_EL1:
783  return MISCREG_AFSR1_EL2;
784  case MISCREG_ESR_EL1:
785  return MISCREG_ESR_EL2;
786  case MISCREG_FAR_EL1:
787  return MISCREG_FAR_EL2;
788  case MISCREG_MAIR_EL1:
789  return MISCREG_MAIR_EL2;
790  case MISCREG_AMAIR_EL1:
791  return MISCREG_AMAIR_EL2;
792  case MISCREG_VBAR_EL1:
793  return MISCREG_VBAR_EL2;
795  return MISCREG_CONTEXTIDR_EL2;
796  case MISCREG_CNTKCTL_EL1:
797  return MISCREG_CNTHCTL_EL2;
799  return sec_el2? MISCREG_CNTHPS_TVAL_EL2:
802  return sec_el2? MISCREG_CNTHPS_CTL_EL2:
805  return sec_el2? MISCREG_CNTHPS_CVAL_EL2:
808  return sec_el2? MISCREG_CNTHVS_TVAL_EL2:
811  return sec_el2? MISCREG_CNTHVS_CTL_EL2:
814  return sec_el2? MISCREG_CNTHVS_CVAL_EL2:
816  default:
817  return misc_reg;
818  }
819  /*should not be accessible */
820  return misc_reg;
821  }
822 
823  int
825  {
826  int reg_as_int = static_cast<int>(reg);
828  reg_as_int += (haveSecurity && !ns) ? 2 : 1;
829  }
830  return reg_as_int;
831  }
832 
833  std::pair<int,int> getMiscIndices(int misc_reg) const
834  {
835  // Note: indexes of AArch64 registers are left unchanged
836  int flat_idx = flattenMiscIndex(misc_reg);
837 
838  if (lookUpMiscReg[flat_idx].lower == 0) {
839  return std::make_pair(flat_idx, 0);
840  }
841 
842  // do additional S/NS flattenings if mapped to NS while in S
843  bool S = haveSecurity && !highestELIs64 &&
846  int lower = lookUpMiscReg[flat_idx].lower;
847  int upper = lookUpMiscReg[flat_idx].upper;
848  // upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op)
849  lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD];
850  upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD];
851  return std::make_pair(lower, upper);
852  }
853 
854  unsigned getCurSveVecLenInBits() const;
855 
856  unsigned getCurSveVecLenInBitsAtReset() const { return sveVL * 128; }
857 
858  template <typename Elem>
859  static void
860  zeroSveVecRegUpperPart(Elem *v, unsigned eCount)
861  {
862  static_assert(sizeof(Elem) <= sizeof(uint64_t),
863  "Elem type is too large.");
864  eCount *= (sizeof(uint64_t) / sizeof(Elem));
865  for (int i = 16 / sizeof(Elem); i < eCount; ++i) {
866  v[i] = 0;
867  }
868  }
869 
870  void serialize(CheckpointOut &cp) const override;
871  void unserialize(CheckpointIn &cp) override;
872 
873  void startup() override;
874 
875  void setupThreadContext();
876 
877  void takeOverFrom(ThreadContext *new_tc,
878  ThreadContext *old_tc) override;
879 
880  enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; }
881 
883  bool haveGICv3CpuIfc() const
884  {
885  // gicv3CpuInterface is initialized at startup time, hence
886  // trying to read its value before the startup stage will lead
887  // to an error
888  assert(afterStartup);
889  return gicv3CpuInterface != nullptr;
890  }
891 
892  enums::VecRegRenameMode
893  initVecRegRenameMode() const override
894  {
895  return highestELIs64 ? enums::Full : enums::Elem;
896  }
897 
898  enums::VecRegRenameMode
899  vecRegRenameMode(ThreadContext *_tc) const override
900  {
901  return _tc->pcState().aarch64() ? enums::Full : enums::Elem;
902  }
903 
904  PARAMS(ArmISA);
905 
906  ISA(const Params &p);
907 
908  uint64_t
909  getExecutingAsid() const override
910  {
912  }
913 
914  bool
915  inUserMode() const override
916  {
917  CPSR cpsr = miscRegs[MISCREG_CPSR];
918  return ArmISA::inUserMode(cpsr);
919  }
920 
921  void copyRegsFrom(ThreadContext *src) override;
922  };
923 
924 } // namespace ArmISA
925 } // namespace gem5
926 
927 #endif
gem5::ArmISA::MISCREG_USR_NS_RD
@ MISCREG_USR_NS_RD
Definition: misc.hh:1121
isa_device.hh
gem5::ArmISA::MISCREG_PRI_S_WR
@ MISCREG_PRI_S_WR
Definition: misc.hh:1129
gem5::ArmISA::MODE_EL2H
@ MODE_EL2H
Definition: types.hh:278
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:649
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:588
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HWrite
chain hypE2HWrite(bool v=true) const
Definition: isa.hh:281
gem5::ArmISA::ISA::PARAMS
PARAMS(ArmISA)
gem5::ArmISA::MISCREG_USR_NS_WR
@ MISCREG_USR_NS_WR
Definition: misc.hh:1122
gem5::ArmISA::MISCREG_PMCCFILTR
@ MISCREG_PMCCFILTR
Definition: misc.hh:361
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::ArmISA::ISA::dummyDevice
DummyISADevice dummyDevice
Dummy device for to handle non-existing ISA devices.
Definition: isa.hh:78
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: misc.hh:603
gem5::ArmISA::ISA::zeroSveVecRegUpperPart
static void zeroSveVecRegUpperPart(Elem *v, unsigned eCount)
Definition: isa.hh:860
gem5::ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition: misc.hh:728
gem5::ArmISA::ISA::MiscRegLUTEntry::lower
uint32_t lower
Definition: isa.hh:120
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monE2H
chain monE2H(bool v=true) const
Definition: isa.hh:339
gem5::ArmISA::ISA::getSelfDebug
static SelfDebug * getSelfDebug(ThreadContext *tc)
Definition: isa.hh:530
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:284
gem5::ArmISA::MISCREG_CNTHVS_TVAL_EL2
@ MISCREG_CNTHVS_TVAL_EL2
Definition: misc.hh:786
gem5::ArmISA::MISCREG_PRI_S_RD
@ MISCREG_PRI_S_RD
Definition: misc.hh:1128
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:62
warn
#define warn(...)
Definition: logging.hh:245
gem5::ArmISA::ISA::redirectRegVHE
int redirectRegVHE(ThreadContext *tc, int misc_reg)
Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at ...
Definition: isa.hh:756
gem5::ArmISA::ISA::selfDebug
SelfDebug * selfDebug
Definition: isa.hh:115
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::MISCREG_BANKED64
@ MISCREG_BANKED64
Definition: misc.hh:1112
gem5::ArmISA::ISA::MiscRegLUTEntry::_raz
uint64_t _raz
Definition: isa.hh:125
gem5::ArmISA::ISA::getCurSveVecLenInBits
unsigned getCurSveVecLenInBits() const
Definition: isa.cc:2358
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:282
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privNonSecureWrite
chain privNonSecureWrite(bool v=true) const
Definition: isa.hh:228
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:566
gem5::ArmISA::ISA::gicv3CpuInterface
std::unique_ptr< BaseISADevice > gicv3CpuInterface
Definition: isa.hh:87
gem5::ArmISA::MISCREG_PRRR_MAIR0_S
@ MISCREG_PRRR_MAIR0_S
Definition: misc.hh:86
gem5::ArmISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:535
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::warnNotFail
chain warnNotFail(bool v=true) const
Definition: isa.hh:181
gem5::ArmISA::ISA::clear
void clear()
Definition: isa.cc:133
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:399
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mutex
chain mutex(bool v=true) const
Definition: isa.hh:185
gem5::ArmISA::MISCREG_CNTHPS_TVAL_EL2
@ MISCREG_CNTHPS_TVAL_EL2
Definition: misc.hh:779
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:759
gem5::ArmISA::MISCREG_CNTHVS_CVAL_EL2
@ MISCREG_CNTHVS_CVAL_EL2
Definition: misc.hh:785
gem5::ArmISA::MISCREG_PRRR_MAIR0_NS
@ MISCREG_PRRR_MAIR0_NS
Definition: misc.hh:85
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:756
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::allPrivileges
chain allPrivileges(bool v=true) const
Definition: isa.hh:381
gem5::ArmISA::ISA::haveLargeAsid64
bool haveLargeAsid64
Definition: isa.hh:95
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::priv
chain priv(bool v=true) const
Definition: isa.hh:250
gem5::ArmISA::MODE_EL2T
@ MODE_EL2T
Definition: types.hh:277
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::ArmISA::ISA::takeOverFrom
void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override
Definition: isa.cc:485
gem5::ArmISA::ISA::initID32
void initID32(const ArmISAParams &p)
Definition: isa.cc:326
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::ArmISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:915
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::ArmISA::MODE_EL1H
@ MODE_EL1H
Definition: types.hh:276
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:283
gem5::ArmISA::MISCREG_MON_NS0_WR
@ MISCREG_MON_NS0_WR
Definition: misc.hh:1142
gem5::ArmISA::ISA::updateRegMap
void updateRegMap(CPSR cpsr)
Definition: isa.hh:464
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privNonSecureRead
chain privNonSecureRead(bool v=true) const
Definition: isa.hh:224
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::secure
chain secure(bool v=true) const
Definition: isa.hh:409
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypWrite
chain hypWrite(bool v=true) const
Definition: isa.hh:313
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmISA::ISA::timer
std::unique_ptr< BaseISADevice > timer
Definition: isa.hh:84
gem5::ArmISA::ISA::MiscRegLUTEntry::MiscRegLUTEntry
MiscRegLUTEntry()
Definition: isa.hh:128
gem5::ArmISA::MISCREG_HYP_E2H_NS_RD
@ MISCREG_HYP_E2H_NS_RD
Definition: misc.hh:1136
gem5::ArmISA::MISCREG_PRI_NS_WR
@ MISCREG_PRI_NS_WR
Definition: misc.hh:1127
gem5::ArmISA::ISA::MiscRegLUTEntry
MiscReg metadata.
Definition: isa.hh:118
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypSecureRead
chain hypSecureRead(bool v=true) const
Definition: isa.hh:291
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::info
std::bitset< NUM_MISCREG_INFOS > & info
Definition: isa.hh:146
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: misc.hh:599
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:740
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: misc.hh:260
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition: misc.hh:643
gem5::ArmISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:619
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:644
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HNonSecureWrite
chain hypE2HNonSecureWrite(bool v=true) const
Definition: isa.hh:277
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::ISA::MiscRegLUTEntry::upper
uint32_t upper
Definition: isa.hh:121
gem5::ArmISA::ISA::MiscRegLUTEntry::_rao
uint64_t _rao
Definition: isa.hh:126
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::res0
chain res0(uint64_t mask) const
Definition: isa.hh:154
gem5::ArmISA::ISA::vecRegRenameMode
enums::VecRegRenameMode vecRegRenameMode(ThreadContext *_tc) const override
Definition: isa.hh:899
gem5::ArmISA::ISA::initVecRegRenameMode
enums::VecRegRenameMode initVecRegRenameMode() const override
Definition: isa.hh:893
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypNonSecureRead
chain hypNonSecureRead(bool v=true) const
Definition: isa.hh:295
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privSecure
chain privSecure(bool v=true) const
Definition: isa.hh:245
gem5::ArmISA::ISA::MiscRegLUTEntry::_reset
uint64_t _reset
Definition: isa.hh:122
gem5::ArmISA::IntRegFiqMap
const IntRegMap IntRegFiqMap
Definition: int.hh:455
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:745
gem5::ArmISA::ISA::haveTME
bool haveTME
Definition: isa.hh:102
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition: misc_types.hh:331
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecureWrite
chain monNonSecureWrite(bool v=true) const
Definition: isa.hh:359
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::IntRegUsrMap
const IntRegMap IntRegUsrMap
Definition: int.hh:329
gem5::ArmISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:510
gem5::ArmISA::MISCREG_NMRR_MAIR1
@ MISCREG_NMRR_MAIR1
Definition: misc.hh:87
gem5::ArmISA::MISCREG_PRRR_MAIR0
@ MISCREG_PRRR_MAIR0
Definition: misc.hh:84
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:383
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: misc.hh:66
tlb.hh
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmISA::ISA::getCurSveVecLenInBitsAtReset
unsigned getCurSveVecLenInBitsAtReset() const
Definition: isa.hh:856
gem5::ArmISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:2402
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition: misc.hh:726
gem5::ArmISA::ISA::haveSecEL2
bool haveSecEL2
Definition: isa.hh:101
gem5::ArmISA::ISA::MiscRegLUTEntry::rao
uint64_t rao() const
Definition: isa.hh:135
gem5::ArmISA::ISA::sveVL
unsigned sveVL
SVE vector length in quadwords.
Definition: isa.hh:105
gem5::ArmISA::MISCREG_NMRR_MAIR1_NS
@ MISCREG_NMRR_MAIR1_NS
Definition: misc.hh:88
gem5::ArmISA::ISA::havePAN
bool havePAN
Definition: isa.hh:100
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::chain
const typedef MiscRegLUTEntryInitializer & chain
Definition: isa.hh:147
gem5::RegId::classValue
RegClass classValue() const
Class accessor.
Definition: reg_class.hh:180
system.hh
gem5::ArmISA::MISCREG_IMPLEMENTED
@ MISCREG_IMPLEMENTED
Definition: misc.hh:1101
gem5::ArmISA::ISA::haveLSE
bool haveLSE
Definition: isa.hh:98
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::ArmISA::MISCREG_USR_S_WR
@ MISCREG_USR_S_WR
Definition: misc.hh:1124
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::userSecureWrite
chain userSecureWrite(bool v=true) const
Definition: isa.hh:213
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HNonSecureRead
chain hypE2HNonSecureRead(bool v=true) const
Definition: isa.hh:264
gem5::ArmISA::MODE_EL3H
@ MODE_EL3H
Definition: types.hh:280
types.hh
gem5::RegId::index
RegIndex index() const
Index accessors.
Definition: reg_class.hh:154
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HSecureWrite
chain hypE2HSecureWrite(bool v=true) const
Definition: isa.hh:273
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2H
chain hypE2H(bool v=true) const
Definition: isa.hh:286
gem5::ArmISA::ISA::intRegMap
const IntRegIndex * intRegMap
Definition: isa.hh:461
gem5::ArmISA::ISA::addressTranslation
void addressTranslation(TLB::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2469
gem5::ArmISA::miscRegInfo
std::bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: misc.cc:3397
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypNonSecureWrite
chain hypNonSecureWrite(bool v=true) const
Definition: isa.hh:309
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privRead
chain privRead(bool v=true) const
Definition: isa.hh:255
gem5::ArmISA::IntReg64Map
const IntRegMap IntReg64Map
Definition: int.hh:318
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:768
gem5::ArmISA::ISA::MiscRegLUTEntry::_res1
uint64_t _res1
Definition: isa.hh:124
gem5::ArmISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:861
gem5::ArmISA::ISA::initID64
void initID64(const ArmISAParams &p)
Definition: isa.cc:364
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition: misc.hh:730
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2
@ MISCREG_CNTHP_TVAL_EL2
Definition: misc.hh:776
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:773
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::unverifiable
chain unverifiable(bool v=true) const
Definition: isa.hh:177
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypSecureWrite
chain hypSecureWrite(bool v=true) const
Definition: isa.hh:305
gem5::Flags< FlagsType >
gem5::ArmISA::MODE_EL3T
@ MODE_EL3T
Definition: types.hh:279
gem5::ArmISA::ISA::pmu
BaseISADevice * pmu
Definition: isa.hh:81
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:614
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::userNonSecureWrite
chain userNonSecureWrite(bool v=true) const
Definition: isa.hh:205
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privSecureRead
chain privSecureRead(bool v=true) const
Definition: isa.hh:237
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: misc.hh:369
gem5::ArmISA::MODE_EL1T
@ MODE_EL1T
Definition: types.hh:275
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::writes
chain writes(bool v) const
Definition: isa.hh:428
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::banked64
chain banked64(bool v=true) const
Definition: isa.hh:193
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::ArmISA::ISA::clear64
void clear64(const ArmISAParams &p)
Definition: isa.cc:277
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::banked
chain banked(bool v=true) const
Definition: isa.hh:189
sim_object.hh
gem5::ArmISA::width
Bitfield< 4 > width
Definition: misc_types.hh:71
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monSecureWrite
chain monSecureWrite(bool v=true) const
Definition: isa.hh:349
gem5::ArmISA::MISCREG_PMSELR
@ MISCREG_PMSELR
Definition: misc.hh:356
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: misc.hh:378
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::ISA::snsBankedIndex64
int snsBankedIndex64(MiscRegIndex reg, bool ns) const
Definition: isa.hh:824
gem5::ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition: misc.hh:731
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2
@ MISCREG_CNTHP_CVAL_EL2
Definition: misc.hh:775
gem5::ArmISA::IntRegSvcMap
const IntRegMap IntRegSvcMap
Definition: int.hh:365
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:584
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::ISA::getMiscIndices
std::pair< int, int > getMiscIndices(int misc_reg) const
Definition: isa.hh:833
gem5::ArmISA::ISA::MiscRegLUTEntry::res0
uint64_t res0() const
Definition: isa.hh:132
gem5::ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:1096
gem5::ArmISA::MISCREG_CNTHVS_CTL_EL2
@ MISCREG_CNTHVS_CTL_EL2
Definition: misc.hh:784
gem5::ArmISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:2409
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mapsTo
chain mapsTo(uint32_t l, uint32_t u=0) const
Definition: isa.hh:149
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::ArmISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:67
gem5::ArmISA::MISCREG_SPSR
@ MISCREG_SPSR
Definition: misc.hh:62
gem5::ArmISA::MISCREG_MON_NS1_WR
@ MISCREG_MON_NS1_WR
Definition: misc.hh:1145
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition: isa.hh:364
gem5::ArmISA::MISCREG_MUTEX
@ MISCREG_MUTEX
Definition: misc.hh:1107
gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: misc.hh:90
gem5::ArmISA::MISCREG_HYP_E2H_S_RD
@ MISCREG_HYP_E2H_S_RD
Definition: misc.hh:1138
gem5::ArmISA::ISA::haveLPAE
bool haveLPAE
Definition: isa.hh:92
gem5::ArmISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:612
gem5::ArmISA::MISCREG_MON_NS1_RD
@ MISCREG_MON_NS1_RD
Definition: misc.hh:1144
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:582
gem5::ArmISA::MISCREG_HYP_S_RD
@ MISCREG_HYP_S_RD
Definition: misc.hh:1133
gem5::MipsISA::l
Bitfield< 5 > l
Definition: pra_constants.hh:323
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:625
gem5::ArmISA::ISA::assert32
void assert32()
Definition: isa.hh:505
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:605
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monSecureRead
chain monSecureRead(bool v=true) const
Definition: isa.hh:344
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::nonSecure
chain nonSecure(bool v=true) const
Definition: isa.hh:398
gem5::ArmISA::ISA::getGICv3CPUInterface
BaseISADevice & getGICv3CPUInterface()
Definition: isa.cc:2351
gem5::ArmISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:559
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::ArmISA::MISCREG_BANKED
@ MISCREG_BANKED
Definition: misc.hh:1109
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::MISCREG_CNTHP_CTL_EL2
@ MISCREG_CNTHP_CTL_EL2
Definition: misc.hh:774
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecure
chain monNonSecure(bool v=true) const
Definition: isa.hh:376
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypSecure
chain hypSecure(bool v=true) const
Definition: isa.hh:319
gem5::ArmISA::ISA::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: isa.cc:447
std::pair< int, int >
gem5::ArmISA::ISA::haveSVE
bool haveSVE
Definition: isa.hh:97
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypRead
chain hypRead(bool v=true) const
Definition: isa.hh:299
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::bankedChild
chain bankedChild(bool v=true) const
Definition: isa.hh:197
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::implemented
chain implemented(bool v=true) const
Definition: isa.hh:170
gem5::ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition: misc.hh:760
gem5::ArmISA::ISA::getGenericTimer
BaseISADevice & getGenericTimer()
Definition: isa.cc:2330
gem5::ArmISA::IntRegUndMap
const IntRegMap IntRegUndMap
Definition: int.hh:419
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:612
gem5::ArmISA::MISCREG_PRI_NS_RD
@ MISCREG_PRI_NS_RD
Definition: misc.hh:1126
gem5::ArmISA::MISCREG_HYP_E2H_NS_WR
@ MISCREG_HYP_E2H_NS_WR
Definition: misc.hh:1137
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: misc.hh:375
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::unimplemented
chain unimplemented() const
Definition: isa.hh:174
gem5::ArmISA::ISA::decoderFlavor
enums::DecoderFlavor decoderFlavor() const
Definition: isa.hh:880
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: misc.hh:758
gem5::ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition: misc.hh:642
gem5::ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: misc.cc:3400
gem5::ArmISA::IntRegAbtMap
const IntRegMap IntRegAbtMap
Definition: int.hh:401
gem5::ArmISA::ISA::haveVirtualization
bool haveVirtualization
Definition: isa.hh:93
utility.hh
gem5::ArmISA::ISA::highestELIs64
bool highestELIs64
Definition: isa.hh:90
gem5::ArmISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:542
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: misc.hh:372
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::reads
chain reads(bool v) const
Definition: isa.hh:418
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::entry
struct MiscRegLUTEntry & entry
Definition: isa.hh:145
gem5::ArmISA::ISA::haveSecurity
bool haveSecurity
Definition: isa.hh:91
gem5::ArmISA::MISCREG_HYP_S_WR
@ MISCREG_HYP_S_WR
Definition: misc.hh:1134
gem5::ArmISA::ISA::MiscRegLUTEntry::raz
uint64_t raz() const
Definition: isa.hh:134
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ArmISA::MISCREG_MON_NS0_RD
@ MISCREG_MON_NS0_RD
Definition: misc.hh:1141
gem5::ArmISA::ISA::setupThreadContext
void setupThreadContext()
Definition: isa.cc:464
gem5::ArmISA::ISA::lookUpMiscReg
static std::vector< struct MiscRegLUTEntry > lookUpMiscReg
Metadata table accessible via the value of the register.
Definition: isa.hh:141
gem5::ArmISA::ISA::MiscRegLUTEntry::wi
uint64_t wi() const
Definition: isa.hh:137
gem5::ArmISA::MISCREG_UNVERIFIABLE
@ MISCREG_UNVERIFIABLE
Definition: misc.hh:1102
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: misc.hh:632
gem5::ArmISA::u
Bitfield< 22 > u
Definition: misc_types.hh:352
isa.hh
gem5::ArmISA::ISA::_decoderFlavor
const enums::DecoderFlavor _decoderFlavor
Definition: isa.hh:75
gem5::RegId::elemIndex
RegIndex elemIndex() const
Elem accessor.
Definition: reg_class.hh:178
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::ArmSystem
Definition: system.hh:62
gem5::ArmISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:598
gem5::ArmISA::ISA::haveVHE
bool haveVHE
Definition: isa.hh:99
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition: isa.cc:2536
gem5::ArmISA::MODE_EL0T
@ MODE_EL0T
Definition: types.hh:274
gem5::ArmISA::IntRegIrqMap
const IntRegMap IntRegIrqMap
Definition: int.hh:437
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monE2HRead
chain monE2HRead(bool v=true) const
Definition: isa.hh:331
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: misc.hh:65
gem5::ArmISA::ISA::InitReg
const MiscRegLUTEntryInitializer InitReg(uint32_t reg)
Definition: isa.hh:453
gem5::ArmISA::MISCREG_CNTP_CVAL_EL0
@ MISCREG_CNTP_CVAL_EL0
Definition: misc.hh:757
gem5::ArmISA::MISCREG_CNTHV_TVAL_EL2
@ MISCREG_CNTHV_TVAL_EL2
Definition: misc.hh:783
gem5::ArmISA::ISA::miscRegs
RegVal miscRegs[NUM_MISCREGS]
Definition: isa.hh:460
gem5::ArmISA::ISA::MiscRegLUTEntry::reset
uint64_t reset() const
Definition: isa.hh:131
misc.hh
gem5::ArmISA::DummyISADevice
Dummy device that prints a warning when it is accessed.
Definition: isa_device.hh:97
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::exceptUserMode
chain exceptUserMode() const
Definition: isa.hh:438
gem5::ArmISA::ISA::getSelfDebug
SelfDebug * getSelfDebug() const
Definition: isa.hh:524
gem5::ArmISA::ISA::system
ArmSystem * system
Definition: isa.hh:72
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:243
gem5::ArmISA::MISCREG_CNTHPS_CTL_EL2
@ MISCREG_CNTHPS_CTL_EL2
Definition: misc.hh:777
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:626
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:289
gem5::ArmISA::inUserMode
static bool inUserMode(CPSR cpsr)
Definition: utility.hh:96
gem5::ArmISA::flattenIntRegModeIndex
static int flattenIntRegModeIndex(int reg)
Definition: int.hh:483
gem5::ArmISA::inSecureState
static bool inSecureState(SCR scr, CPSR cpsr)
Definition: utility.hh:223
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::MiscRegLUTEntryInitializer
MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e, std::bitset< NUM_MISCREG_INFOS > &i)
Definition: isa.hh:443
gem5::ArmISA::TLB::ArmTranslationType
ArmTranslationType
Definition: tlb.hh:128
gem5::ArmISA::MISCREG_CNTHPS_CVAL_EL2
@ MISCREG_CNTHPS_CVAL_EL2
Definition: misc.hh:778
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:883
gem5::ArmISA::ISA::getExecutingAsid
uint64_t getExecutingAsid() const override
Definition: isa.hh:909
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HRead
chain hypE2HRead(bool v=true) const
Definition: isa.hh:268
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer
Definition: isa.hh:143
gem5::ArmISA::IntRegHypMap
const IntRegMap IntRegHypMap
Definition: int.hh:347
gem5::ArmISA::MISCREG_USR_S_RD
@ MISCREG_USR_S_RD
Definition: misc.hh:1123
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition: misc.hh:635
gem5::ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition: misc.hh:360
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monE2HWrite
chain monE2HWrite(bool v=true) const
Definition: isa.hh:335
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monSecure
chain monSecure(bool v=true) const
Definition: isa.hh:371
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:817
gem5::ArmISA::ISA::MiscRegLUTEntry::_res0
uint64_t _res0
Definition: isa.hh:123
gem5::ArmISA::MISCREG_HYP_E2H_S_WR
@ MISCREG_HYP_E2H_S_WR
Definition: misc.hh:1139
gem5::ArmISA::MISCREG_CNTHV_CVAL_EL2
@ MISCREG_CNTHV_CVAL_EL2
Definition: misc.hh:782
gem5::ArmISA::ISA::physAddrRange
uint8_t physAddrRange
Definition: isa.hh:96
self_debug.hh
gem5::BaseISA
Definition: isa.hh:54
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition: isa.hh:326
gem5::ArmISA::ISA::afterStartup
bool afterStartup
Definition: isa.hh:113
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::userNonSecureRead
chain userNonSecureRead(bool v=true) const
Definition: isa.hh:201
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:286
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5::ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition: misc.hh:637
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: misc.hh:597
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privSecureWrite
chain privSecureWrite(bool v=true) const
Definition: isa.hh:241
gem5::ArmISA::ISA::addressTranslation64
void addressTranslation64(TLB::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2418
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:651
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::user
chain user(bool v=true) const
Definition: isa.hh:217
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::raz
chain raz(uint64_t mask) const
Definition: isa.hh:162
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HSecureRead
chain hypE2HSecureRead(bool v=true) const
Definition: isa.hh:260
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::res1
chain res1(uint64_t mask) const
Definition: isa.hh:158
gem5::ArmISA::MISCREG_NMRR_MAIR1_S
@ MISCREG_NMRR_MAIR1_S
Definition: misc.hh:89
gem5::ArmISA::MISCREG_CNTHV_CTL_EL2
@ MISCREG_CNTHV_CTL_EL2
Definition: misc.hh:781
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:639
int.hh
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:736
gem5::ArmISA::IntRegMonMap
const IntRegMap IntRegMonMap
Definition: int.hh:383
gem5::ArmISA::MISCREG_MON_E2H_RD
@ MISCREG_MON_E2H_RD
Definition: misc.hh:1147
gem5::ArmISA::MISCREG_MON_E2H_WR
@ MISCREG_MON_E2H_WR
Definition: misc.hh:1148
gem5::ArmISA::ISA::MiscRegLUTEntry::res1
uint64_t res1() const
Definition: isa.hh:133
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: misc.hh:68
gem5::ArmISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:626
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecureRead
chain monNonSecureRead(bool v=true) const
Definition: isa.hh:354
gem5::ArmISA::MISCREG_BANKED_CHILD
@ MISCREG_BANKED_CHILD
Definition: misc.hh:1115
gem5::ArmISA::MISCREG_HYP_NS_RD
@ MISCREG_HYP_NS_RD
Definition: misc.hh:1131
gem5::ArmISA::ISA::clear32
void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
Definition: isa.cc:225
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::ISA::haveCrypto
bool haveCrypto
Definition: isa.hh:94
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: misc.hh:820
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::rao
chain rao(uint64_t mask) const
Definition: isa.hh:166
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privNonSecure
chain privNonSecure(bool v=true) const
Definition: isa.hh:232
gem5::ArmISA::ISA::haveGICv3CpuIfc
bool haveGICv3CpuIfc() const
Returns true if the ISA has a GICv3 cpu interface.
Definition: isa.hh:883
gem5::ArmISA::ISA::assert64
void assert64()
Definition: isa.hh:506
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:601
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::ArmISA::ISA::impdefAsNop
bool impdefAsNop
If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED ...
Definition: isa.hh:111
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:61
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::ArmISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:633
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: misc.hh:761
gem5::ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition: misc.hh:1104
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::userSecureRead
chain userSecureRead(bool v=true) const
Definition: isa.hh:209
gem5::ArmISA::MISCREG_HYP_NS_WR
@ MISCREG_HYP_NS_WR
Definition: misc.hh:1132

Generated on Tue Sep 21 2021 12:24:24 for gem5 by doxygen 1.8.17