gem5  v21.1.0.2
malta_cchip.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
33 #include "dev/mips/malta_cchip.hh"
34 
35 #include <deque>
36 #include <string>
37 #include <vector>
38 
39 #include "base/trace.hh"
40 #include "cpu/base.hh"
41 #include "cpu/thread_context.hh"
42 #include "debug/Malta.hh"
43 #include "dev/mips/malta.hh"
44 #include "dev/mips/maltareg.h"
45 #include "mem/packet.hh"
46 #include "mem/packet_access.hh"
47 #include "mem/port.hh"
48 #include "params/MaltaCChip.hh"
49 #include "sim/system.hh"
50 
51 namespace gem5
52 {
53 
55  : BasicPioDevice(p, 0xfffffff), malta(p.malta)
56 {
57  warn("MaltaCCHIP::MaltaCChip() not implemented.");
58 
59  //Put back pointer in malta
60  malta->cchip = this;
61 
62 }
63 
64 Tick
66 {
67  panic("MaltaCCHIP::read() not implemented.");
68  return pioDelay;
69 }
70 
71 Tick
73 {
74  panic("MaltaCCHIP::write() not implemented.");
75  return pioDelay;
76 }
77 
78 void
79 MaltaCChip::clearIPI(uint64_t ipintr)
80 {
81  panic("MaltaCCHIP::clear() not implemented.");
82 }
83 
84 void
85 MaltaCChip::clearITI(uint64_t itintr)
86 {
87  panic("MaltaCCHIP::clearITI() not implemented.");
88 }
89 
90 void
91 MaltaCChip::reqIPI(uint64_t ipreq)
92 {
93  panic("MaltaCCHIP::reqIPI() not implemented.");
94 }
95 
96 
97 void
99 {
100  panic("MaltaCCHIP::postRTC() not implemented.");
101 }
102 
103 void
104 MaltaCChip::postIntr(uint32_t interrupt)
105 {
106  uint64_t size = sys->threads.size();
107  assert(size <= Malta::Max_CPUs);
108 
109  for (int i=0; i < size; i++) {
110  //Note: Malta does not use index, but this was added to use the
111  //pre-existing implementation
112  auto tc = sys->threads[i];
113  tc->getCpuPtr()->postInterrupt(tc->threadId(), interrupt, 0);
114  DPRINTF(Malta, "posting interrupt to cpu %d, interrupt %d\n",
115  i, interrupt);
116  }
117 }
118 
119 void
120 MaltaCChip::clearIntr(uint32_t interrupt)
121 {
122  uint64_t size = sys->threads.size();
123  assert(size <= Malta::Max_CPUs);
124 
125  for (int i=0; i < size; i++) {
126  //Note: Malta does not use index, but this was added to use the
127  //pre-existing implementation
128  auto tc = sys->threads[i];
129  tc->getCpuPtr()->clearInterrupt(tc->threadId(), interrupt, 0);
130  DPRINTF(Malta, "clearing interrupt to cpu %d, interrupt %d\n",
131  i, interrupt);
132  }
133 }
134 
135 
136 void
138 {
139 }
140 
141 void
143 {
144 }
145 
146 } // namespace gem5
gem5::Malta
Top level class for Malta Chipset emulation.
Definition: malta.hh:54
warn
#define warn(...)
Definition: logging.hh:245
gem5::System::Threads::size
int size() const
Definition: system.hh:216
malta.hh
system.hh
gem5::Malta::cchip
MaltaCChip * cchip
Pointer to the Malta CChip.
Definition: malta.hh:67
gem5::MaltaCChip::postIntr
void postIntr(uint32_t interrupt)
post an interrupt to the CPU.
Definition: malta_cchip.cc:104
gem5::MaltaCChip::clearITI
void clearITI(uint64_t itintr)
clear a timer interrupt previously posted to the CPU.
Definition: malta_cchip.cc:85
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::MaltaCChip::clearIntr
void clearIntr(uint32_t interrupt)
clear an interrupt previously posted to the CPU.
Definition: malta_cchip.cc:120
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::MaltaCChip::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: malta_cchip.cc:72
gem5::MaltaCChip::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: malta_cchip.cc:137
malta_cchip.hh
packet.hh
maltareg.h
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::MaltaCChip::MaltaCChip
MaltaCChip(const Params &p)
Initialize the Malta CChip by setting all of the device register to 0.
Definition: malta_cchip.cc:54
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PioDevice::sys
System * sys
Definition: io_device.hh:105
gem5::MaltaCChip::reqIPI
void reqIPI(uint64_t ipreq)
request an interrupt be posted to the CPU.
Definition: malta_cchip.cc:91
port.hh
gem5::BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:157
gem5::Malta::Max_CPUs
static const int Max_CPUs
Max number of CPUs in a Malta.
Definition: malta.hh:58
gem5::MaltaCChip::malta
Malta * malta
pointer to the malta object.
Definition: malta_cchip.hh:55
gem5::MaltaCChip::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: malta_cchip.cc:65
packet_access.hh
base.hh
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::MaltaCChip::postRTC
void postRTC()
post an RTC interrupt to the CPU
Definition: malta_cchip.cc:98
trace.hh
gem5::MaltaCChip::clearIPI
void clearIPI(uint64_t ipintr)
post an ipi interrupt to the CPU.
Definition: malta_cchip.cc:79
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::MaltaCChip::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: malta_cchip.cc:142
thread_context.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

Generated on Tue Sep 21 2021 12:25:16 for gem5 by doxygen 1.8.17