gem5  v21.1.0.2
malta_io.hh
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28 
33 #ifndef __DEV_MALTA_IO_HH__
34 #define __DEV_MALTA_IO_HH__
35 
36 #include "dev/mips/malta.hh"
37 #include "dev/mips/malta_cchip.hh"
38 #include "dev/intel_8254_timer.hh"
39 #include "dev/io_device.hh"
40 #include "dev/mc146818.hh"
41 #include "params/MaltaIO.hh"
42 #include "sim/eventq.hh"
43 
44 namespace gem5
45 {
46 
51 class MaltaIO : public BasicPioDevice
52 {
53  protected:
54 
55  class RTC : public MC146818
56  {
57  public:
59  RTC(const std::string &name, const MaltaIOParams &p);
60 
61  protected:
62  void handleEvent()
63  {
64  //Actually interrupt the processor here
65  malta->cchip->postRTC();
66  }
67  };
68 
70  uint8_t mask1;
71 
73  uint8_t mask2;
74 
76  uint8_t mode1;
77 
79  uint8_t mode2;
80 
82  uint8_t picr; //Raw PIC interrput register
83 
86 
89 
92 
94 
99  uint16_t timerData;
100 
101  public:
106  Tick frequency() const;
107 
108  PARAMS(MaltaIO);
109 
114  MaltaIO(const Params &p);
115 
116  Tick read(PacketPtr pkt) override;
117  Tick write(PacketPtr pkt) override;
118 
119 
121  void postIntr(uint8_t interrupt);
122 
124  void clearIntr(uint8_t interrupt);
125 
126  void serialize(CheckpointOut &cp) const override;
127  void unserialize(CheckpointIn &cp) override;
128 
132  void startup() override;
133 
134 };
135 
136 } // namespace gem5
137 
138 #endif // __DEV_MALTA_IO_HH__
gem5::MaltaIO::pitimer
Intel8254Timer pitimer
Intel 8253 Periodic Interval Timer.
Definition: malta_io.hh:91
io_device.hh
gem5::Malta
Top level class for Malta Chipset emulation.
Definition: malta.hh:54
malta.hh
gem5::Malta::cchip
MaltaCChip * cchip
Pointer to the Malta CChip.
Definition: malta.hh:67
gem5::MaltaIO::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: malta_io.cc:89
gem5::Intel8254Timer
Programmable Interval Timer (Intel 8254)
Definition: intel_8254_timer.hh:46
gem5::MaltaIO::RTC::malta
Malta * malta
Definition: malta_io.hh:58
gem5::MaltaIO::startup
void startup() override
Start running.
Definition: malta_io.cc:142
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::MaltaIO::malta
Malta * malta
A pointer to the Malta device which be belong to.
Definition: malta_io.hh:88
gem5::MaltaIO::postIntr
void postIntr(uint8_t interrupt)
Post an Interrupt to the CPU.
Definition: malta_io.cc:96
gem5::MaltaIO::PARAMS
PARAMS(MaltaIO)
gem5::MaltaIO::mask2
uint8_t mask2
Mask of the PIC2.
Definition: malta_io.hh:73
malta_cchip.hh
gem5::MaltaIO::RTC::RTC
RTC(const std::string &name, const MaltaIOParams &p)
Definition: malta_io.cc:57
gem5::MaltaIO::picr
uint8_t picr
Raw PIC interrupt register before masking.
Definition: malta_io.hh:82
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::MaltaIO::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: malta_io.cc:126
gem5::MaltaIO::RTC::handleEvent
void handleEvent()
Definition: malta_io.hh:62
gem5::MC146818::name
const std::string & name() const
Definition: mc146818.hh:88
gem5::MaltaIO::mode1
uint8_t mode1
Mode of PIC1.
Definition: malta_io.hh:76
gem5::MaltaIO::mask1
uint8_t mask1
Mask of the PIC1.
Definition: malta_io.hh:70
gem5::MaltaIO::clearIntr
void clearIntr(uint8_t interrupt)
Clear an Interrupt to the CPU.
Definition: malta_io.cc:103
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::MaltaIO::frequency
Tick frequency() const
Return the freqency of the RTC.
Definition: malta_io.cc:76
gem5::MaltaIO::rtc
RTC rtc
Definition: malta_io.hh:93
gem5::MaltaIO::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: malta_io.cc:82
gem5::MaltaIO::MaltaIO
MaltaIO(const Params &p)
Initialize all the data for devices supported by Malta I/O.
Definition: malta_io.cc:63
gem5::MaltaIO::RTC
Definition: malta_io.hh:55
intel_8254_timer.hh
gem5::MaltaIO::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: malta_io.cc:110
gem5::MaltaIO::timerData
uint16_t timerData
The interval is set via two writes to the PIT.
Definition: malta_io.hh:99
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::MaltaCChip::postRTC
void postRTC()
post an RTC interrupt to the CPU
Definition: malta_cchip.cc:98
gem5::MaltaIO::picInterrupting
bool picInterrupting
Is the pic interrupting right now or not.
Definition: malta_io.hh:85
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::MaltaIO
Malta I/O device is a catch all for all the south bridge stuff we care to implement.
Definition: malta_io.hh:51
gem5::MC146818
Real-Time Clock (MC146818)
Definition: mc146818.hh:41
mc146818.hh
gem5::MaltaIO::mode2
uint8_t mode2
Mode of PIC2.
Definition: malta_io.hh:79
eventq.hh

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