gem5  v21.1.0.2
malta_io.cc
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28 
33 #include "dev/mips/malta_io.hh"
34 
35 #include <sys/time.h>
36 
37 #include <deque>
38 #include <string>
39 #include <vector>
40 
41 #include "base/time.hh"
42 #include "base/trace.hh"
43 #include "debug/Malta.hh"
44 #include "dev/mips/malta.hh"
45 #include "dev/mips/malta_cchip.hh"
46 #include "dev/mips/maltareg.h"
47 #include "dev/rtcreg.h"
48 #include "mem/packet.hh"
49 #include "mem/packet_access.hh"
50 #include "mem/port.hh"
51 #include "params/MaltaIO.hh"
52 #include "sim/system.hh"
53 
54 namespace gem5
55 {
56 
57 MaltaIO::RTC::RTC(const std::string &name, const MaltaIOParams &p)
58  : MC146818(p.malta, name, p.time, p.year_is_bcd, p.frequency),
59  malta(p.malta)
60 {
61 }
62 
64  : BasicPioDevice(p, 0x100), malta(p.malta),
65  pitimer(this, p.name + "pitimer"), rtc(p.name + ".rtc", p)
66 {
67  // set the back pointer from malta to myself
68  malta->io = this;
69 
70  timerData = 0;
71  picr = 0;
72  picInterrupting = false;
73 }
74 
75 Tick
77 {
78  return sim_clock::Frequency / params().frequency;
79 }
80 
81 Tick
83 {
84  panic("MaltaIO::read(...) not implemented inside malta_io.cc");
85  return pioDelay;
86 }
87 
88 Tick
90 {
91  panic("MaltaIO::write(...) not implemented inside malta_io.cc");
92  return pioDelay;
93 }
94 
95 void
96 MaltaIO::postIntr(uint8_t interrupt)
97 {
98  malta->cchip->postIntr(interrupt);
99  DPRINTF(Malta, "posting pic interrupt to cchip\n");
100 }
101 
102 void
103 MaltaIO::clearIntr(uint8_t interrupt)
104 {
105  malta->cchip->clearIntr(interrupt);
106  DPRINTF(Malta, "clear pic interrupt to cchip\n");
107 }
108 
109 void
111 {
119 
120  // Serialize the timers
121  pitimer.serialize("pitimer", cp);
122  rtc.serialize("rtc", cp);
123 }
124 
125 void
127 {
135 
136  // Unserialize the timers
137  pitimer.unserialize("pitimer", cp);
138  rtc.unserialize("rtc", cp);
139 }
140 
141 void
143 {
144  rtc.startup();
145  pitimer.startup();
146 }
147 
148 } // namespace gem5
gem5::MaltaIO::pitimer
Intel8254Timer pitimer
Intel 8253 Periodic Interval Timer.
Definition: malta_io.hh:91
gem5::Malta
Top level class for Malta Chipset emulation.
Definition: malta.hh:54
malta.hh
system.hh
gem5::Malta::cchip
MaltaCChip * cchip
Pointer to the Malta CChip.
Definition: malta.hh:67
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::MaltaIO::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: malta_io.cc:89
gem5::MaltaIO::startup
void startup() override
Start running.
Definition: malta_io.cc:142
gem5::MaltaCChip::postIntr
void postIntr(uint32_t interrupt)
post an interrupt to the CPU.
Definition: malta_cchip.cc:104
malta_io.hh
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::MaltaIO::malta
Malta * malta
A pointer to the Malta device which be belong to.
Definition: malta_io.hh:88
time.hh
gem5::MaltaCChip::clearIntr
void clearIntr(uint32_t interrupt)
clear an interrupt previously posted to the CPU.
Definition: malta_cchip.cc:120
gem5::Intel8254Timer::startup
void startup()
Start ticking.
Definition: intel_8254_timer.cc:92
gem5::sim_clock::Frequency
Tick Frequency
The simulated frequency of curTick(). (In ticks per second)
Definition: core.cc:48
gem5::MaltaIO::postIntr
void postIntr(uint8_t interrupt)
Post an Interrupt to the CPU.
Definition: malta_io.cc:96
gem5::MaltaIO::mask2
uint8_t mask2
Mask of the PIC2.
Definition: malta_io.hh:73
malta_cchip.hh
gem5::MaltaIO::RTC::RTC
RTC(const std::string &name, const MaltaIOParams &p)
Definition: malta_io.cc:57
packet.hh
maltareg.h
gem5::MaltaIO::picr
uint8_t picr
Raw PIC interrupt register before masking.
Definition: malta_io.hh:82
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::MaltaIO::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: malta_io.cc:126
gem5::MaltaIO::mode1
uint8_t mode1
Mode of PIC1.
Definition: malta_io.hh:76
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::MaltaIO::mask1
uint8_t mask1
Mask of the PIC1.
Definition: malta_io.hh:70
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MaltaIO::clearIntr
void clearIntr(uint8_t interrupt)
Clear an Interrupt to the CPU.
Definition: malta_io.cc:103
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MC146818::startup
virtual void startup()
Start ticking.
Definition: mc146818.cc:124
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
port.hh
gem5::Malta::io
MaltaIO * io
Pointer to the MaltaIO device which has the RTC.
Definition: malta.hh:61
gem5::MaltaIO::frequency
Tick frequency() const
Return the freqency of the RTC.
Definition: malta_io.cc:76
gem5::BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:157
gem5::MaltaIO::rtc
RTC rtc
Definition: malta_io.hh:93
gem5::MaltaIO::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: malta_io.cc:82
gem5::MaltaIO::MaltaIO
MaltaIO(const Params &p)
Initialize all the data for devices supported by Malta I/O.
Definition: malta_io.cc:63
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::Intel8254Timer::serialize
void serialize(const std::string &base, CheckpointOut &cp) const
Serialize this object to the given output stream.
Definition: intel_8254_timer.cc:74
packet_access.hh
gem5::MaltaIO::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: malta_io.cc:110
gem5::MC146818::serialize
void serialize(const std::string &base, CheckpointOut &cp) const
Serialize this object to the given output stream.
Definition: mc146818.cc:266
gem5::MaltaIO::timerData
uint16_t timerData
The interval is set via two writes to the PIT.
Definition: malta_io.hh:99
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
rtcreg.h
trace.hh
gem5::Intel8254Timer::unserialize
void unserialize(const std::string &base, CheckpointIn &cp)
Reconstruct the state of this object from a checkpoint.
Definition: intel_8254_timer.cc:83
gem5::MaltaIO::picInterrupting
bool picInterrupting
Is the pic interrupting right now or not.
Definition: malta_io.hh:85
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::MC146818::unserialize
void unserialize(const std::string &base, CheckpointIn &cp)
Reconstruct the state of this object from a checkpoint.
Definition: mc146818.cc:286
gem5::MC146818
Real-Time Clock (MC146818)
Definition: mc146818.hh:41
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::MaltaIO::mode2
uint8_t mode2
Mode of PIC2.
Definition: malta_io.hh:79

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