gem5 v24.0.0.0
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mem_delay.cc
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1/*
2 * Copyright (c) 2018, 2020 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "mem/mem_delay.hh"
39
40#include "params/MemDelay.hh"
41#include "params/SimpleMemDelay.hh"
42
43namespace gem5
44{
45
46MemDelay::MemDelay(const MemDelayParams &p)
48 requestPort(name() + "-mem_side_port", *this),
49 responsePort(name() + "-cpu_side_port", *this),
50 reqQueue(*this, requestPort),
51 respQueue(*this, responsePort),
52 snoopRespQueue(*this, requestPort)
53{
54}
55
56void
58{
60 fatal("Memory delay is not connected on both sides.\n");
61}
62
63
64Port &
65MemDelay::getPort(const std::string &if_name, PortID idx)
66{
67 if (if_name == "mem_side_port") {
68 return requestPort;
69 } else if (if_name == "cpu_side_port") {
70 return responsePort;
71 } else {
72 return ClockedObject::getPort(if_name, idx);
73 }
74}
75
76bool
82
83MemDelay::RequestPort::RequestPort(const std::string &_name, MemDelay &_parent)
84 : QueuedRequestPort(_name, _parent.reqQueue, _parent.snoopRespQueue),
85 parent(_parent)
86{
87}
88
89bool
91{
92 // technically the packet only reaches us after the header delay,
93 // and typically we also need to deserialise any payload
94 const Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
95 pkt->headerDelay = pkt->payloadDelay = 0;
96
97 const Tick when = curTick() + parent.delayResp(pkt) + receive_delay;
98
99 parent.responsePort.schedTimingResp(pkt, when);
100
101 return true;
102}
103
104void
106{
107 if (parent.trySatisfyFunctional(pkt)) {
108 pkt->makeResponse();
109 } else {
110 parent.responsePort.sendFunctionalSnoop(pkt);
111 }
112}
113
114Tick
116{
117 const Tick delay = parent.delaySnoopResp(pkt);
118
119 return delay + parent.responsePort.sendAtomicSnoop(pkt);
120}
121
122void
124{
125 parent.responsePort.sendTimingSnoopReq(pkt);
126}
127
128
130ResponsePort(const std::string &_name, MemDelay &_parent)
132 parent(_parent)
133{
134}
135
136Tick
138{
139 const Tick delay = parent.delayReq(pkt) + parent.delayResp(pkt);
140
141 return delay + parent.requestPort.sendAtomic(pkt);
142}
143
144bool
146{
147 // technically the packet only reaches us after the header
148 // delay, and typically we also need to deserialise any
149 // payload
150 Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
151 pkt->headerDelay = pkt->payloadDelay = 0;
152
153 const Tick when = curTick() + parent.delayReq(pkt) + receive_delay;
154
155 parent.requestPort.schedTimingReq(pkt, when);
156
157 return true;
158}
159
160void
162{
163 if (parent.trySatisfyFunctional(pkt)) {
164 pkt->makeResponse();
165 } else {
166 parent.requestPort.sendFunctional(pkt);
167 }
168}
169
170bool
172{
173 const Tick when = curTick() + parent.delaySnoopResp(pkt);
174
175 parent.requestPort.schedTimingSnoopResp(pkt, when);
176
177 return true;
178}
179
180
181
182SimpleMemDelay::SimpleMemDelay(const SimpleMemDelayParams &p)
183 : MemDelay(p),
184 readReqDelay(p.read_req),
185 readRespDelay(p.read_resp),
186 writeReqDelay(p.write_req),
187 writeRespDelay(p.write_resp)
188{
189}
190
191Tick
193{
194 if (pkt->isRead()) {
195 return readReqDelay;
196 } else if (pkt->isWrite()) {
197 return writeReqDelay;
198 } else {
199 return 0;
200 }
201}
202
203Tick
205{
206 if (pkt->isRead()) {
207 return readRespDelay;
208 } else if (pkt->isWrite()) {
209 return writeRespDelay;
210 } else {
211 return 0;
212 }
213}
214
215} // namespace gem5
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Tick recvAtomicSnoop(PacketPtr pkt) override
Receive an atomic snoop request packet from our peer.
Definition mem_delay.cc:115
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition mem_delay.cc:90
void recvTimingSnoopReq(PacketPtr pkt) override
Receive a timing snoop request from the peer.
Definition mem_delay.cc:123
void recvFunctionalSnoop(PacketPtr pkt) override
Receive a functional snoop request packet from the peer.
Definition mem_delay.cc:105
RequestPort(const std::string &_name, MemDelay &_parent)
Definition mem_delay.cc:83
bool recvTimingReq(PacketPtr pkt) override
Receive a timing request from the peer.
Definition mem_delay.cc:145
ResponsePort(const std::string &_name, MemDelay &_parent)
Definition mem_delay.cc:130
void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the peer.
Definition mem_delay.cc:161
bool recvTimingSnoopResp(PacketPtr pkt) override
Receive a timing snoop response from the peer.
Definition mem_delay.cc:171
Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the peer.
Definition mem_delay.cc:137
This abstract component provides a mechanism to delay packets.
Definition mem_delay.hh:66
bool trySatisfyFunctional(PacketPtr pkt)
Definition mem_delay.cc:77
RequestPort requestPort
Definition mem_delay.hh:128
MemDelay(const MemDelayParams &params)
Definition mem_delay.cc:46
RespPacketQueue respQueue
Definition mem_delay.hh:132
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition mem_delay.cc:65
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition mem_delay.cc:57
ResponsePort responsePort
Definition mem_delay.hh:129
const std::string _name
Definition named.hh:41
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
bool isRead() const
Definition packet.hh:593
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition packet.hh:449
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition packet.hh:1062
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition packet.hh:431
bool isWrite() const
Definition packet.hh:594
Ports are used to interface objects to each other.
Definition port.hh:62
bool isConnected() const
Is this port currently connected to a peer?
Definition port.hh:133
The QueuedRequestPort combines two queues, a request queue and a snoop response queue,...
Definition qport.hh:111
bool trySatisfyFunctional(PacketPtr pkt)
Check the list of buffered packets against the supplied functional request.
Definition qport.hh:164
A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module...
Definition qport.hh:62
bool trySatisfyFunctional(PacketPtr pkt)
Check the list of buffered packets against the supplied functional request.
Definition qport.hh:99
const Tick writeReqDelay
Definition mem_delay.hh:179
const Tick readRespDelay
Definition mem_delay.hh:177
const Tick writeRespDelay
Definition mem_delay.hh:180
const Tick readReqDelay
Definition mem_delay.hh:176
Tick delayReq(PacketPtr pkt) override
Delay a request by some number of ticks.
Definition mem_delay.cc:192
SimpleMemDelay(const SimpleMemDelayParams &params)
Definition mem_delay.cc:182
Tick delayResp(PacketPtr pkt) override
Delay a response by some number of ticks.
Definition mem_delay.cc:204
#define fatal(...)
This implements a cprintf based fatal() function.
Definition logging.hh:200
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
uint64_t Tick
Tick count type.
Definition types.hh:58
const std::string & name()
Definition trace.cc:48

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