gem5  v21.1.0.2
mem_delay.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2018, 2020 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #include "mem/mem_delay.hh"
39 
40 #include "params/MemDelay.hh"
41 #include "params/SimpleMemDelay.hh"
42 
43 namespace gem5
44 {
45 
46 MemDelay::MemDelay(const MemDelayParams &p)
47  : ClockedObject(p),
48  requestPort(name() + "-mem_side_port", *this),
49  responsePort(name() + "-cpu_side_port", *this),
50  reqQueue(*this, requestPort),
51  respQueue(*this, responsePort),
52  snoopRespQueue(*this, requestPort)
53 {
54 }
55 
56 void
58 {
60  fatal("Memory delay is not connected on both sides.\n");
61 }
62 
63 
64 Port &
65 MemDelay::getPort(const std::string &if_name, PortID idx)
66 {
67  if (if_name == "mem_side_port") {
68  return requestPort;
69  } else if (if_name == "cpu_side_port") {
70  return responsePort;
71  } else {
72  return ClockedObject::getPort(if_name, idx);
73  }
74 }
75 
76 bool
78 {
79  return responsePort.trySatisfyFunctional(pkt) ||
81 }
82 
83 MemDelay::RequestPort::RequestPort(const std::string &_name, MemDelay &_parent)
84  : QueuedRequestPort(_name, &_parent,
85  _parent.reqQueue, _parent.snoopRespQueue),
86  parent(_parent)
87 {
88 }
89 
90 bool
92 {
93  // technically the packet only reaches us after the header delay,
94  // and typically we also need to deserialise any payload
95  const Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
96  pkt->headerDelay = pkt->payloadDelay = 0;
97 
98  const Tick when = curTick() + parent.delayResp(pkt) + receive_delay;
99 
100  parent.responsePort.schedTimingResp(pkt, when);
101 
102  return true;
103 }
104 
105 void
107 {
108  if (parent.trySatisfyFunctional(pkt)) {
109  pkt->makeResponse();
110  } else {
111  parent.responsePort.sendFunctionalSnoop(pkt);
112  }
113 }
114 
115 Tick
117 {
118  const Tick delay = parent.delaySnoopResp(pkt);
119 
120  return delay + parent.responsePort.sendAtomicSnoop(pkt);
121 }
122 
123 void
125 {
126  parent.responsePort.sendTimingSnoopReq(pkt);
127 }
128 
129 
131 ResponsePort(const std::string &_name, MemDelay &_parent)
132  : QueuedResponsePort(_name, &_parent, _parent.respQueue),
133  parent(_parent)
134 {
135 }
136 
137 Tick
139 {
140  const Tick delay = parent.delayReq(pkt) + parent.delayResp(pkt);
141 
142  return delay + parent.requestPort.sendAtomic(pkt);
143 }
144 
145 bool
147 {
148  // technically the packet only reaches us after the header
149  // delay, and typically we also need to deserialise any
150  // payload
151  Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
152  pkt->headerDelay = pkt->payloadDelay = 0;
153 
154  const Tick when = curTick() + parent.delayReq(pkt) + receive_delay;
155 
156  parent.requestPort.schedTimingReq(pkt, when);
157 
158  return true;
159 }
160 
161 void
163 {
164  if (parent.trySatisfyFunctional(pkt)) {
165  pkt->makeResponse();
166  } else {
167  parent.requestPort.sendFunctional(pkt);
168  }
169 }
170 
171 bool
173 {
174  const Tick when = curTick() + parent.delaySnoopResp(pkt);
175 
176  parent.requestPort.schedTimingSnoopResp(pkt, when);
177 
178  return true;
179 }
180 
181 
182 
183 SimpleMemDelay::SimpleMemDelay(const SimpleMemDelayParams &p)
184  : MemDelay(p),
185  readReqDelay(p.read_req),
186  readRespDelay(p.read_resp),
187  writeReqDelay(p.write_req),
188  writeRespDelay(p.write_resp)
189 {
190 }
191 
192 Tick
194 {
195  if (pkt->isRead()) {
196  return readReqDelay;
197  } else if (pkt->isWrite()) {
198  return writeReqDelay;
199  } else {
200  return 0;
201  }
202 }
203 
204 Tick
206 {
207  if (pkt->isRead()) {
208  return readRespDelay;
209  } else if (pkt->isWrite()) {
210  return writeRespDelay;
211  } else {
212  return 0;
213  }
214 }
215 
216 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::MemDelay::ResponsePort::recvTimingSnoopResp
bool recvTimingSnoopResp(PacketPtr pkt) override
Receive a timing snoop response from the peer.
Definition: mem_delay.cc:172
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::MemDelay::RequestPort::recvFunctionalSnoop
void recvFunctionalSnoop(PacketPtr pkt) override
Receive a functional snoop request packet from the peer.
Definition: mem_delay.cc:106
gem5::MemDelay::requestPort
RequestPort requestPort
Definition: mem_delay.hh:128
gem5::QueuedRequestPort
The QueuedRequestPort combines two queues, a request queue and a snoop response queue,...
Definition: qport.hh:109
gem5::MemDelay::responsePort
ResponsePort responsePort
Definition: mem_delay.hh:129
gem5::SimpleMemDelay::readRespDelay
const Tick readRespDelay
Definition: mem_delay.hh:177
gem5::MemDelay::ResponsePort::ResponsePort
ResponsePort(const std::string &_name, MemDelay &_parent)
Definition: mem_delay.cc:131
mem_delay.hh
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::MemDelay::respQueue
RespPacketQueue respQueue
Definition: mem_delay.hh:132
gem5::SimpleMemDelay::readReqDelay
const Tick readReqDelay
Definition: mem_delay.hh:176
gem5::Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:420
gem5::MemDelay
This abstract component provides a mechanism to delay packets.
Definition: mem_delay.hh:65
gem5::MemDelay::RequestPort::recvAtomicSnoop
Tick recvAtomicSnoop(PacketPtr pkt) override
Receive an atomic snoop request packet from our peer.
Definition: mem_delay.cc:116
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::MemDelay::RequestPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: mem_delay.cc:91
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:582
gem5::QueuedResponsePort
A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module...
Definition: qport.hh:61
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::SimpleMemDelay::SimpleMemDelay
SimpleMemDelay(const SimpleMemDelayParams &params)
Definition: mem_delay.cc:183
gem5::Port::isConnected
bool isConnected() const
Is this port currently connected to a peer?
Definition: port.hh:133
gem5::SimpleMemDelay::writeReqDelay
const Tick writeReqDelay
Definition: mem_delay.hh:179
name
const std::string & name()
Definition: trace.cc:49
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::MemDelay::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr pkt)
Definition: mem_delay.cc:77
gem5::MemDelay::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: mem_delay.cc:65
gem5::SimpleMemDelay::writeRespDelay
const Tick writeRespDelay
Definition: mem_delay.hh:180
gem5::SimpleMemDelay::delayResp
Tick delayResp(PacketPtr pkt) override
Delay a response by some number of ticks.
Definition: mem_delay.cc:205
gem5::MemDelay::ResponsePort::recvTimingReq
bool recvTimingReq(PacketPtr pkt) override
Receive a timing request from the peer.
Definition: mem_delay.cc:146
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::MemDelay::ResponsePort::recvFunctional
void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the peer.
Definition: mem_delay.cc:162
gem5::Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1031
gem5::QueuedResponsePort::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr pkt)
Check the list of buffered packets against the supplied functional request.
Definition: qport.hh:98
gem5::QueuedRequestPort::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr pkt)
Check the list of buffered packets against the supplied functional request.
Definition: qport.hh:163
gem5::SimpleMemDelay::delayReq
Tick delayReq(PacketPtr pkt) override
Delay a request by some number of ticks.
Definition: mem_delay.cc:193
gem5::MemDelay::RequestPort::RequestPort
RequestPort(const std::string &_name, MemDelay &_parent)
Definition: mem_delay.cc:83
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::MemDelay::RequestPort::recvTimingSnoopReq
void recvTimingSnoopReq(PacketPtr pkt) override
Receive a timing snoop request from the peer.
Definition: mem_delay.cc:124
gem5::MemDelay::MemDelay
MemDelay(const MemDelayParams &params)
Definition: mem_delay.cc:46
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::MemDelay::ResponsePort::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the peer.
Definition: mem_delay.cc:138
gem5::MemDelay::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: mem_delay.cc:57

Generated on Tue Sep 21 2021 12:25:32 for gem5 by doxygen 1.8.17