gem5  v22.1.0.0
microspecop.hh
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27 
28 #ifndef __ARCH_X86_INSTS_MICROSPECOP_HH__
29 #define __ARCH_X86_INSTS_MICROSPECOP_HH__
30 
32 #include "cpu/exec_context.hh"
33 
34 namespace gem5
35 {
36 
37 namespace X86ISA
38 {
39 
40 class MicroHalt : public InstOperands<X86MicroopBase>
41 {
42  public:
43  MicroHalt(ExtMachInst mach_inst, const char *inst_mnem,
44  uint64_t set_flags) :
45  InstOperands<X86MicroopBase>(mach_inst, "halt", inst_mnem,
46  set_flags | (1ULL << StaticInst::IsNonSpeculative) |
47  (1ULL << StaticInst::IsQuiesce),
48  No_OpClass, {})
49  {}
50 
51  Fault
52  execute(ExecContext *xc, trace::InstRecord *) const override
53  {
54  xc->tcBase()->suspend();
55  return NoFault;
56  }
57 };
58 
59 } // namespace X86ISA
60 } // namespace gem5
61 
62 #endif //__ARCH_X86_INSTS_MICROSPECOP_HH__
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:72
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
Base, ISA-independent static instruction class.
Definition: static_inst.hh:89
virtual void suspend()=0
Set the status to Suspended.
MicroHalt(ExtMachInst mach_inst, const char *inst_mnem, uint64_t set_flags)
Definition: microspecop.hh:43
Fault execute(ExecContext *xc, trace::InstRecord *) const override
Definition: microspecop.hh:52
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
constexpr decltype(nullptr) NoFault
Definition: types.hh:253

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