gem5 v24.0.0.0
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microspecop.hh
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1/*
2 * Copyright 2021 Google Inc.
3 *
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5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
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26 */
27
28#ifndef __ARCH_X86_INSTS_MICROSPECOP_HH__
29#define __ARCH_X86_INSTS_MICROSPECOP_HH__
30
32#include "cpu/exec_context.hh"
33
34namespace gem5
35{
36
37namespace X86ISA
38{
39
40class MicroHalt : public InstOperands<X86MicroopBase>
41{
42 public:
43 MicroHalt(ExtMachInst mach_inst, const char *inst_mnem,
44 uint64_t set_flags) :
45 InstOperands<X86MicroopBase>(mach_inst, "halt", inst_mnem,
46 set_flags | (1ULL << StaticInst::IsNonSpeculative) |
47 (1ULL << StaticInst::IsQuiesce),
48 No_OpClass, {})
49 {}
50
51 Fault
52 execute(ExecContext *xc, trace::InstRecord *) const override
53 {
54 xc->tcBase()->suspend();
55 return NoFault;
56 }
57};
58
59} // namespace X86ISA
60} // namespace gem5
61
62#endif //__ARCH_X86_INSTS_MICROSPECOP_HH__
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
Base, ISA-independent static instruction class.
virtual void suspend()=0
Set the status to Suspended.
MicroHalt(ExtMachInst mach_inst, const char *inst_mnem, uint64_t set_flags)
Fault execute(ExecContext *xc, trace::InstRecord *) const override
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
constexpr decltype(nullptr) NoFault
Definition types.hh:253

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