gem5
v24.0.0.0
Loading...
Searching...
No Matches
arch
x86
insts
microspecop.hh
Go to the documentation of this file.
1
/*
2
* Copyright 2021 Google Inc.
3
*
4
* Redistribution and use in source and binary forms, with or without
5
* modification, are permitted provided that the following conditions are
6
* met: redistributions of source code must retain the above copyright
7
* notice, this list of conditions and the following disclaimer;
8
* redistributions in binary form must reproduce the above copyright
9
* notice, this list of conditions and the following disclaimer in the
10
* documentation and/or other materials provided with the distribution;
11
* neither the name of the copyright holders nor the names of its
12
* contributors may be used to endorse or promote products derived from
13
* this software without specific prior written permission.
14
*
15
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
*/
27
28
#ifndef __ARCH_X86_INSTS_MICROSPECOP_HH__
29
#define __ARCH_X86_INSTS_MICROSPECOP_HH__
30
31
#include "
arch/x86/insts/microop.hh
"
32
#include "
cpu/exec_context.hh
"
33
34
namespace
gem5
35
{
36
37
namespace
X86ISA
38
{
39
40
class
MicroHalt
:
public
InstOperands
<X86MicroopBase>
41
{
42
public
:
43
MicroHalt
(
ExtMachInst
mach_inst,
const
char
*inst_mnem,
44
uint64_t set_flags) :
45
InstOperands
<
X86MicroopBase
>(mach_inst,
"halt"
, inst_mnem,
46
set_flags | (1ULL <<
StaticInst
::IsNonSpeculative) |
47
(1ULL <<
StaticInst
::IsQuiesce),
48
No_OpClass, {})
49
{}
50
51
Fault
52
execute
(
ExecContext
*xc,
trace::InstRecord
*)
const override
53
{
54
xc->
tcBase
()->
suspend
();
55
return
NoFault
;
56
}
57
};
58
59
}
// namespace X86ISA
60
}
// namespace gem5
61
62
#endif
//__ARCH_X86_INSTS_MICROSPECOP_HH__
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition
exec_context.hh:72
gem5::ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition
static_inst.hh:89
gem5::ThreadContext::suspend
virtual void suspend()=0
Set the status to Suspended.
gem5::X86ISA::InstOperands
Definition
microop_args.hh:396
gem5::X86ISA::MicroHalt
Definition
microspecop.hh:41
gem5::X86ISA::MicroHalt::MicroHalt
MicroHalt(ExtMachInst mach_inst, const char *inst_mnem, uint64_t set_flags)
Definition
microspecop.hh:43
gem5::X86ISA::MicroHalt::execute
Fault execute(ExecContext *xc, trace::InstRecord *) const override
Definition
microspecop.hh:52
gem5::X86ISA::X86MicroopBase
Definition
microop.hh:98
gem5::trace::InstRecord
Definition
insttracer.hh:62
exec_context.hh
microop.hh
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition
types.hh:249
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition
types.hh:253
gem5::X86ISA::ExtMachInst
Definition
types.hh:213
Generated on Tue Jun 18 2024 16:24:00 for gem5 by
doxygen
1.11.0