gem5  v21.1.0.2
rtc.hh
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37 
38 #ifndef __DEV_RISCV_RTC_HH__
39 #define __DEV_RISCV_RTC_HH__
40 
41 #include "dev/intpin.hh"
42 #include "dev/mc146818.hh"
43 #include "params/RiscvRTC.hh"
44 #include "sim/sim_object.hh"
45 
46 namespace gem5
47 {
48 
54 class RiscvRTC : public SimObject
55 {
56  public:
57 
58  class RTC: public MC146818
59  {
60  public:
62 
64 
65  RTC(EventManager *em, const std::string &n, const struct tm time,
66  bool bcd, Tick frequency, int int_pin_count);
67 
68  protected:
69  void handleEvent();
70  } rtc;
71 
72  typedef RiscvRTCParams Params;
73 
74  RiscvRTC(const Params &params);
75 
76  Port & getPort(const std::string &if_name,
77  PortID idx=InvalidPortID) override;
78 
79  void startup() override;
80 
81  void serialize(CheckpointOut &cp) const override;
82  void unserialize(CheckpointIn &cp) override;
83 };
84 
85 } // namespace gem5
86 
87 #endif //__DEV_RISCV_RTC_HH__
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::RiscvRTC::Params
RiscvRTCParams Params
Definition: rtc.hh:72
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::RiscvRTC::RTC::intPin
std::vector< std::unique_ptr< IntSource > > intPin
Definition: rtc.hh:63
gem5::RiscvRTC::RTC::RTC
RTC(EventManager *em, const std::string &n, const struct tm time, bool bcd, Tick frequency, int int_pin_count)
Definition: rtc.cc:53
std::vector
STL vector class.
Definition: stl.hh:37
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::RiscvRTC::RiscvRTC
RiscvRTC(const Params &params)
Definition: rtc.cc:46
gem5::RiscvRTC::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: rtc.cc:88
gem5::RiscvRTC::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: rtc.cc:95
gem5::X86ISA::em
Bitfield< 2 > em
Definition: misc.hh:608
gem5::EventManager
Definition: eventq.hh:987
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
sim_object.hh
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::RiscvRTC::RTC::handleEvent
void handleEvent()
Definition: rtc.cc:64
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::PowerISA::tm
Bitfield< 32 > tm
Definition: misc.hh:107
gem5::RiscvRTC::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: rtc.cc:82
gem5::RiscvRTC
NOTE: This is a generic wrapper around the MC146818 RTC.
Definition: rtc.hh:54
gem5::RiscvRTC::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: rtc.cc:73
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ArmISA::n
Bitfield< 31 > n
Definition: misc_types.hh:455
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::RiscvRTC::rtc
gem5::RiscvRTC::RTC rtc
gem5::RiscvRTC::RTC
Definition: rtc.hh:58
gem5::IntSourcePin
Definition: intpin.hh:112
intpin.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::MC146818
Real-Time Clock (MC146818)
Definition: mc146818.hh:41
mc146818.hh

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