tarmac_parser.hh

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/*
 * Copyright (c) 2011,2017-2019 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
#define __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
 
#include <fstream>
#include <memory>
#include <unordered_map>
 
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "mem/request.hh"
#include "params/TarmacParser.hh"
#include "sim/insttracer.hh"
#include "tarmac_base.hh"
 
namespace gem5
{
 
namespace trace {
 
class TarmacParserRecord : public TarmacBaseRecord
{
  public:
    struct TarmacParserRecordEvent: public Event
    {
        TarmacParser& parent;
        ThreadContext* thread;
        const StaticInstPtr inst;
        std::unique_ptr<PCStateBase> pc;
        bool mismatch;
        bool mismatchOnPcOrOpcode;
 
        TarmacParserRecordEvent(TarmacParser& _parent,
                                ThreadContext *_thread,
                                const StaticInstPtr _inst,
                                const PCStateBase &_pc,
                                bool _mismatch,
                                bool _mismatch_on_pc_or_opcode) :
            parent(_parent), thread(_thread), inst(_inst), pc(_pc.clone()),
            mismatch(_mismatch),
            mismatchOnPcOrOpcode(_mismatch_on_pc_or_opcode)
        {
        }
 
        void process();
        const char *description() const;
    };
 
    struct ParserInstEntry : public InstEntry
    {
      public:
        uint64_t seq_num;
    };
 
    struct ParserRegEntry : public RegEntry
    {
      public:
        char repr[16];
    };
 
    struct ParserMemEntry : public MemEntry
    { };
 
    static const int MaxLineLength = 256;
 
    static void printMismatchHeader(const StaticInstPtr inst,
                                    const PCStateBase &pc);
 
    TarmacParserRecord(Tick _when, ThreadContext *_thread,
                       const StaticInstPtr _staticInst,
                       const PCStateBase &_pc,
                       TarmacParser& _parent,
                       const StaticInstPtr _macroStaticInst = NULL);
 
    void dump() override;
 
    bool readMemNoEffect(Addr addr, uint8_t *data, unsigned size,
                         unsigned flags);
 
  private:
    bool advanceTrace();
 
    const char *iSetStateToStr(ISetState isetstate) const;
 
    static ParserInstEntry instRecord;
 
    static ParserRegEntry regRecord;
 
    static ParserMemEntry memRecord;
 
    static TarmacRecordType currRecordType;
 
    static char buf[MaxLineLength];
 
    static std::list<ParserRegEntry> destRegRecords;
 
    using MiscRegMap = std::unordered_map<std::string, RegIndex>;
    static MiscRegMap miscRegMap;
 
    bool parsingStarted;
 
    bool mismatch;
 
    bool mismatchOnPcOrOpcode;
 
    RequestPtr memReq;
 
    static int8_t maxVectorLength;
 
  protected:
    TarmacParser& parent;
};
 
class TarmacParser : public InstTracer
{
    friend class TarmacParserRecord;
 
  public:
    typedef TarmacParserParams Params;
 
    TarmacParser(const Params &p) : InstTracer(p), startPc(p.start_pc),
                                    exitOnDiff(p.exit_on_diff),
                                    exitOnInsnDiff(p.exit_on_insn_diff),
                                    memWrCheck(p.mem_wr_check),
                                    ignoredAddrRange(p.ignore_mem_addr),
                                    cpuId(p.cpu_id),
                                    macroopInProgress(false)
    {
        assert(!(exitOnDiff && exitOnInsnDiff));
 
        trace.open(p.path_to_trace.c_str());
        if (startPc == 0x0) {
            started = true;
        } else {
            advanceTraceToStartPc();
            started = false;
        }
    }
 
    virtual ~TarmacParser()
    {
        trace.close();
    }
 
    InstRecord *
    getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst,
                  const PCStateBase &pc,
                  const StaticInstPtr macroStaticInst=nullptr) override
    {
        if (!started && pc.instAddr() == startPc)
            started = true;
 
        if (started) {
            return new TarmacParserRecord(when, tc, staticInst, pc, *this,
                                          macroStaticInst);
        } else {
            return nullptr;
        }
    }
 
  private:
    void advanceTraceToStartPc();
 
    std::ifstream trace;
 
    Addr startPc;
 
    bool exitOnDiff;
 
    bool exitOnInsnDiff;
 
    bool memWrCheck;
 
    AddrRange ignoredAddrRange;
 
    bool cpuId;
 
    bool started;
 
    bool macroopInProgress;
};
 
} // namespace trace
} // namespace gem5
 
#endif // __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__