gem5  v22.1.0.0
tarmac_parser.hh
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37 
46 #ifndef __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
47 #define __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
48 
49 #include <fstream>
50 #include <memory>
51 #include <unordered_map>
52 
53 #include "base/trace.hh"
54 #include "base/types.hh"
55 #include "cpu/static_inst.hh"
56 #include "cpu/thread_context.hh"
57 #include "mem/request.hh"
58 #include "params/TarmacParser.hh"
59 #include "sim/insttracer.hh"
60 #include "tarmac_base.hh"
61 
62 namespace gem5
63 {
64 
65 namespace trace {
66 
68 {
69  public:
77  {
87  std::unique_ptr<PCStateBase> pc;
89  bool mismatch;
95 
97  ThreadContext *_thread,
98  const StaticInstPtr _inst,
99  const PCStateBase &_pc,
100  bool _mismatch,
101  bool _mismatch_on_pc_or_opcode) :
102  parent(_parent), thread(_thread), inst(_inst), pc(_pc.clone()),
103  mismatch(_mismatch),
104  mismatchOnPcOrOpcode(_mismatch_on_pc_or_opcode)
105  {
106  }
107 
108  void process();
109  const char *description() const;
110  };
111 
112  struct ParserInstEntry : public InstEntry
113  {
114  public:
115  uint64_t seq_num;
116  };
117 
118  struct ParserRegEntry : public RegEntry
119  {
120  public:
121  char repr[16];
122  };
123 
124  struct ParserMemEntry : public MemEntry
125  { };
126 
127  static const int MaxLineLength = 256;
128 
133  static void printMismatchHeader(const StaticInstPtr inst,
134  const PCStateBase &pc);
135 
136  TarmacParserRecord(Tick _when, ThreadContext *_thread,
137  const StaticInstPtr _staticInst,
138  const PCStateBase &_pc,
139  TarmacParser& _parent,
140  const StaticInstPtr _macroStaticInst = NULL);
141 
142  void dump() override;
143 
149  bool readMemNoEffect(Addr addr, uint8_t *data, unsigned size,
150  unsigned flags);
151 
152  private:
159  bool advanceTrace();
160 
162  const char *iSetStateToStr(ISetState isetstate) const;
163 
166 
169 
172 
175 
177  static char buf[MaxLineLength];
178 
181 
183  using MiscRegMap = std::unordered_map<std::string, RegIndex>;
185 
191 
193  bool mismatch;
194 
200 
203 
205  static int8_t maxVectorLength;
206 
207  protected:
209 };
210 
216 class TarmacParser : public InstTracer
217 {
218  friend class TarmacParserRecord;
219 
220  public:
221  typedef TarmacParserParams Params;
222 
223  TarmacParser(const Params &p) : InstTracer(p), startPc(p.start_pc),
224  exitOnDiff(p.exit_on_diff),
225  exitOnInsnDiff(p.exit_on_insn_diff),
226  memWrCheck(p.mem_wr_check),
227  ignoredAddrRange(p.ignore_mem_addr),
228  cpuId(p.cpu_id),
229  macroopInProgress(false)
230  {
231  assert(!(exitOnDiff && exitOnInsnDiff));
232 
233  trace.open(p.path_to_trace.c_str());
234  if (startPc == 0x0) {
235  started = true;
236  } else {
238  started = false;
239  }
240  }
241 
242  virtual ~TarmacParser()
243  {
244  trace.close();
245  }
246 
247  InstRecord *
248  getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst,
249  const PCStateBase &pc,
250  const StaticInstPtr macroStaticInst=nullptr) override
251  {
252  if (!started && pc.instAddr() == startPc)
253  started = true;
254 
255  if (started) {
256  return new TarmacParserRecord(when, tc, staticInst, pc, *this,
257  macroStaticInst);
258  } else {
259  return nullptr;
260  }
261  }
262 
263  private:
265  void advanceTraceToStartPc();
266 
268  std::ifstream trace;
269 
275 
280 
286 
289 
292 
294  bool cpuId;
295 
297  bool started;
298 
301 };
302 
303 } // namespace trace
304 } // namespace gem5
305 
306 #endif // __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:82
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Addr addr
The address that was accessed.
Definition: insttracer.hh:85
unsigned flags
The flags that were assigned to the request.
Definition: insttracer.hh:87
std::unique_ptr< PCStateBase > pc
Definition: insttracer.hh:71
union gem5::trace::InstRecord::Data data
Addr size
The size of the memory request.
Definition: insttracer.hh:86
ISetState
ARM instruction set state.
Definition: tarmac_base.hh:78
TarmacRecordType
TARMAC trace record type.
Definition: tarmac_base.hh:70
bool advanceTrace()
Advances the TARMAC trace up to the next instruction, register, or memory access record.
const char * iSetStateToStr(ISetState isetstate) const
Returns the string representation of an instruction set state.
static ParserInstEntry instRecord
Buffer for instruction trace records.
static std::list< ParserRegEntry > destRegRecords
List of records of destination registers.
bool mismatchOnPcOrOpcode
True if a mismatch has been detected for this instruction on PC or opcode.
static char buf[MaxLineLength]
Buffer used for trace file parsing.
static ParserRegEntry regRecord
Buffer for register trace records.
static void printMismatchHeader(const StaticInstPtr inst, const PCStateBase &pc)
Print a mismatch header containing the instruction fields as reported by gem5.
static TarmacRecordType currRecordType
Type of last parsed record.
bool mismatch
True if a mismatch has been detected for this instruction.
RequestPtr memReq
Request for memory write checks.
std::unordered_map< std::string, RegIndex > MiscRegMap
Map from misc.
bool parsingStarted
True if a TARMAC instruction record has already been parsed for this instruction.
bool readMemNoEffect(Addr addr, uint8_t *data, unsigned size, unsigned flags)
Performs a memory access to read the value written by a previous write.
static ParserMemEntry memRecord
Buffer for memory access trace records (stores only).
TarmacParserRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, const PCStateBase &_pc, TarmacParser &_parent, const StaticInstPtr _macroStaticInst=NULL)
Tarmac Parser: this tracer parses an existing Tarmac trace and it diffs it with gem5 simulation statu...
std::ifstream trace
TARMAC trace file.
TarmacParserParams Params
bool cpuId
If true, the trace format includes the CPU id.
void advanceTraceToStartPc()
Helper function to advance the trace up to startPc.
bool exitOnDiff
If true, the simulation is stopped as the first mismatch is detected.
bool macroopInProgress
True if a macroop is currently in progress.
bool exitOnInsnDiff
If true, the simulation is stopped as the first mismatch is detected on PC or opcode.
AddrRange ignoredAddrRange
Ignored addresses (ignored if empty).
InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, const PCStateBase &pc, const StaticInstPtr macroStaticInst=nullptr) override
bool memWrCheck
If true, memory write accesses are checked.
bool started
True if tracing has started.
TarmacParser(const Params &p)
Addr startPc
Tracing starts when the PC gets this value for the first time (ignored if 0x0).
STL list class.
Definition: stl.hh:51
Bitfield< 4 > pc
Bitfield< 54 > p
Definition: pagetable.hh:70
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
uint64_t Tick
Tick count type.
Definition: types.hh:58
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
TARMAC instruction trace record.
Definition: tarmac_base.hh:86
TARMAC memory access trace record (stores only).
Definition: tarmac_base.hh:123
TARMAC register trace record.
Definition: tarmac_base.hh:103
Event triggered to check the value of the destination registers.
ThreadContext * thread
Current thread context.
std::unique_ptr< PCStateBase > pc
PC of the current instruction.
bool mismatchOnPcOrOpcode
True if a mismatch has been detected for this instruction on PC or opcode.
TarmacParserRecordEvent(TarmacParser &_parent, ThreadContext *_thread, const StaticInstPtr _inst, const PCStateBase &_pc, bool _mismatch, bool _mismatch_on_pc_or_opcode)
TarmacParser & parent
Reference to the TARMAC trace object to which this record belongs.
bool mismatch
True if a mismatch has been detected for this instruction.
const StaticInstPtr inst
Current instruction.
const char * description() const
Return a C string describing the event.

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