gem5  v21.1.0.2
tarmac_parser.hh
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37 
46 #ifndef __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
47 #define __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
48 
49 #include <fstream>
50 #include <unordered_map>
51 
52 #include "base/trace.hh"
53 #include "base/types.hh"
54 #include "cpu/static_inst.hh"
55 #include "cpu/thread_context.hh"
56 #include "mem/request.hh"
57 #include "params/TarmacParser.hh"
58 #include "sim/insttracer.hh"
59 #include "tarmac_base.hh"
60 
61 namespace gem5
62 {
63 
64 namespace Trace {
65 
67 {
68  public:
76  {
88  bool mismatch;
94 
96  ThreadContext *_thread,
97  const StaticInstPtr _inst,
98  ArmISA::PCState _pc,
99  bool _mismatch,
100  bool _mismatch_on_pc_or_opcode) :
101  parent(_parent), thread(_thread), inst(_inst), pc(_pc),
102  mismatch(_mismatch),
103  mismatchOnPcOrOpcode(_mismatch_on_pc_or_opcode)
104  {
105  }
106 
107  void process();
108  const char *description() const;
109  };
110 
111  struct ParserInstEntry : public InstEntry
112  {
113  public:
114  uint64_t seq_num;
115  };
116 
117  struct ParserRegEntry : public RegEntry
118  {
119  public:
120  char repr[16];
121  };
122 
123  struct ParserMemEntry : public MemEntry
124  { };
125 
126  static const int MaxLineLength = 256;
127 
132  static void printMismatchHeader(const StaticInstPtr inst,
134 
135  TarmacParserRecord(Tick _when, ThreadContext *_thread,
136  const StaticInstPtr _staticInst, ArmISA::PCState _pc,
137  TarmacParser& _parent,
138  const StaticInstPtr _macroStaticInst = NULL);
139 
140  void dump() override;
141 
147  bool readMemNoEffect(Addr addr, uint8_t *data, unsigned size,
148  unsigned flags);
149 
150  private:
157  bool advanceTrace();
158 
160  const char *iSetStateToStr(ISetState isetstate) const;
161 
164 
167 
170 
173 
175  static char buf[MaxLineLength];
176 
179 
181  using MiscRegMap = std::unordered_map<std::string, RegIndex>;
183 
189 
191  bool mismatch;
192 
198 
201 
203  static int8_t maxVectorLength;
204 
205  protected:
207 };
208 
214 class TarmacParser : public InstTracer
215 {
216  friend class TarmacParserRecord;
217 
218  public:
219  typedef TarmacParserParams Params;
220 
221  TarmacParser(const Params &p) : InstTracer(p), startPc(p.start_pc),
222  exitOnDiff(p.exit_on_diff),
223  exitOnInsnDiff(p.exit_on_insn_diff),
224  memWrCheck(p.mem_wr_check),
225  ignoredAddrRange(p.ignore_mem_addr),
226  cpuId(p.cpu_id),
227  macroopInProgress(false)
228  {
229  assert(!(exitOnDiff && exitOnInsnDiff));
230 
231  trace.open(p.path_to_trace.c_str());
232  if (startPc == 0x0) {
233  started = true;
234  } else {
236  started = false;
237  }
238  }
239 
240  virtual ~TarmacParser()
241  {
242  trace.close();
243  }
244 
245  InstRecord *
246  getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst,
248  const StaticInstPtr macroStaticInst = NULL)
249  {
250  if (!started && pc.pc() == startPc)
251  started = true;
252 
253  if (started)
254  return new TarmacParserRecord(when, tc, staticInst, pc, *this,
255  macroStaticInst);
256  else
257  return NULL;
258  }
259 
260  private:
262  void advanceTraceToStartPc();
263 
265  std::ifstream trace;
266 
272 
277 
283 
286 
289 
291  bool cpuId;
292 
294  bool started;
295 
298 };
299 
300 } // namespace Trace
301 } // namespace gem5
302 
303 #endif // __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
gem5::Trace::TarmacParserRecord::mismatch
bool mismatch
True if a mismatch has been detected for this instruction.
Definition: tarmac_parser.hh:191
gem5::Trace::TarmacParserRecord::buf
static char buf[MaxLineLength]
Buffer used for trace file parsing.
Definition: tarmac_parser.hh:175
gem5::Trace::TarmacParser::memWrCheck
bool memWrCheck
If true, memory write accesses are checked.
Definition: tarmac_parser.hh:285
gem5::Trace::TarmacParser::TarmacParser
TarmacParser(const Params &p)
Definition: tarmac_parser.hh:221
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::TarmacParserRecordEvent
TarmacParserRecordEvent(TarmacParser &_parent, ThreadContext *_thread, const StaticInstPtr _inst, ArmISA::PCState _pc, bool _mismatch, bool _mismatch_on_pc_or_opcode)
Definition: tarmac_parser.hh:95
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::process
void process()
Definition: tarmac_parser.cc:740
gem5::Trace::TarmacParserRecord::destRegRecords
static std::list< ParserRegEntry > destRegRecords
List of records of destination registers.
Definition: tarmac_parser.hh:178
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::thread
ThreadContext * thread
Current thread context.
Definition: tarmac_parser.hh:82
gem5::Trace::TarmacParserRecord::maxVectorLength
static int8_t maxVectorLength
Max.
Definition: tarmac_parser.hh:203
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::mismatchOnPcOrOpcode
bool mismatchOnPcOrOpcode
True if a mismatch has been detected for this instruction on PC or opcode.
Definition: tarmac_parser.hh:93
insttracer.hh
gem5::Trace::TarmacParserRecord::dump
void dump() override
Definition: tarmac_parser.cc:979
gem5::Trace::TarmacBaseRecord
Definition: tarmac_base.hh:64
gem5::Trace::InstRecord::data
union gem5::Trace::InstRecord::@111 data
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::description
const char * description() const
Return a C string describing the event.
Definition: tarmac_parser.cc:942
gem5::Trace::TarmacParser::trace
std::ifstream trace
TARMAC trace file.
Definition: tarmac_parser.hh:265
gem5::Trace::TarmacParser::TarmacParserRecord
friend class TarmacParserRecord
Definition: tarmac_parser.hh:216
gem5::Trace::TarmacParserRecord::ParserMemEntry
Definition: tarmac_parser.hh:123
gem5::Trace::TarmacParser::Params
TarmacParserParams Params
Definition: tarmac_parser.hh:219
tarmac_base.hh
gem5::Trace::TarmacParser::started
bool started
True if tracing has started.
Definition: tarmac_parser.hh:294
gem5::Trace::TarmacParser::cpuId
bool cpuId
If true, the trace format includes the CPU id.
Definition: tarmac_parser.hh:291
request.hh
gem5::RefCountingPtr< StaticInst >
gem5::Trace::TarmacParser::ignoredAddrRange
AddrRange ignoredAddrRange
Ignored addresses (ignored if empty).
Definition: tarmac_parser.hh:288
gem5::Trace::TarmacParser::macroopInProgress
bool macroopInProgress
True if a macroop is currently in progress.
Definition: tarmac_parser.hh:297
gem5::Trace::TarmacParserRecord::iSetStateToStr
const char * iSetStateToStr(ISetState isetstate) const
Returns the string representation of an instruction set state.
Definition: tarmac_parser.cc:1357
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent
Event triggered to check the value of the destination registers.
Definition: tarmac_parser.hh:75
gem5::Trace::TarmacParserRecord::instRecord
static ParserInstEntry instRecord
Buffer for instruction trace records.
Definition: tarmac_parser.hh:163
gem5::Trace::TarmacParserRecord::mismatchOnPcOrOpcode
bool mismatchOnPcOrOpcode
True if a mismatch has been detected for this instruction on PC or opcode.
Definition: tarmac_parser.hh:197
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::parent
TarmacParser & parent
Reference to the TARMAC trace object to which this record belongs.
Definition: tarmac_parser.hh:80
gem5::Trace::TarmacBaseRecord::ISetState
ISetState
ARM instruction set state.
Definition: tarmac_base.hh:77
gem5::Trace::TarmacParserRecord::memRecord
static ParserMemEntry memRecord
Buffer for memory access trace records (stores only).
Definition: tarmac_parser.hh:169
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Trace::TarmacBaseRecord::InstEntry
TARMAC instruction trace record.
Definition: tarmac_base.hh:84
gem5::Trace::TarmacParserRecord::ParserRegEntry::repr
char repr[16]
Definition: tarmac_parser.hh:120
gem5::Trace::TarmacParserRecord::parent
TarmacParser & parent
Definition: tarmac_parser.hh:206
gem5::Trace::InstRecord::pc
TheISA::PCState pc
Definition: insttracer.hh:69
gem5::Trace::TarmacParserRecord
Definition: tarmac_parser.hh:66
gem5::Event
Definition: eventq.hh:251
gem5::Trace::TarmacParserRecord::MaxLineLength
static const int MaxLineLength
Definition: tarmac_parser.hh:126
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Trace::TarmacParserRecord::ParserInstEntry
Definition: tarmac_parser.hh:111
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Trace::TarmacParserRecord::TarmacParserRecord
TarmacParserRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, ArmISA::PCState _pc, TarmacParser &_parent, const StaticInstPtr _macroStaticInst=NULL)
Definition: tarmac_parser.cc:962
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::Trace::TarmacParserRecord::regRecord
static ParserRegEntry regRecord
Buffer for register trace records.
Definition: tarmac_parser.hh:166
gem5::Trace::InstTracer
Definition: insttracer.hh:259
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::inst
const StaticInstPtr inst
Current instruction.
Definition: tarmac_parser.hh:84
gem5::Trace::TarmacParser::exitOnDiff
bool exitOnDiff
If true, the simulation is stopped as the first mismatch is detected.
Definition: tarmac_parser.hh:276
gem5::Trace::TarmacBaseRecord::RegEntry
TARMAC register trace record.
Definition: tarmac_base.hh:101
gem5::Trace::TarmacParserRecord::ParserInstEntry::seq_num
uint64_t seq_num
Definition: tarmac_parser.hh:114
static_inst.hh
gem5::Trace::TarmacParser::~TarmacParser
virtual ~TarmacParser()
Definition: tarmac_parser.hh:240
gem5::Trace::TarmacBaseRecord::TarmacRecordType
TarmacRecordType
TARMAC trace record type.
Definition: tarmac_base.hh:68
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::pc
ArmISA::PCState pc
PC of the current instruction.
Definition: tarmac_parser.hh:86
gem5::Trace::TarmacParserRecord::ParserRegEntry
Definition: tarmac_parser.hh:117
gem5::Trace::TarmacParserRecord::memReq
RequestPtr memReq
Request for memory write checks.
Definition: tarmac_parser.hh:200
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::mismatch
bool mismatch
True if a mismatch has been detected for this instruction.
Definition: tarmac_parser.hh:88
gem5::Trace::TarmacParserRecord::readMemNoEffect
bool readMemNoEffect(Addr addr, uint8_t *data, unsigned size, unsigned flags)
Performs a memory access to read the value written by a previous write.
Definition: tarmac_parser.cc:1289
gem5::Trace::TarmacParser
Tarmac Parser: this tracer parses an existing Tarmac trace and it diffs it with gem5 simulation statu...
Definition: tarmac_parser.hh:214
gem5::Trace::InstRecord::size
Addr size
The size of the memory request.
Definition: insttracer.hh:84
gem5::Trace::TarmacParserRecord::miscRegMap
static MiscRegMap miscRegMap
Definition: tarmac_parser.hh:182
types.hh
gem5::Trace::TarmacBaseRecord::MemEntry
TARMAC memory access trace record (stores only).
Definition: tarmac_base.hh:121
gem5::Trace::TarmacParserRecord::parsingStarted
bool parsingStarted
True if a TARMAC instruction record has already been parsed for this instruction.
Definition: tarmac_parser.hh:188
gem5::Trace::InstRecord::addr
Addr addr
The address that was accessed.
Definition: insttracer.hh:83
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::Trace::TarmacParserRecord::printMismatchHeader
static void printMismatchHeader(const StaticInstPtr inst, ArmISA::PCState pc)
Print a mismatch header containing the instruction fields as reported by gem5.
Definition: tarmac_parser.cc:949
gem5::Trace::TarmacParser::startPc
Addr startPc
Tracing starts when the PC gets this value for the first time (ignored if 0x0).
Definition: tarmac_parser.hh:271
trace.hh
gem5::Trace::TarmacParser::advanceTraceToStartPc
void advanceTraceToStartPc()
Helper function to advance the trace up to startPc.
Definition: tarmac_parser.cc:1326
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
std::list
STL list class.
Definition: stl.hh:51
gem5::Trace::TarmacParser::getInstRecord
InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, ArmISA::PCState pc, const StaticInstPtr macroStaticInst=NULL)
Definition: tarmac_parser.hh:246
gem5::Trace::TarmacParser::exitOnInsnDiff
bool exitOnInsnDiff
If true, the simulation is stopped as the first mismatch is detected on PC or opcode.
Definition: tarmac_parser.hh:282
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Trace::TarmacParserRecord::advanceTrace
bool advanceTrace()
Advances the TARMAC trace up to the next instruction, register, or memory access record.
Definition: tarmac_parser.cc:1086
thread_context.hh
gem5::Trace::TarmacParserRecord::currRecordType
static TarmacRecordType currRecordType
Type of last parsed record.
Definition: tarmac_parser.hh:172
gem5::Trace::InstRecord::flags
unsigned flags
The flags that were assigned to the request.
Definition: insttracer.hh:85
gem5::Trace::TarmacParserRecord::MiscRegMap
std::unordered_map< std::string, RegIndex > MiscRegMap
Map from misc.
Definition: tarmac_parser.hh:181

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