gem5  v22.0.0.2
tarmac_parser.hh
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37 
46 #ifndef __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
47 #define __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
48 
49 #include <fstream>
50 #include <memory>
51 #include <unordered_map>
52 
53 #include "base/trace.hh"
54 #include "base/types.hh"
55 #include "cpu/static_inst.hh"
56 #include "cpu/thread_context.hh"
57 #include "mem/request.hh"
58 #include "params/TarmacParser.hh"
59 #include "sim/insttracer.hh"
60 #include "tarmac_base.hh"
61 
62 namespace gem5
63 {
64 
65 namespace Trace {
66 
68 {
69  public:
77  {
87  std::unique_ptr<PCStateBase> pc;
89  bool mismatch;
95 
97  ThreadContext *_thread,
98  const StaticInstPtr _inst,
99  const PCStateBase &_pc,
100  bool _mismatch,
101  bool _mismatch_on_pc_or_opcode) :
102  parent(_parent), thread(_thread), inst(_inst), pc(_pc.clone()),
103  mismatch(_mismatch),
104  mismatchOnPcOrOpcode(_mismatch_on_pc_or_opcode)
105  {
106  }
107 
108  void process();
109  const char *description() const;
110  };
111 
112  struct ParserInstEntry : public InstEntry
113  {
114  public:
115  uint64_t seq_num;
116  };
117 
118  struct ParserRegEntry : public RegEntry
119  {
120  public:
121  char repr[16];
122  };
123 
124  struct ParserMemEntry : public MemEntry
125  { };
126 
127  static const int MaxLineLength = 256;
128 
133  static void printMismatchHeader(const StaticInstPtr inst,
134  const PCStateBase &pc);
135 
136  TarmacParserRecord(Tick _when, ThreadContext *_thread,
137  const StaticInstPtr _staticInst,
138  const PCStateBase &_pc,
139  TarmacParser& _parent,
140  const StaticInstPtr _macroStaticInst = NULL);
141 
142  void dump() override;
143 
149  bool readMemNoEffect(Addr addr, uint8_t *data, unsigned size,
150  unsigned flags);
151 
152  private:
159  bool advanceTrace();
160 
162  const char *iSetStateToStr(ISetState isetstate) const;
163 
166 
169 
172 
175 
177  static char buf[MaxLineLength];
178 
181 
183  using MiscRegMap = std::unordered_map<std::string, RegIndex>;
185 
191 
193  bool mismatch;
194 
200 
203 
205  static int8_t maxVectorLength;
206 
207  protected:
209 };
210 
216 class TarmacParser : public InstTracer
217 {
218  friend class TarmacParserRecord;
219 
220  public:
221  typedef TarmacParserParams Params;
222 
223  TarmacParser(const Params &p) : InstTracer(p), startPc(p.start_pc),
224  exitOnDiff(p.exit_on_diff),
225  exitOnInsnDiff(p.exit_on_insn_diff),
226  memWrCheck(p.mem_wr_check),
227  ignoredAddrRange(p.ignore_mem_addr),
228  cpuId(p.cpu_id),
229  macroopInProgress(false)
230  {
231  assert(!(exitOnDiff && exitOnInsnDiff));
232 
233  trace.open(p.path_to_trace.c_str());
234  if (startPc == 0x0) {
235  started = true;
236  } else {
238  started = false;
239  }
240  }
241 
242  virtual ~TarmacParser()
243  {
244  trace.close();
245  }
246 
247  InstRecord *
248  getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst,
249  const PCStateBase &pc,
250  const StaticInstPtr macroStaticInst=nullptr) override
251  {
252  if (!started && pc.instAddr() == startPc)
253  started = true;
254 
255  if (started) {
256  return new TarmacParserRecord(when, tc, staticInst, pc, *this,
257  macroStaticInst);
258  } else {
259  return nullptr;
260  }
261  }
262 
263  private:
265  void advanceTraceToStartPc();
266 
268  std::ifstream trace;
269 
275 
280 
286 
289 
292 
294  bool cpuId;
295 
297  bool started;
298 
301 };
302 
303 } // namespace Trace
304 } // namespace gem5
305 
306 #endif // __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
gem5::Trace::TarmacParserRecord::mismatch
bool mismatch
True if a mismatch has been detected for this instruction.
Definition: tarmac_parser.hh:193
gem5::Trace::TarmacParserRecord::buf
static char buf[MaxLineLength]
Buffer used for trace file parsing.
Definition: tarmac_parser.hh:177
gem5::Trace::TarmacParser::memWrCheck
bool memWrCheck
If true, memory write accesses are checked.
Definition: tarmac_parser.hh:288
gem5::Trace::TarmacParser::TarmacParser
TarmacParser(const Params &p)
Definition: tarmac_parser.hh:223
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::process
void process()
Definition: tarmac_parser.cc:744
gem5::Trace::TarmacParserRecord::destRegRecords
static std::list< ParserRegEntry > destRegRecords
List of records of destination registers.
Definition: tarmac_parser.hh:180
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::thread
ThreadContext * thread
Current thread context.
Definition: tarmac_parser.hh:83
gem5::Trace::TarmacParserRecord::maxVectorLength
static int8_t maxVectorLength
Max.
Definition: tarmac_parser.hh:205
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::mismatchOnPcOrOpcode
bool mismatchOnPcOrOpcode
True if a mismatch has been detected for this instruction on PC or opcode.
Definition: tarmac_parser.hh:94
insttracer.hh
gem5::Trace::TarmacParserRecord::dump
void dump() override
Definition: tarmac_parser.cc:969
gem5::Trace::TarmacBaseRecord
Definition: tarmac_base.hh:64
gem5::Trace::InstRecord::data
union gem5::Trace::InstRecord::@336 data
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::description
const char * description() const
Return a C string describing the event.
Definition: tarmac_parser.cc:932
gem5::Trace::TarmacParser::trace
std::ifstream trace
TARMAC trace file.
Definition: tarmac_parser.hh:268
gem5::Trace::TarmacParser::TarmacParserRecord
friend class TarmacParserRecord
Definition: tarmac_parser.hh:218
gem5::Trace::TarmacParserRecord::ParserMemEntry
Definition: tarmac_parser.hh:124
gem5::Trace::TarmacParser::Params
TarmacParserParams Params
Definition: tarmac_parser.hh:221
tarmac_base.hh
gem5::Trace::TarmacParser::started
bool started
True if tracing has started.
Definition: tarmac_parser.hh:297
gem5::Trace::TarmacParser::cpuId
bool cpuId
If true, the trace format includes the CPU id.
Definition: tarmac_parser.hh:294
request.hh
gem5::RefCountingPtr< StaticInst >
gem5::Trace::TarmacParser::ignoredAddrRange
AddrRange ignoredAddrRange
Ignored addresses (ignored if empty).
Definition: tarmac_parser.hh:291
gem5::Trace::TarmacParser::macroopInProgress
bool macroopInProgress
True if a macroop is currently in progress.
Definition: tarmac_parser.hh:300
gem5::Trace::TarmacParserRecord::iSetStateToStr
const char * iSetStateToStr(ISetState isetstate) const
Returns the string representation of an instruction set state.
Definition: tarmac_parser.cc:1348
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent
Event triggered to check the value of the destination registers.
Definition: tarmac_parser.hh:76
gem5::Trace::TarmacParserRecord::instRecord
static ParserInstEntry instRecord
Buffer for instruction trace records.
Definition: tarmac_parser.hh:165
gem5::Trace::TarmacParserRecord::mismatchOnPcOrOpcode
bool mismatchOnPcOrOpcode
True if a mismatch has been detected for this instruction on PC or opcode.
Definition: tarmac_parser.hh:199
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::parent
TarmacParser & parent
Reference to the TARMAC trace object to which this record belongs.
Definition: tarmac_parser.hh:81
gem5::Trace::TarmacBaseRecord::ISetState
ISetState
ARM instruction set state.
Definition: tarmac_base.hh:77
gem5::Trace::TarmacParserRecord::memRecord
static ParserMemEntry memRecord
Buffer for memory access trace records (stores only).
Definition: tarmac_parser.hh:171
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Trace::TarmacBaseRecord::InstEntry
TARMAC instruction trace record.
Definition: tarmac_base.hh:84
gem5::Trace::TarmacParserRecord::ParserRegEntry::repr
char repr[16]
Definition: tarmac_parser.hh:121
gem5::Trace::TarmacParserRecord::parent
TarmacParser & parent
Definition: tarmac_parser.hh:208
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Trace::TarmacParserRecord
Definition: tarmac_parser.hh:67
gem5::Event
Definition: eventq.hh:251
gem5::Trace::TarmacParserRecord::MaxLineLength
static const int MaxLineLength
Definition: tarmac_parser.hh:127
gem5::Trace::TarmacParserRecord::ParserInstEntry
Definition: tarmac_parser.hh:112
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::Trace::TarmacParserRecord::regRecord
static ParserRegEntry regRecord
Buffer for register trace records.
Definition: tarmac_parser.hh:168
gem5::Trace::InstTracer
Definition: insttracer.hh:295
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::inst
const StaticInstPtr inst
Current instruction.
Definition: tarmac_parser.hh:85
gem5::Trace::TarmacParser::exitOnDiff
bool exitOnDiff
If true, the simulation is stopped as the first mismatch is detected.
Definition: tarmac_parser.hh:279
gem5::Trace::TarmacBaseRecord::RegEntry
TARMAC register trace record.
Definition: tarmac_base.hh:101
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::TarmacParserRecordEvent
TarmacParserRecordEvent(TarmacParser &_parent, ThreadContext *_thread, const StaticInstPtr _inst, const PCStateBase &_pc, bool _mismatch, bool _mismatch_on_pc_or_opcode)
Definition: tarmac_parser.hh:96
gem5::Trace::TarmacParserRecord::ParserInstEntry::seq_num
uint64_t seq_num
Definition: tarmac_parser.hh:115
static_inst.hh
gem5::Trace::TarmacParser::~TarmacParser
virtual ~TarmacParser()
Definition: tarmac_parser.hh:242
gem5::Trace::TarmacBaseRecord::TarmacRecordType
TarmacRecordType
TARMAC trace record type.
Definition: tarmac_base.hh:68
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Trace::TarmacParserRecord::ParserRegEntry
Definition: tarmac_parser.hh:118
gem5::Trace::TarmacParserRecord::memReq
RequestPtr memReq
Request for memory write checks.
Definition: tarmac_parser.hh:202
gem5::Trace::TarmacParser::getInstRecord
InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, const PCStateBase &pc, const StaticInstPtr macroStaticInst=nullptr) override
Definition: tarmac_parser.hh:248
gem5::Trace::InstRecord::pc
std::unique_ptr< PCStateBase > pc
Definition: insttracer.hh:72
gem5::Trace::TarmacParserRecord::TarmacParserRecord
TarmacParserRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, const PCStateBase &_pc, TarmacParser &_parent, const StaticInstPtr _macroStaticInst=NULL)
Definition: tarmac_parser.cc:952
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::mismatch
bool mismatch
True if a mismatch has been detected for this instruction.
Definition: tarmac_parser.hh:89
gem5::Trace::TarmacParserRecord::readMemNoEffect
bool readMemNoEffect(Addr addr, uint8_t *data, unsigned size, unsigned flags)
Performs a memory access to read the value written by a previous write.
Definition: tarmac_parser.cc:1279
gem5::Trace::TarmacParser
Tarmac Parser: this tracer parses an existing Tarmac trace and it diffs it with gem5 simulation statu...
Definition: tarmac_parser.hh:216
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::pc
std::unique_ptr< PCStateBase > pc
PC of the current instruction.
Definition: tarmac_parser.hh:87
gem5::Trace::InstRecord::size
Addr size
The size of the memory request.
Definition: insttracer.hh:87
gem5::Trace::TarmacParserRecord::miscRegMap
static MiscRegMap miscRegMap
Definition: tarmac_parser.hh:184
types.hh
gem5::Trace::TarmacBaseRecord::MemEntry
TARMAC memory access trace record (stores only).
Definition: tarmac_base.hh:121
gem5::Trace::TarmacParserRecord::parsingStarted
bool parsingStarted
True if a TARMAC instruction record has already been parsed for this instruction.
Definition: tarmac_parser.hh:190
gem5::Trace::InstRecord::addr
Addr addr
The address that was accessed.
Definition: insttracer.hh:86
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::Trace::TarmacParser::startPc
Addr startPc
Tracing starts when the PC gets this value for the first time (ignored if 0x0).
Definition: tarmac_parser.hh:274
trace.hh
gem5::Trace::TarmacParser::advanceTraceToStartPc
void advanceTraceToStartPc()
Helper function to advance the trace up to startPc.
Definition: tarmac_parser.cc:1317
gem5::Trace::InstRecord
Definition: insttracer.hh:61
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:81
std::list
STL list class.
Definition: stl.hh:51
gem5::Trace::TarmacParser::exitOnInsnDiff
bool exitOnInsnDiff
If true, the simulation is stopped as the first mismatch is detected on PC or opcode.
Definition: tarmac_parser.hh:285
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Trace::TarmacParserRecord::advanceTrace
bool advanceTrace()
Advances the TARMAC trace up to the next instruction, register, or memory access record.
Definition: tarmac_parser.cc:1076
thread_context.hh
gem5::Trace::TarmacParserRecord::currRecordType
static TarmacRecordType currRecordType
Type of last parsed record.
Definition: tarmac_parser.hh:174
gem5::Trace::InstRecord::flags
unsigned flags
The flags that were assigned to the request.
Definition: insttracer.hh:88
gem5::Trace::TarmacParserRecord::MiscRegMap
std::unordered_map< std::string, RegIndex > MiscRegMap
Map from misc.
Definition: tarmac_parser.hh:183
gem5::Trace::TarmacParserRecord::printMismatchHeader
static void printMismatchHeader(const StaticInstPtr inst, const PCStateBase &pc)
Print a mismatch header containing the instruction fields as reported by gem5.
Definition: tarmac_parser.cc:939

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