gem5  v22.1.0.0
tarmac_parser.cc
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1 /*
2  * Copyright (c) 2011,2017-2020 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
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25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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36  */
37 
38 #include <algorithm>
39 #include <cctype>
40 #include <cstring>
41 #include <iomanip>
42 #include <string>
43 
45 
47 #include "arch/arm/mmu.hh"
48 #include "arch/arm/regs/int.hh"
49 #include "arch/arm/regs/vec.hh"
50 #include "cpu/static_inst.hh"
51 #include "cpu/thread_context.hh"
52 #include "mem/packet.hh"
53 #include "mem/port_proxy.hh"
56 #include "sim/core.hh"
57 #include "sim/cur_tick.hh"
58 #include "sim/faults.hh"
59 #include "sim/full_system.hh"
60 #include "sim/sim_exit.hh"
61 
62 namespace gem5
63 {
64 
65 using namespace ArmISA;
66 
67 namespace trace {
68 
69 // TARMAC Parser static variables
70 const int TarmacParserRecord::MaxLineLength;
71 int8_t TarmacParserRecord::maxVectorLength = 0;
72 
73 TarmacParserRecord::ParserInstEntry TarmacParserRecord::instRecord;
74 TarmacParserRecord::ParserRegEntry TarmacParserRecord::regRecord;
75 TarmacParserRecord::ParserMemEntry TarmacParserRecord::memRecord;
76 TarmacBaseRecord::TarmacRecordType TarmacParserRecord::currRecordType;
77 
79  TarmacParserRecord::destRegRecords;
80 char TarmacParserRecord::buf[TarmacParserRecord::MaxLineLength];
81 TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
82 
83  { "cpsr", MISCREG_CPSR },
84  { "nzcv", MISCREG_NZCV },
85 
86  // AArch32 CP14 registers
87  { "dbgdidr", MISCREG_DBGDIDR },
88  { "dbgdscrint", MISCREG_DBGDSCRint },
89  { "dbgdccint", MISCREG_DBGDCCINT },
90  { "dbgdtrtxint", MISCREG_DBGDTRTXint },
91  { "dbgdtrrxint", MISCREG_DBGDTRRXint },
92  { "dbgwfar", MISCREG_DBGWFAR },
93  { "dbgvcr", MISCREG_DBGVCR },
94  { "dbgdtrrxext", MISCREG_DBGDTRRXext },
95  { "dbgdscrext", MISCREG_DBGDSCRext },
96  { "dbgdtrtxext", MISCREG_DBGDTRTXext },
97  { "dbgoseccr", MISCREG_DBGOSECCR },
98  { "dbgbvr0", MISCREG_DBGBVR0 },
99  { "dbgbvr1", MISCREG_DBGBVR1 },
100  { "dbgbvr2", MISCREG_DBGBVR2 },
101  { "dbgbvr3", MISCREG_DBGBVR3 },
102  { "dbgbvr4", MISCREG_DBGBVR4 },
103  { "dbgbvr5", MISCREG_DBGBVR5 },
104  { "dbgbvr6", MISCREG_DBGBVR6 },
105  { "dbgbvr7", MISCREG_DBGBVR7 },
106  { "dbgbvr8", MISCREG_DBGBVR8 },
107  { "dbgbvr9", MISCREG_DBGBVR9 },
108  { "dbgbvr10", MISCREG_DBGBVR10 },
109  { "dbgbvr11", MISCREG_DBGBVR11 },
110  { "dbgbvr12", MISCREG_DBGBVR12 },
111  { "dbgbvr13", MISCREG_DBGBVR13 },
112  { "dbgbvr14", MISCREG_DBGBVR14 },
113  { "dbgbvr15", MISCREG_DBGBVR15 },
114  { "dbgbcr0", MISCREG_DBGBCR0 },
115  { "dbgbcr1", MISCREG_DBGBCR1 },
116  { "dbgbcr2", MISCREG_DBGBCR2 },
117  { "dbgbcr3", MISCREG_DBGBCR3 },
118  { "dbgbcr4", MISCREG_DBGBCR4 },
119  { "dbgbcr5", MISCREG_DBGBCR5 },
120  { "dbgbcr6", MISCREG_DBGBCR6 },
121  { "dbgbcr7", MISCREG_DBGBCR7 },
122  { "dbgbcr8", MISCREG_DBGBCR8 },
123  { "dbgbcr9", MISCREG_DBGBCR9 },
124  { "dbgbcr10", MISCREG_DBGBCR10 },
125  { "dbgbcr11", MISCREG_DBGBCR11 },
126  { "dbgbcr12", MISCREG_DBGBCR12 },
127  { "dbgbcr13", MISCREG_DBGBCR13 },
128  { "dbgbcr14", MISCREG_DBGBCR14 },
129  { "dbgbcr15", MISCREG_DBGBCR15 },
130  { "dbgwvr0", MISCREG_DBGWVR0 },
131  { "dbgwvr1", MISCREG_DBGWVR1 },
132  { "dbgwvr2", MISCREG_DBGWVR2 },
133  { "dbgwvr3", MISCREG_DBGWVR3 },
134  { "dbgwvr4", MISCREG_DBGWVR4 },
135  { "dbgwvr5", MISCREG_DBGWVR5 },
136  { "dbgwvr6", MISCREG_DBGWVR6 },
137  { "dbgwvr7", MISCREG_DBGWVR7 },
138  { "dbgwvr8", MISCREG_DBGWVR8 },
139  { "dbgwvr9", MISCREG_DBGWVR9 },
140  { "dbgwvr10", MISCREG_DBGWVR10 },
141  { "dbgwvr11", MISCREG_DBGWVR11 },
142  { "dbgwvr12", MISCREG_DBGWVR12 },
143  { "dbgwvr13", MISCREG_DBGWVR13 },
144  { "dbgwvr14", MISCREG_DBGWVR14 },
145  { "dbgwvr15", MISCREG_DBGWVR15 },
146  { "dbgwcr0", MISCREG_DBGWCR0 },
147  { "dbgwcr1", MISCREG_DBGWCR1 },
148  { "dbgwcr2", MISCREG_DBGWCR2 },
149  { "dbgwcr3", MISCREG_DBGWCR3 },
150  { "dbgwcr4", MISCREG_DBGWCR4 },
151  { "dbgwcr5", MISCREG_DBGWCR5 },
152  { "dbgwcr6", MISCREG_DBGWCR6 },
153  { "dbgwcr7", MISCREG_DBGWCR7 },
154  { "dbgwcr8", MISCREG_DBGWCR8 },
155  { "dbgwcr9", MISCREG_DBGWCR9 },
156  { "dbgwcr10", MISCREG_DBGWCR10 },
157  { "dbgwcr11", MISCREG_DBGWCR11 },
158  { "dbgwcr12", MISCREG_DBGWCR12 },
159  { "dbgwcr13", MISCREG_DBGWCR13 },
160  { "dbgwcr14", MISCREG_DBGWCR14 },
161  { "dbgwcr15", MISCREG_DBGWCR15 },
162  { "dbgdrar", MISCREG_DBGDRAR },
163  { "dbgbxvr0", MISCREG_DBGBXVR0 },
164  { "dbgbxvr1", MISCREG_DBGBXVR1 },
165  { "dbgbxvr2", MISCREG_DBGBXVR2 },
166  { "dbgbxvr3", MISCREG_DBGBXVR3 },
167  { "dbgbxvr4", MISCREG_DBGBXVR4 },
168  { "dbgbxvr5", MISCREG_DBGBXVR5 },
169  { "dbgbxvr6", MISCREG_DBGBXVR6 },
170  { "dbgbxvr7", MISCREG_DBGBXVR7 },
171  { "dbgbxvr8", MISCREG_DBGBXVR8 },
172  { "dbgbxvr9", MISCREG_DBGBXVR9 },
173  { "dbgbxvr10", MISCREG_DBGBXVR10 },
174  { "dbgbxvr11", MISCREG_DBGBXVR11 },
175  { "dbgbxvr12", MISCREG_DBGBXVR12 },
176  { "dbgbxvr13", MISCREG_DBGBXVR13 },
177  { "dbgbxvr14", MISCREG_DBGBXVR14 },
178  { "dbgbxvr15", MISCREG_DBGBXVR15 },
179  { "dbgoslar", MISCREG_DBGOSLAR },
180  { "dbgoslsr", MISCREG_DBGOSLSR },
181  { "dbgosdlr", MISCREG_DBGOSDLR },
182  { "dbgprcr", MISCREG_DBGPRCR },
183  { "dbgdsar", MISCREG_DBGDSAR },
184  { "dbgclaimset", MISCREG_DBGCLAIMSET },
185  { "dbgclaimclr", MISCREG_DBGCLAIMCLR },
186  { "dbgauthstatus", MISCREG_DBGAUTHSTATUS },
187  { "dbgdevid2", MISCREG_DBGDEVID2 },
188  { "dbgdevid1", MISCREG_DBGDEVID1 },
189  { "dbgdevid0", MISCREG_DBGDEVID0 },
190  { "teecr", MISCREG_TEECR },
191  { "jidr", MISCREG_JIDR },
192  { "teehbr", MISCREG_TEEHBR },
193  { "joscr", MISCREG_JOSCR },
194  { "jmcr", MISCREG_JMCR },
195 
196  // AArch32 CP15 registers
197  { "midr", MISCREG_MIDR },
198  { "ctr", MISCREG_CTR },
199  { "tcmtr", MISCREG_TCMTR },
200  { "tlbtr", MISCREG_TLBTR },
201  { "mpidr", MISCREG_MPIDR },
202  { "revidr", MISCREG_REVIDR },
203  { "id_pfr0", MISCREG_ID_PFR0 },
204  { "id_pfr1", MISCREG_ID_PFR1 },
205  { "id_dfr0", MISCREG_ID_DFR0 },
206  { "id_afr0", MISCREG_ID_AFR0 },
207  { "id_mmfr0", MISCREG_ID_MMFR0 },
208  { "id_mmfr1", MISCREG_ID_MMFR1 },
209  { "id_mmfr2", MISCREG_ID_MMFR2 },
210  { "id_mmfr3", MISCREG_ID_MMFR3 },
211  { "id_mmfr4", MISCREG_ID_MMFR4 },
212  { "id_isar0", MISCREG_ID_ISAR0 },
213  { "id_isar1", MISCREG_ID_ISAR1 },
214  { "id_isar2", MISCREG_ID_ISAR2 },
215  { "id_isar3", MISCREG_ID_ISAR3 },
216  { "id_isar4", MISCREG_ID_ISAR4 },
217  { "id_isar5", MISCREG_ID_ISAR5 },
218  { "id_isar6", MISCREG_ID_ISAR6 },
219  { "ccsidr", MISCREG_CCSIDR },
220  { "clidr", MISCREG_CLIDR },
221  { "aidr", MISCREG_AIDR },
222  { "csselr_ns", MISCREG_CSSELR_NS },
223  { "csselr_s", MISCREG_CSSELR_S },
224  { "vpidr", MISCREG_VPIDR },
225  { "vmpidr", MISCREG_VMPIDR },
226  { "sctlr_ns", MISCREG_SCTLR_NS },
227  { "sctlr_s", MISCREG_SCTLR_S },
228  { "actlr_ns", MISCREG_ACTLR_NS },
229  { "actlr_s", MISCREG_ACTLR_S },
230  { "cpacr", MISCREG_CPACR },
231  { "scr", MISCREG_SCR },
232  { "sder", MISCREG_SDER },
233  { "nsacr", MISCREG_NSACR },
234  { "hsctlr", MISCREG_HSCTLR },
235  { "hactlr", MISCREG_HACTLR },
236  { "hcr", MISCREG_HCR },
237  { "hcr2", MISCREG_HCR2 },
238  { "hdcr", MISCREG_HDCR },
239  { "hcptr", MISCREG_HCPTR },
240  { "hstr", MISCREG_HSTR },
241  { "hacr", MISCREG_HACR },
242  { "ttbr0_ns", MISCREG_TTBR0_NS },
243  { "ttbr0_s", MISCREG_TTBR0_S },
244  { "ttbr1_ns", MISCREG_TTBR1_NS },
245  { "ttbr1_s", MISCREG_TTBR1_S },
246  { "ttbcr_ns", MISCREG_TTBCR_NS },
247  { "ttbcr_s", MISCREG_TTBCR_S },
248  { "htcr", MISCREG_HTCR },
249  { "vtcr", MISCREG_VTCR },
250  { "dacr_ns", MISCREG_DACR_NS },
251  { "dacr_s", MISCREG_DACR_S },
252  { "dfsr_ns", MISCREG_DFSR_NS },
253  { "dfsr_s", MISCREG_DFSR_S },
254  { "ifsr_ns", MISCREG_IFSR_NS },
255  { "ifsr_s", MISCREG_IFSR_S },
256  { "adfsr_ns", MISCREG_ADFSR_NS },
257  { "adfsr_s", MISCREG_ADFSR_S },
258  { "aifsr_ns", MISCREG_AIFSR_NS },
259  { "aifsr_s", MISCREG_AIFSR_S },
260  { "hadfsr", MISCREG_HADFSR },
261  { "haifsr", MISCREG_HAIFSR },
262  { "hsr", MISCREG_HSR },
263  { "dfar_ns", MISCREG_DFAR_NS },
264  { "dfar_s", MISCREG_DFAR_S },
265  { "ifar_ns", MISCREG_IFAR_NS },
266  { "ifar_s", MISCREG_IFAR_S },
267  { "hdfar", MISCREG_HDFAR },
268  { "hifar", MISCREG_HIFAR },
269  { "hpfar", MISCREG_HPFAR },
270  { "icialluis", MISCREG_ICIALLUIS },
271  { "bpiallis", MISCREG_BPIALLIS },
272  { "par_ns", MISCREG_PAR_NS },
273  { "par_s", MISCREG_PAR_S },
274  { "iciallu", MISCREG_ICIALLU },
275  { "icimvau", MISCREG_ICIMVAU },
276  { "cp15isb", MISCREG_CP15ISB },
277  { "bpiall", MISCREG_BPIALL },
278  { "bpimva", MISCREG_BPIMVA },
279  { "dcimvac", MISCREG_DCIMVAC },
280  { "dcisw", MISCREG_DCISW },
281  { "ats1cpr", MISCREG_ATS1CPR },
282  { "ats1cpw", MISCREG_ATS1CPW },
283  { "ats1cur", MISCREG_ATS1CUR },
284  { "ats1cuw", MISCREG_ATS1CUW },
285  { "ats12nsopr", MISCREG_ATS12NSOPR },
286  { "ats12nsopw", MISCREG_ATS12NSOPW },
287  { "ats12nsour", MISCREG_ATS12NSOUR },
288  { "ats12nsouw", MISCREG_ATS12NSOUW },
289  { "dccmvac", MISCREG_DCCMVAC },
290  { "dccsw", MISCREG_DCCSW },
291  { "cp15dsb", MISCREG_CP15DSB },
292  { "cp15dmb", MISCREG_CP15DMB },
293  { "dccmvau", MISCREG_DCCMVAU },
294  { "dccimvac", MISCREG_DCCIMVAC },
295  { "dccisw", MISCREG_DCCISW },
296  { "ats1hr", MISCREG_ATS1HR },
297  { "ats1hw", MISCREG_ATS1HW },
298  { "tlbiallis", MISCREG_TLBIALLIS },
299  { "tlbimvais", MISCREG_TLBIMVAIS },
300  { "tlbiasidis", MISCREG_TLBIASIDIS },
301  { "tlbimvaais", MISCREG_TLBIMVAAIS },
302  { "tlbimvalis", MISCREG_TLBIMVALIS },
303  { "tlbimvaalis", MISCREG_TLBIMVAALIS },
304  { "itlbiall", MISCREG_ITLBIALL },
305  { "itlbimva", MISCREG_ITLBIMVA },
306  { "itlbiasid", MISCREG_ITLBIASID },
307  { "dtlbiall", MISCREG_DTLBIALL },
308  { "dtlbimva", MISCREG_DTLBIMVA },
309  { "dtlbiasid", MISCREG_DTLBIASID },
310  { "tlbiall", MISCREG_TLBIALL },
311  { "tlbimva", MISCREG_TLBIMVA },
312  { "tlbiasid", MISCREG_TLBIASID },
313  { "tlbimvaa", MISCREG_TLBIMVAA },
314  { "tlbimval", MISCREG_TLBIMVAL },
315  { "tlbimvaal", MISCREG_TLBIMVAAL },
316  { "tlbiipas2is", MISCREG_TLBIIPAS2IS },
317  { "tlbiipas2lis", MISCREG_TLBIIPAS2LIS },
318  { "tlbiallhis", MISCREG_TLBIALLHIS },
319  { "tlbimvahis", MISCREG_TLBIMVAHIS },
320  { "tlbiallnsnhis", MISCREG_TLBIALLNSNHIS },
321  { "tlbimvalhis", MISCREG_TLBIMVALHIS },
322  { "tlbiipas2", MISCREG_TLBIIPAS2 },
323  { "tlbiipas2l", MISCREG_TLBIIPAS2L },
324  { "tlbiallh", MISCREG_TLBIALLH },
325  { "tlbimvah", MISCREG_TLBIMVAH },
326  { "tlbiallnsnh", MISCREG_TLBIALLNSNH },
327  { "tlbimvalh", MISCREG_TLBIMVALH },
328  { "pmcr", MISCREG_PMCR },
329  { "pmcntenset", MISCREG_PMCNTENSET },
330  { "pmcntenclr", MISCREG_PMCNTENCLR },
331  { "pmovsr", MISCREG_PMOVSR },
332  { "pmswinc", MISCREG_PMSWINC },
333  { "pmselr", MISCREG_PMSELR },
334  { "pmceid0", MISCREG_PMCEID0 },
335  { "pmceid1", MISCREG_PMCEID1 },
336  { "pmccntr", MISCREG_PMCCNTR },
337  { "pmxevtyper", MISCREG_PMXEVTYPER },
338  { "pmccfiltr", MISCREG_PMCCFILTR },
339  { "pmxevcntr", MISCREG_PMXEVCNTR },
340  { "pmuserenr", MISCREG_PMUSERENR },
341  { "pmintenset", MISCREG_PMINTENSET },
342  { "pmintenclr", MISCREG_PMINTENCLR },
343  { "pmovsset", MISCREG_PMOVSSET },
344  { "l2ctlr", MISCREG_L2CTLR },
345  { "l2ectlr", MISCREG_L2ECTLR },
346  { "prrr_ns", MISCREG_PRRR_NS },
347  { "prrr_s", MISCREG_PRRR_S },
348  { "mair0_ns", MISCREG_MAIR0_NS },
349  { "mair0_s", MISCREG_MAIR0_S },
350  { "nmrr_ns", MISCREG_NMRR_NS },
351  { "nmrr_s", MISCREG_NMRR_S },
352  { "mair1_ns", MISCREG_MAIR1_NS },
353  { "mair1_s", MISCREG_MAIR1_S },
354  { "amair0_ns", MISCREG_AMAIR0_NS },
355  { "amair0_s", MISCREG_AMAIR0_S },
356  { "amair1_ns", MISCREG_AMAIR1_NS },
357  { "amair1_s", MISCREG_AMAIR1_S },
358  { "hmair0", MISCREG_HMAIR0 },
359  { "hmair1", MISCREG_HMAIR1 },
360  { "hamair0", MISCREG_HAMAIR0 },
361  { "hamair1", MISCREG_HAMAIR1 },
362  { "vbar_ns", MISCREG_VBAR_NS },
363  { "vbar_s", MISCREG_VBAR_S },
364  { "mvbar", MISCREG_MVBAR },
365  { "rmr", MISCREG_RMR },
366  { "isr", MISCREG_ISR },
367  { "hvbar", MISCREG_HVBAR },
368  { "fcseidr", MISCREG_FCSEIDR },
369  { "contextidr_ns", MISCREG_CONTEXTIDR_NS },
370  { "contextidr_s", MISCREG_CONTEXTIDR_S },
371  { "tpidrurw_ns", MISCREG_TPIDRURW_NS },
372  { "tpidrurw_s", MISCREG_TPIDRURW_S },
373  { "tpidruro_ns", MISCREG_TPIDRURO_NS },
374  { "tpidruro_s", MISCREG_TPIDRURO_S },
375  { "tpidrprw_ns", MISCREG_TPIDRPRW_NS },
376  { "tpidrprw_s", MISCREG_TPIDRPRW_S },
377  { "htpidr", MISCREG_HTPIDR },
378  { "cntfrq", MISCREG_CNTFRQ },
379  { "cntkctl", MISCREG_CNTKCTL },
380  { "cntp_tval_ns", MISCREG_CNTP_TVAL_NS },
381  { "cntp_tval_s", MISCREG_CNTP_TVAL_S },
382  { "cntp_ctl_ns", MISCREG_CNTP_CTL_NS },
383  { "cntp_ctl_s", MISCREG_CNTP_CTL_S },
384  { "cntv_tval", MISCREG_CNTV_TVAL },
385  { "cntv_ctl", MISCREG_CNTV_CTL },
386  { "cnthctl", MISCREG_CNTHCTL },
387  { "cnthp_tval", MISCREG_CNTHP_TVAL },
388  { "cnthp_ctl", MISCREG_CNTHP_CTL },
389  { "il1data0", MISCREG_IL1DATA0 },
390  { "il1data1", MISCREG_IL1DATA1 },
391  { "il1data2", MISCREG_IL1DATA2 },
392  { "il1data3", MISCREG_IL1DATA3 },
393  { "dl1data0", MISCREG_DL1DATA0 },
394  { "dl1data1", MISCREG_DL1DATA1 },
395  { "dl1data2", MISCREG_DL1DATA2 },
396  { "dl1data3", MISCREG_DL1DATA3 },
397  { "dl1data4", MISCREG_DL1DATA4 },
398  { "ramindex", MISCREG_RAMINDEX },
399  { "l2actlr", MISCREG_L2ACTLR },
400  { "cbar", MISCREG_CBAR },
401  { "httbr", MISCREG_HTTBR },
402  { "vttbr", MISCREG_VTTBR },
403  { "cntpct", MISCREG_CNTPCT },
404  { "cntvct", MISCREG_CNTVCT },
405  { "cntp_cval_ns", MISCREG_CNTP_CVAL_NS },
406  { "cntp_cval_s", MISCREG_CNTP_CVAL_S },
407  { "cntv_cval", MISCREG_CNTV_CVAL },
408  { "cntvoff", MISCREG_CNTVOFF },
409  { "cnthp_cval", MISCREG_CNTHP_CVAL },
410  { "cpumerrsr", MISCREG_CPUMERRSR },
411  { "l2merrsr", MISCREG_L2MERRSR },
412 
413  // AArch64 registers (Op0=2)
414  { "mdccint_el1", MISCREG_MDCCINT_EL1 },
415  { "osdtrrx_el1", MISCREG_OSDTRRX_EL1 },
416  { "mdscr_el1", MISCREG_MDSCR_EL1 },
417  { "osdtrtx_el1", MISCREG_OSDTRTX_EL1 },
418  { "oseccr_el1", MISCREG_OSECCR_EL1 },
419  { "dbgbvr0_el1", MISCREG_DBGBVR0_EL1 },
420  { "dbgbvr1_el1", MISCREG_DBGBVR1_EL1 },
421  { "dbgbvr2_el1", MISCREG_DBGBVR2_EL1 },
422  { "dbgbvr3_el1", MISCREG_DBGBVR3_EL1 },
423  { "dbgbvr4_el1", MISCREG_DBGBVR4_EL1 },
424  { "dbgbvr5_el1", MISCREG_DBGBVR5_EL1 },
425  { "dbgbvr6_el1", MISCREG_DBGBVR6_EL1 },
426  { "dbgbvr7_el1", MISCREG_DBGBVR7_EL1 },
427  { "dbgbvr8_el1", MISCREG_DBGBVR8_EL1 },
428  { "dbgbvr9_el1", MISCREG_DBGBVR9_EL1 },
429  { "dbgbvr10_el1", MISCREG_DBGBVR10_EL1 },
430  { "dbgbvr11_el1", MISCREG_DBGBVR11_EL1 },
431  { "dbgbvr12_el1", MISCREG_DBGBVR12_EL1 },
432  { "dbgbvr13_el1", MISCREG_DBGBVR13_EL1 },
433  { "dbgbvr14_el1", MISCREG_DBGBVR14_EL1 },
434  { "dbgbvr15_el1", MISCREG_DBGBVR15_EL1 },
435  { "dbgbcr0_el1", MISCREG_DBGBCR0_EL1 },
436  { "dbgbcr1_el1", MISCREG_DBGBCR1_EL1 },
437  { "dbgbcr2_el1", MISCREG_DBGBCR2_EL1 },
438  { "dbgbcr3_el1", MISCREG_DBGBCR3_EL1 },
439  { "dbgbcr4_el1", MISCREG_DBGBCR4_EL1 },
440  { "dbgbcr5_el1", MISCREG_DBGBCR5_EL1 },
441  { "dbgbcr6_el1", MISCREG_DBGBCR6_EL1 },
442  { "dbgbcr7_el1", MISCREG_DBGBCR7_EL1 },
443  { "dbgbcr8_el1", MISCREG_DBGBCR8_EL1 },
444  { "dbgbcr9_el1", MISCREG_DBGBCR9_EL1 },
445  { "dbgbcr10_el1", MISCREG_DBGBCR10_EL1 },
446  { "dbgbcr11_el1", MISCREG_DBGBCR11_EL1 },
447  { "dbgbcr12_el1", MISCREG_DBGBCR12_EL1 },
448  { "dbgbcr13_el1", MISCREG_DBGBCR13_EL1 },
449  { "dbgbcr14_el1", MISCREG_DBGBCR14_EL1 },
450  { "dbgbcr15_el1", MISCREG_DBGBCR15_EL1 },
451  { "dbgwvr0_el1", MISCREG_DBGWVR0_EL1 },
452  { "dbgwvr1_el1", MISCREG_DBGWVR1_EL1 },
453  { "dbgwvr2_el1", MISCREG_DBGWVR2_EL1 },
454  { "dbgwvr3_el1", MISCREG_DBGWVR3_EL1 },
455  { "dbgwvr4_el1", MISCREG_DBGWVR4_EL1 },
456  { "dbgwvr5_el1", MISCREG_DBGWVR5_EL1 },
457  { "dbgwvr6_el1", MISCREG_DBGWVR6_EL1 },
458  { "dbgwvr7_el1", MISCREG_DBGWVR7_EL1 },
459  { "dbgwvr8_el1", MISCREG_DBGWVR8_EL1 },
460  { "dbgwvr9_el1", MISCREG_DBGWVR9_EL1 },
461  { "dbgwvr10_el1", MISCREG_DBGWVR10_EL1 },
462  { "dbgwvr11_el1", MISCREG_DBGWVR11_EL1 },
463  { "dbgwvr12_el1", MISCREG_DBGWVR12_EL1 },
464  { "dbgwvr13_el1", MISCREG_DBGWVR13_EL1 },
465  { "dbgwvr14_el1", MISCREG_DBGWVR14_EL1 },
466  { "dbgwvr15_el1", MISCREG_DBGWVR15_EL1 },
467  { "dbgwcr0_el1", MISCREG_DBGWCR0_EL1 },
468  { "dbgwcr1_el1", MISCREG_DBGWCR1_EL1 },
469  { "dbgwcr2_el1", MISCREG_DBGWCR2_EL1 },
470  { "dbgwcr3_el1", MISCREG_DBGWCR3_EL1 },
471  { "dbgwcr4_el1", MISCREG_DBGWCR4_EL1 },
472  { "dbgwcr5_el1", MISCREG_DBGWCR5_EL1 },
473  { "dbgwcr6_el1", MISCREG_DBGWCR6_EL1 },
474  { "dbgwcr7_el1", MISCREG_DBGWCR7_EL1 },
475  { "dbgwcr8_el1", MISCREG_DBGWCR8_EL1 },
476  { "dbgwcr9_el1", MISCREG_DBGWCR9_EL1 },
477  { "dbgwcr10_el1", MISCREG_DBGWCR10_EL1 },
478  { "dbgwcr11_el1", MISCREG_DBGWCR11_EL1 },
479  { "dbgwcr12_el1", MISCREG_DBGWCR12_EL1 },
480  { "dbgwcr13_el1", MISCREG_DBGWCR13_EL1 },
481  { "dbgwcr14_el1", MISCREG_DBGWCR14_EL1 },
482  { "dbgwcr15_el1", MISCREG_DBGWCR15_EL1 },
483  { "mdccsr_el0", MISCREG_MDCCSR_EL0 },
484  { "mddtr_el0", MISCREG_MDDTR_EL0 },
485  { "mddtrtx_el0", MISCREG_MDDTRTX_EL0 },
486  { "mddtrrx_el0", MISCREG_MDDTRRX_EL0 },
487  { "dbgvcr32_el2", MISCREG_DBGVCR32_EL2 },
488  { "mdrar_el1", MISCREG_MDRAR_EL1 },
489  { "oslar_el1", MISCREG_OSLAR_EL1 },
490  { "oslsr_el1", MISCREG_OSLSR_EL1 },
491  { "osdlr_el1", MISCREG_OSDLR_EL1 },
492  { "dbgprcr_el1", MISCREG_DBGPRCR_EL1 },
493  { "dbgclaimset_el1", MISCREG_DBGCLAIMSET_EL1 },
494  { "dbgclaimclr_el1", MISCREG_DBGCLAIMCLR_EL1 },
495  { "dbgauthstatus_el1", MISCREG_DBGAUTHSTATUS_EL1 },
496  { "teecr32_el1", MISCREG_TEECR32_EL1 },
497  { "teehbr32_el1", MISCREG_TEEHBR32_EL1 },
498 
499  // AArch64 registers (Op0=1,3)
500  { "midr_el1", MISCREG_MIDR_EL1 },
501  { "mpidr_el1", MISCREG_MPIDR_EL1 },
502  { "revidr_el1", MISCREG_REVIDR_EL1 },
503  { "id_pfr0_el1", MISCREG_ID_PFR0_EL1 },
504  { "id_pfr1_el1", MISCREG_ID_PFR1_EL1 },
505  { "id_dfr0_el1", MISCREG_ID_DFR0_EL1 },
506  { "id_afr0_el1", MISCREG_ID_AFR0_EL1 },
507  { "id_mmfr0_el1", MISCREG_ID_MMFR0_EL1 },
508  { "id_mmfr1_el1", MISCREG_ID_MMFR1_EL1 },
509  { "id_mmfr2_el1", MISCREG_ID_MMFR2_EL1 },
510  { "id_mmfr3_el1", MISCREG_ID_MMFR3_EL1 },
511  { "id_mmfr4_el1", MISCREG_ID_MMFR4_EL1 },
512  { "id_isar0_el1", MISCREG_ID_ISAR0_EL1 },
513  { "id_isar1_el1", MISCREG_ID_ISAR1_EL1 },
514  { "id_isar2_el1", MISCREG_ID_ISAR2_EL1 },
515  { "id_isar3_el1", MISCREG_ID_ISAR3_EL1 },
516  { "id_isar4_el1", MISCREG_ID_ISAR4_EL1 },
517  { "id_isar5_el1", MISCREG_ID_ISAR5_EL1 },
518  { "id_isar6_el1", MISCREG_ID_ISAR6_EL1 },
519  { "mvfr0_el1", MISCREG_MVFR0_EL1 },
520  { "mvfr1_el1", MISCREG_MVFR1_EL1 },
521  { "mvfr2_el1", MISCREG_MVFR2_EL1 },
522  { "id_aa64pfr0_el1", MISCREG_ID_AA64PFR0_EL1 },
523  { "id_aa64pfr1_el1", MISCREG_ID_AA64PFR1_EL1 },
524  { "id_aa64dfr0_el1", MISCREG_ID_AA64DFR0_EL1 },
525  { "id_aa64dfr1_el1", MISCREG_ID_AA64DFR1_EL1 },
526  { "id_aa64afr0_el1", MISCREG_ID_AA64AFR0_EL1 },
527  { "id_aa64afr1_el1", MISCREG_ID_AA64AFR1_EL1 },
528  { "id_aa64isar0_el1", MISCREG_ID_AA64ISAR0_EL1 },
529  { "id_aa64isar1_el1", MISCREG_ID_AA64ISAR1_EL1 },
530  { "id_aa64mmfr0_el1", MISCREG_ID_AA64MMFR0_EL1 },
531  { "id_aa64mmfr1_el1", MISCREG_ID_AA64MMFR1_EL1 },
532  { "id_aa64mmfr2_el1", MISCREG_ID_AA64MMFR2_EL1 },
533  { "ccsidr_el1", MISCREG_CCSIDR_EL1 },
534  { "clidr_el1", MISCREG_CLIDR_EL1 },
535  { "aidr_el1", MISCREG_AIDR_EL1 },
536  { "csselr_el1", MISCREG_CSSELR_EL1 },
537  { "ctr_el0", MISCREG_CTR_EL0 },
538  { "dczid_el0", MISCREG_DCZID_EL0 },
539  { "vpidr_el2", MISCREG_VPIDR_EL2 },
540  { "vmpidr_el2", MISCREG_VMPIDR_EL2 },
541  { "sctlr_el1", MISCREG_SCTLR_EL1 },
542  { "actlr_el1", MISCREG_ACTLR_EL1 },
543  { "cpacr_el1", MISCREG_CPACR_EL1 },
544  { "sctlr_el2", MISCREG_SCTLR_EL2 },
545  { "actlr_el2", MISCREG_ACTLR_EL2 },
546  { "hcr_el2", MISCREG_HCR_EL2 },
547  { "mdcr_el2", MISCREG_MDCR_EL2 },
548  { "cptr_el2", MISCREG_CPTR_EL2 },
549  { "hstr_el2", MISCREG_HSTR_EL2 },
550  { "hacr_el2", MISCREG_HACR_EL2 },
551  { "sctlr_el3", MISCREG_SCTLR_EL3 },
552  { "actlr_el3", MISCREG_ACTLR_EL3 },
553  { "scr_el3", MISCREG_SCR_EL3 },
554  { "sder32_el3", MISCREG_SDER32_EL3 },
555  { "cptr_el3", MISCREG_CPTR_EL3 },
556  { "mdcr_el3", MISCREG_MDCR_EL3 },
557  { "ttbr0_el1", MISCREG_TTBR0_EL1 },
558  { "ttbr1_el1", MISCREG_TTBR1_EL1 },
559  { "tcr_el1", MISCREG_TCR_EL1 },
560  { "ttbr0_el2", MISCREG_TTBR0_EL2 },
561  { "tcr_el2", MISCREG_TCR_EL2 },
562  { "vttbr_el2", MISCREG_VTTBR_EL2 },
563  { "vtcr_el2", MISCREG_VTCR_EL2 },
564  { "ttbr0_el3", MISCREG_TTBR0_EL3 },
565  { "tcr_el3", MISCREG_TCR_EL3 },
566  { "dacr32_el2", MISCREG_DACR32_EL2 },
567  { "spsr_el1", MISCREG_SPSR_EL1 },
568  { "elr_el1", MISCREG_ELR_EL1 },
569  { "sp_el0", MISCREG_SP_EL0 },
570  { "spsel", MISCREG_SPSEL },
571  { "currentel", MISCREG_CURRENTEL },
572  { "nzcv", MISCREG_NZCV },
573  { "daif", MISCREG_DAIF },
574  { "fpcr", MISCREG_FPCR },
575  { "fpsr", MISCREG_FPSR },
576  { "dspsr_el0", MISCREG_DSPSR_EL0 },
577  { "dlr_el0", MISCREG_DLR_EL0 },
578  { "spsr_el2", MISCREG_SPSR_EL2 },
579  { "elr_el2", MISCREG_ELR_EL2 },
580  { "sp_el1", MISCREG_SP_EL1 },
581  { "spsr_irq", MISCREG_SPSR_IRQ_AA64 },
582  { "spsr_abt", MISCREG_SPSR_ABT_AA64 },
583  { "spsr_und", MISCREG_SPSR_UND_AA64 },
584  { "spsr_fiq", MISCREG_SPSR_FIQ_AA64 },
585  { "spsr_el3", MISCREG_SPSR_EL3 },
586  { "elr_el3", MISCREG_ELR_EL3 },
587  { "sp_el2", MISCREG_SP_EL2 },
588  { "afsr0_el1", MISCREG_AFSR0_EL1 },
589  { "afsr1_el1", MISCREG_AFSR1_EL1 },
590  { "esr_el1", MISCREG_ESR_EL1 },
591  { "ifsr32_el2", MISCREG_IFSR32_EL2 },
592  { "afsr0_el2", MISCREG_AFSR0_EL2 },
593  { "afsr1_el2", MISCREG_AFSR1_EL2 },
594  { "esr_el2", MISCREG_ESR_EL2 },
595  { "fpexc32_el2", MISCREG_FPEXC32_EL2 },
596  { "afsr0_el3", MISCREG_AFSR0_EL3 },
597  { "afsr1_el3", MISCREG_AFSR1_EL3 },
598  { "esr_el3", MISCREG_ESR_EL3 },
599  { "far_el1", MISCREG_FAR_EL1 },
600  { "far_el2", MISCREG_FAR_EL2 },
601  { "hpfar_el2", MISCREG_HPFAR_EL2 },
602  { "far_el3", MISCREG_FAR_EL3 },
603  { "ic_ialluis", MISCREG_IC_IALLUIS },
604  { "par_el1", MISCREG_PAR_EL1 },
605  { "ic_iallu", MISCREG_IC_IALLU },
606  { "dc_ivac_xt", MISCREG_DC_IVAC_Xt },
607  { "dc_isw_xt", MISCREG_DC_ISW_Xt },
608  { "at_s1e1r_xt", MISCREG_AT_S1E1R_Xt },
609  { "at_s1e1w_xt", MISCREG_AT_S1E1W_Xt },
610  { "at_s1e0r_xt", MISCREG_AT_S1E0R_Xt },
611  { "at_s1e0w_xt", MISCREG_AT_S1E0W_Xt },
612  { "dc_csw_xt", MISCREG_DC_CSW_Xt },
613  { "dc_cisw_xt", MISCREG_DC_CISW_Xt },
614  { "dc_zva_xt", MISCREG_DC_ZVA_Xt },
615  { "ic_ivau_xt", MISCREG_IC_IVAU_Xt },
616  { "dc_cvac_xt", MISCREG_DC_CVAC_Xt },
617  { "dc_cvau_xt", MISCREG_DC_CVAU_Xt },
618  { "dc_civac_xt", MISCREG_DC_CIVAC_Xt },
619  { "at_s1e2r_xt", MISCREG_AT_S1E2R_Xt },
620  { "at_s1e2w_xt", MISCREG_AT_S1E2W_Xt },
621  { "at_s12e1r_xt", MISCREG_AT_S12E1R_Xt },
622  { "at_s12e1w_xt", MISCREG_AT_S12E1W_Xt },
623  { "at_s12e0r_xt", MISCREG_AT_S12E0R_Xt },
624  { "at_s12e0w_xt", MISCREG_AT_S12E0W_Xt },
625  { "at_s1e3r_xt", MISCREG_AT_S1E3R_Xt },
626  { "at_s1e3w_xt", MISCREG_AT_S1E3W_Xt },
627  { "tlbi_vmalle1is", MISCREG_TLBI_VMALLE1IS },
628  { "tlbi_vae1is_xt", MISCREG_TLBI_VAE1IS_Xt },
629  { "tlbi_aside1is_xt", MISCREG_TLBI_ASIDE1IS_Xt },
630  { "tlbi_vaae1is_xt", MISCREG_TLBI_VAAE1IS_Xt },
631  { "tlbi_vale1is_xt", MISCREG_TLBI_VALE1IS_Xt },
632  { "tlbi_vaale1is_xt", MISCREG_TLBI_VAALE1IS_Xt },
633  { "tlbi_vmalle1", MISCREG_TLBI_VMALLE1 },
634  { "tlbi_vae1_xt", MISCREG_TLBI_VAE1_Xt },
635  { "tlbi_aside1_xt", MISCREG_TLBI_ASIDE1_Xt },
636  { "tlbi_vaae1_xt", MISCREG_TLBI_VAAE1_Xt },
637  { "tlbi_vale1_xt", MISCREG_TLBI_VALE1_Xt },
638  { "tlbi_vaale1_xt", MISCREG_TLBI_VAALE1_Xt },
639  { "tlbi_ipas2e1is_xt", MISCREG_TLBI_IPAS2E1IS_Xt },
640  { "tlbi_ipas2le1is_xt", MISCREG_TLBI_IPAS2LE1IS_Xt },
641  { "tlbi_alle2is", MISCREG_TLBI_ALLE2IS },
642  { "tlbi_vae2is_xt", MISCREG_TLBI_VAE2IS_Xt },
643  { "tlbi_alle1is", MISCREG_TLBI_ALLE1IS },
644  { "tlbi_vale2is_xt", MISCREG_TLBI_VALE2IS_Xt },
645  { "tlbi_vmalls12e1is", MISCREG_TLBI_VMALLS12E1IS },
646  { "tlbi_ipas2e1_xt", MISCREG_TLBI_IPAS2E1_Xt },
647  { "tlbi_ipas2le1_xt", MISCREG_TLBI_IPAS2LE1_Xt },
648  { "tlbi_alle2", MISCREG_TLBI_ALLE2 },
649  { "tlbi_vae2_xt", MISCREG_TLBI_VAE2_Xt },
650  { "tlbi_alle1", MISCREG_TLBI_ALLE1 },
651  { "tlbi_vale2_xt", MISCREG_TLBI_VALE2_Xt },
652  { "tlbi_vmalls12e1", MISCREG_TLBI_VMALLS12E1 },
653  { "tlbi_alle3is", MISCREG_TLBI_ALLE3IS },
654  { "tlbi_vae3is_xt", MISCREG_TLBI_VAE3IS_Xt },
655  { "tlbi_vale3is_xt", MISCREG_TLBI_VALE3IS_Xt },
656  { "tlbi_alle3", MISCREG_TLBI_ALLE3 },
657  { "tlbi_vae3_xt", MISCREG_TLBI_VAE3_Xt },
658  { "tlbi_vale3_xt", MISCREG_TLBI_VALE3_Xt },
659  { "pmintenset_el1", MISCREG_PMINTENSET_EL1 },
660  { "pmintenclr_el1", MISCREG_PMINTENCLR_EL1 },
661  { "pmcr_el0", MISCREG_PMCR_EL0 },
662  { "pmcntenset_el0", MISCREG_PMCNTENSET_EL0 },
663  { "pmcntenclr_el0", MISCREG_PMCNTENCLR_EL0 },
664  { "pmovsclr_el0", MISCREG_PMOVSCLR_EL0 },
665  { "pmswinc_el0", MISCREG_PMSWINC_EL0 },
666  { "pmselr_el0", MISCREG_PMSELR_EL0 },
667  { "pmceid0_el0", MISCREG_PMCEID0_EL0 },
668  { "pmceid1_el0", MISCREG_PMCEID1_EL0 },
669  { "pmccntr_el0", MISCREG_PMCCNTR_EL0 },
670  { "pmxevtyper_el0", MISCREG_PMXEVTYPER_EL0 },
671  { "pmccfiltr_el0", MISCREG_PMCCFILTR_EL0 },
672  { "pmxevcntr_el0", MISCREG_PMXEVCNTR_EL0 },
673  { "pmuserenr_el0", MISCREG_PMUSERENR_EL0 },
674  { "pmovsset_el0", MISCREG_PMOVSSET_EL0 },
675  { "mair_el1", MISCREG_MAIR_EL1 },
676  { "amair_el1", MISCREG_AMAIR_EL1 },
677  { "mair_el2", MISCREG_MAIR_EL2 },
678  { "amair_el2", MISCREG_AMAIR_EL2 },
679  { "mair_el3", MISCREG_MAIR_EL3 },
680  { "amair_el3", MISCREG_AMAIR_EL3 },
681  { "l2ctlr_el1", MISCREG_L2CTLR_EL1 },
682  { "l2ectlr_el1", MISCREG_L2ECTLR_EL1 },
683  { "vbar_el1", MISCREG_VBAR_EL1 },
684  { "rvbar_el1", MISCREG_RVBAR_EL1 },
685  { "isr_el1", MISCREG_ISR_EL1 },
686  { "vbar_el2", MISCREG_VBAR_EL2 },
687  { "rvbar_el2", MISCREG_RVBAR_EL2 },
688  { "vbar_el3", MISCREG_VBAR_EL3 },
689  { "rvbar_el3", MISCREG_RVBAR_EL3 },
690  { "rmr_el3", MISCREG_RMR_EL3 },
691  { "contextidr_el1", MISCREG_CONTEXTIDR_EL1 },
692  { "contextidr_el2", MISCREG_CONTEXTIDR_EL2 },
693  { "tpidr_el1", MISCREG_TPIDR_EL1 },
694  { "tpidr_el0", MISCREG_TPIDR_EL0 },
695  { "tpidrro_el0", MISCREG_TPIDRRO_EL0 },
696  { "tpidr_el2", MISCREG_TPIDR_EL2 },
697  { "tpidr_el3", MISCREG_TPIDR_EL3 },
698  { "cntkctl_el1", MISCREG_CNTKCTL_EL1 },
699  { "cntfrq_el0", MISCREG_CNTFRQ_EL0 },
700  { "cntpct_el0", MISCREG_CNTPCT_EL0 },
701  { "cntvct_el0", MISCREG_CNTVCT_EL0 },
702  { "cntp_tval_el0", MISCREG_CNTP_TVAL_EL0 },
703  { "cntp_ctl_el0", MISCREG_CNTP_CTL_EL0 },
704  { "cntp_cval_el0", MISCREG_CNTP_CVAL_EL0 },
705  { "cntv_tval_el0", MISCREG_CNTV_TVAL_EL0 },
706  { "cntv_ctl_el0", MISCREG_CNTV_CTL_EL0 },
707  { "cntv_cval_el0", MISCREG_CNTV_CVAL_EL0 },
708  { "pmevcntr0_el0", MISCREG_PMEVCNTR0_EL0 },
709  { "pmevcntr1_el0", MISCREG_PMEVCNTR1_EL0 },
710  { "pmevcntr2_el0", MISCREG_PMEVCNTR2_EL0 },
711  { "pmevcntr3_el0", MISCREG_PMEVCNTR3_EL0 },
712  { "pmevcntr4_el0", MISCREG_PMEVCNTR4_EL0 },
713  { "pmevcntr5_el0", MISCREG_PMEVCNTR5_EL0 },
714  { "pmevtyper0_el0", MISCREG_PMEVTYPER0_EL0 },
715  { "pmevtyper1_el0", MISCREG_PMEVTYPER1_EL0 },
716  { "pmevtyper2_el0", MISCREG_PMEVTYPER2_EL0 },
717  { "pmevtyper3_el0", MISCREG_PMEVTYPER3_EL0 },
718  { "pmevtyper4_el0", MISCREG_PMEVTYPER4_EL0 },
719  { "pmevtyper5_el0", MISCREG_PMEVTYPER5_EL0 },
720  { "cntvoff_el2", MISCREG_CNTVOFF_EL2 },
721  { "cnthctl_el2", MISCREG_CNTHCTL_EL2 },
722  { "cnthp_tval_el2", MISCREG_CNTHP_TVAL_EL2 },
723  { "cnthp_ctl_el2", MISCREG_CNTHP_CTL_EL2 },
724  { "cnthp_cval_el2", MISCREG_CNTHP_CVAL_EL2 },
725  { "cntps_tval_el1", MISCREG_CNTPS_TVAL_EL1 },
726  { "cntps_ctl_el1", MISCREG_CNTPS_CTL_EL1 },
727  { "cntps_cval_el1", MISCREG_CNTPS_CVAL_EL1 },
728  { "il1data0_el1", MISCREG_IL1DATA0_EL1 },
729  { "il1data1_el1", MISCREG_IL1DATA1_EL1 },
730  { "il1data2_el1", MISCREG_IL1DATA2_EL1 },
731  { "il1data3_el1", MISCREG_IL1DATA3_EL1 },
732  { "dl1data0_el1", MISCREG_DL1DATA0_EL1 },
733  { "dl1data1_el1", MISCREG_DL1DATA1_EL1 },
734  { "dl1data2_el1", MISCREG_DL1DATA2_EL1 },
735  { "dl1data3_el1", MISCREG_DL1DATA3_EL1 },
736  { "dl1data4_el1", MISCREG_DL1DATA4_EL1 },
737  { "l2actlr_el1", MISCREG_L2ACTLR_EL1 },
738  { "cpuactlr_el1", MISCREG_CPUACTLR_EL1 },
739  { "cpuectlr_el1", MISCREG_CPUECTLR_EL1 },
740  { "cpumerrsr_el1", MISCREG_CPUMERRSR_EL1 },
741  { "l2merrsr_el1", MISCREG_L2MERRSR_EL1 },
742  { "cbar_el1", MISCREG_CBAR_EL1 },
743 };
744 
745 void
746 TarmacParserRecord::TarmacParserRecordEvent::process()
747 {
748  std::ostream &outs = trace::output();
749 
750  std::list<ParserRegEntry>::iterator it = destRegRecords.begin(),
751  end = destRegRecords.end();
752 
753  std::vector<uint64_t> values;
754 
755  for (; it != end; ++it) {
756  values.clear();
757  switch (it->type) {
758  case REG_R:
759  case REG_X:
760  values.push_back(thread->getReg(intRegClass[it->index]));
761  break;
762  case REG_S:
763  if (instRecord.isetstate == ISET_A64) {
765  thread->getReg(vecRegClass[it->index], &vc);
766  auto vv = vc.as<uint32_t>();
767  values.push_back(vv[0]);
768  } else {
769  const VecElem elem = thread->getReg(vecElemClass[it->index]);
770  values.push_back(elem);
771  }
772  break;
773  case REG_D:
774  if (instRecord.isetstate == ISET_A64) {
776  thread->getReg(vecRegClass[it->index], &vc);
777  auto vv = vc.as<uint64_t>();
778  values.push_back(vv[0]);
779  } else {
780  const VecElem w0 = thread->getReg(vecElemClass[it->index]);
781  const VecElem w1 = thread->getReg(vecElemClass[it->index + 1]);
782 
783  values.push_back((uint64_t)(w1) << 32 | w0);
784  }
785  break;
786  case REG_P:
787  {
789  thread->getReg(vecPredRegClass[it->index], &pc);
790  auto pv = pc.as<uint8_t>();
791  uint64_t p = 0;
792  for (int i = maxVectorLength * 8; i > 0; ) {
793  p = (p << 1) | pv[--i];
794  }
795  values.push_back(p);
796  }
797  break;
798  case REG_Q:
799  if (instRecord.isetstate == ISET_A64) {
801  thread->getReg(vecRegClass[it->index], &vc);
802  auto vv = vc.as<uint64_t>();
803  values.push_back(vv[0]);
804  values.push_back(vv[1]);
805  } else {
806  const VecElem w0 = thread->getReg(vecElemClass[it->index]);
807  const VecElem w1 = thread->getReg(vecElemClass[it->index + 1]);
808  const VecElem w2 = thread->getReg(vecElemClass[it->index + 2]);
809  const VecElem w3 = thread->getReg(vecElemClass[it->index + 3]);
810 
811  values.push_back((uint64_t)(w1) << 32 | w0);
812  values.push_back((uint64_t)(w3) << 32 | w2);
813  }
814  break;
815  case REG_Z:
816  {
817  int8_t i = maxVectorLength;
819  thread->getReg(vecRegClass[it->index], &vc);
820  auto vv = vc.as<uint64_t>();
821  while (i > 0) {
822  values.push_back(vv[--i]);
823  }
824  }
825  break;
826  case REG_MISC:
827  if (it->index == MISCREG_CPSR) {
828  // Read condition codes from aliased integer regs
829  CPSR cpsr = thread->readMiscRegNoEffect(it->index);
830  cpsr.nz = thread->getReg(cc_reg::Nz);
831  cpsr.c = thread->getReg(cc_reg::C);
832  cpsr.v = thread->getReg(cc_reg::V);
833  cpsr.ge = thread->getReg(cc_reg::Ge);
834  values.push_back(cpsr);
835  } else if (it->index == MISCREG_NZCV) {
836  CPSR cpsr = 0;
837  cpsr.nz = thread->getReg(cc_reg::Nz);
838  cpsr.c = thread->getReg(cc_reg::C);
839  cpsr.v = thread->getReg(cc_reg::V);
840  values.push_back(cpsr);
841  } else if (it->index == MISCREG_FPCR) {
842  // Read FPSCR and extract FPCR value
843  FPSCR fpscr = thread->readMiscRegNoEffect(MISCREG_FPSCR);
844  const uint32_t ones = (uint32_t)(-1);
845  FPSCR fpcrMask = 0;
846  fpcrMask.ioe = ones;
847  fpcrMask.dze = ones;
848  fpcrMask.ofe = ones;
849  fpcrMask.ufe = ones;
850  fpcrMask.ixe = ones;
851  fpcrMask.ide = ones;
852  fpcrMask.len = ones;
853  fpcrMask.stride = ones;
854  fpcrMask.rMode = ones;
855  fpcrMask.fz = ones;
856  fpcrMask.dn = ones;
857  fpcrMask.ahp = ones;
858  values.push_back(fpscr & fpcrMask);
859  } else if (it->index == MISCREG_FPSR) {
860  // Read FPSCR and extract FPSR value
861  FPSCR fpscr = thread->readMiscRegNoEffect(MISCREG_FPSCR);
862  const uint32_t ones = (uint32_t)(-1);
863  FPSCR fpsrMask = 0;
864  fpsrMask.ioc = ones;
865  fpsrMask.dzc = ones;
866  fpsrMask.ofc = ones;
867  fpsrMask.ufc = ones;
868  fpsrMask.ixc = ones;
869  fpsrMask.idc = ones;
870  fpsrMask.qc = ones;
871  fpsrMask.v = ones;
872  fpsrMask.c = ones;
873  fpsrMask.z = ones;
874  fpsrMask.n = ones;
875  values.push_back(fpscr & fpsrMask);
876  } else {
877  values.push_back(thread->readMiscRegNoEffect(it->index));
878  }
879  break;
880  default:
881  panic("Unknown TARMAC trace record type!");
882  }
883 
884  bool same = true;
885  if (values.size() != it->values.size()) same = false;
886 
887  uint32_t size = values.size();
888  if (size > it->values.size())
889  size = it->values.size();
890 
891  if (same) {
892  for (int i = 0; i < size; ++i) {
893  if (values[i] != it->values[i]) {
894  same = false;
895  break;
896  }
897  }
898  }
899 
900  if (!same) {
901  if (!mismatch) {
902  TarmacParserRecord::printMismatchHeader(inst, *pc);
903  mismatch = true;
904  }
905  outs << "diff> [" << it->repr << "] gem5: 0x" << std::hex;
906  for (auto v : values)
907  outs << std::setw(16) << std::setfill('0') << v;
908 
909  outs << ", TARMAC: 0x" << std::hex;
910  for (auto v : it->values)
911  outs << std::setw(16) << std::setfill('0') << v;
912  outs << std::endl;
913  }
914  }
915  destRegRecords.clear();
916 
917  if (mismatchOnPcOrOpcode && (parent.exitOnDiff ||
918  parent.exitOnInsnDiff))
919  exitSimLoop("a mismatch with the TARMAC trace has been detected "
920  "on PC or opcode", 1);
921  if (mismatch && parent.exitOnDiff)
922  exitSimLoop("a mismatch with the TARMAC trace has been detected "
923  "on data value", 1);
924 }
925 
926 const char *
927 TarmacParserRecord::TarmacParserRecordEvent::description() const
928 {
929  return "TARMAC parser record event";
930 }
931 
932 
933 void
934 TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst,
935  const PCStateBase &pc)
936 {
937  std::ostream &outs = trace::output();
938  outs << "\nMismatch between gem5 and TARMAC trace @ " << std::dec
939  << curTick() << " ticks\n"
940  << "[seq_num: " << std::dec << instRecord.seq_num
941  << ", opcode: 0x" << std::hex << (staticInst->getEMI() & 0xffffffff)
942  << ", PC: 0x" << pc.instAddr()
943  << ", disasm: " << staticInst->disassemble(pc.instAddr()) << "]"
944  << std::endl;
945 }
946 
947 TarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread,
948  const StaticInstPtr _staticInst,
949  const PCStateBase &_pc,
950  TarmacParser& _parent,
951  const StaticInstPtr _macroStaticInst)
952  : TarmacBaseRecord(_when, _thread, _staticInst,
953  _pc, _macroStaticInst),
954  parsingStarted(false), mismatch(false),
955  mismatchOnPcOrOpcode(false), parent(_parent)
956 {
957  memReq = std::make_shared<Request>();
958  if (maxVectorLength == 0) {
959  maxVectorLength = ArmStaticInst::getCurSveVecLen<uint64_t>(_thread);
960  }
961 }
962 
963 void
965 {
966  std::ostream &outs = trace::output();
967 
968  uint64_t written_data = 0;
969  unsigned mem_flags = 3 | ArmISA::MMU::AllowUnaligned;
970 
971  ISetState isetstate;
972 
974 
976  // A microop faulted and it was not the last microop -> advance
977  // TARMAC trace to next instruction
978  advanceTrace();
979  }
980 
981  parent.macroopInProgress = false;
982 
983  auto arm_inst = static_cast<const ArmStaticInst*>(
984  staticInst.get()
985  );
986 
987  while (advanceTrace()) {
988  switch (currRecordType) {
989 
990  case TARMAC_INST:
991  parsingStarted = true;
992  if (pc->instAddr() != instRecord.addr) {
993  if (!mismatch)
995  outs << "diff> [PC] gem5: 0x" << std::hex << pc->instAddr()
996  << ", TARMAC: 0x" << instRecord.addr << std::endl;
997  mismatch = true;
998  mismatchOnPcOrOpcode = true;
999  }
1000 
1001  if (arm_inst->encoding() != instRecord.opcode) {
1002  if (!mismatch)
1004  outs << "diff> [opcode] gem5: 0x" << std::hex
1005  << arm_inst->encoding()
1006  << ", TARMAC: 0x" << instRecord.opcode << std::endl;
1007  mismatch = true;
1008  mismatchOnPcOrOpcode = true;
1009  }
1010 
1011  // Set the Instruction set state.
1012  isetstate = pcToISetState(*pc);
1013 
1014  if (instRecord.isetstate != isetstate &&
1015  isetstate != ISET_UNSUPPORTED) {
1016  if (!mismatch)
1018  outs << "diff> [iset_state] gem5: "
1019  << iSetStateToStr(isetstate)
1020  << ", TARMAC: "
1022  mismatch = true;
1023  }
1024 
1025  // TODO(Giacomo): add support for predicate and mode checking
1026  break;
1027 
1028  case TARMAC_REG:
1029  destRegRecords.push_back(regRecord);
1030  break;
1031 
1032  case TARMAC_MEM:
1033  if (!readMemNoEffect(memRecord.addr, (uint8_t*) &written_data,
1034  memRecord.size, mem_flags))
1035  break;
1036  if (written_data != memRecord.data) {
1037  if (!mismatch)
1039  outs << "diff> [mem(0x" << std::hex << memRecord.addr
1040  << ")] gem5: 0x" << written_data
1041  << ", TARMAC: 0x" << memRecord.data
1042  << std::endl;
1043  }
1044  break;
1045 
1046  case TARMAC_UNSUPPORTED:
1047  break;
1048 
1049  default:
1050  panic("Unknown TARMAC trace record type!");
1051  }
1052  }
1053  // We are done with the current instruction, i.e. all the corresponding
1054  // entries in the TARMAC trace have been parsed
1055  if (destRegRecords.size()) {
1059  mainEventQueue[0]->schedule(event, curTick());
1060  } else if (mismatchOnPcOrOpcode && (parent.exitOnDiff ||
1062  exitSimLoop("a mismatch with the TARMAC trace has been detected "
1063  "on PC or opcode", 1);
1064  }
1065  } else {
1066  parent.macroopInProgress = true;
1067  }
1068 }
1069 
1070 bool
1072 {
1073  std::ifstream& trace = parent.trace;
1074  trace >> std::hex; // All integer values are in hex base
1075 
1076  if (buf[0] != 'I') {
1077  trace >> buf;
1078  if (trace.eof())
1079  return false;
1080  trace >> buf >> buf;
1081  if (parent.cpuId) {
1082  assert((buf[0] == 'c') && (buf[1] == 'p') && (buf[2] == 'u'));
1083  trace >> buf;
1084  }
1085  }
1086 
1087  if (trace.eof())
1088  return false;
1089 
1090  if (buf[0] == 'I') {
1091  // Instruction trace record
1092  if (parsingStarted)
1093  return false;
1095  instRecord.taken = (buf[1] == 'T');
1096  trace >> buf;
1097  instRecord.seq_num = atoi(&buf[1]);
1098  trace >> instRecord.addr;
1099  char c = trace.peek();
1100  if (c == ':') {
1101  // Skip phys. address and _S/_NS suffix
1102  trace >> c >> buf;
1103  }
1104  trace >> instRecord.opcode;
1105  trace >> buf;
1106  switch (buf[0]) {
1107  case 'A':
1109  break;
1110  case 'T':
1112  break;
1113  case 'O':
1115  break;
1116  default:
1117  warn("Invalid TARMAC trace record (seq_num: %lld)",
1121  break;
1122  }
1123  trace.ignore(MaxLineLength, '\n');
1124  buf[0] = 0;
1125  } else if (buf[0] == 'R') {
1126  // Register trace record
1128  regRecord.values.clear();
1129  trace >> buf;
1130  strcpy(regRecord.repr, buf);
1131  if (std::tolower(buf[0]) == 'r' && isdigit(buf[1])) {
1132  // R register
1133  regRecord.type = REG_R;
1134  int base_index = atoi(&buf[1]);
1135  char* pch = strchr(buf, '_');
1136  if (pch == NULL) {
1137  regRecord.index = int_reg::usr(base_index);
1138  } else {
1139  ++pch;
1140  if (strncmp(pch, "usr", 3) == 0)
1141  regRecord.index = int_reg::usr(base_index);
1142  else if (strncmp(pch, "fiq", 3) == 0)
1143  regRecord.index = int_reg::fiq(base_index);
1144  else if (strncmp(pch, "irq", 3) == 0)
1145  regRecord.index = int_reg::irq(base_index);
1146  else if (strncmp(pch, "svc", 3) == 0)
1147  regRecord.index = int_reg::svc(base_index);
1148  else if (strncmp(pch, "mon", 3) == 0)
1149  regRecord.index = int_reg::mon(base_index);
1150  else if (strncmp(pch, "abt", 3) == 0)
1151  regRecord.index = int_reg::abt(base_index);
1152  else if (strncmp(pch, "und", 3) == 0)
1153  regRecord.index = int_reg::und(base_index);
1154  else if (strncmp(pch, "hyp", 3) == 0)
1155  regRecord.index = int_reg::hyp(base_index);
1156  }
1157  } else if (std::tolower(buf[0]) == 'x' && isdigit(buf[1])) {
1158  // X register (A64)
1159  regRecord.type = REG_X;
1160  regRecord.index = atoi(&buf[1]);
1161  } else if (std::tolower(buf[0]) == 's' && isdigit(buf[1])) {
1162  // S register
1163  regRecord.type = REG_S;
1164  regRecord.index = atoi(&buf[1]);
1165  } else if (std::tolower(buf[0]) == 'd' && isdigit(buf[1])) {
1166  // D register
1167  regRecord.type = REG_D;
1168  regRecord.index = atoi(&buf[1]);
1169  } else if (std::tolower(buf[0]) == 'q' && isdigit(buf[1])) {
1170  // Q register
1171  regRecord.type = REG_Q;
1172  regRecord.index = atoi(&buf[1]);
1173  } else if (std::tolower(buf[0]) == 'z' && isdigit(buf[1])) {
1174  // Z (SVE vector) register
1175  regRecord.type = REG_Z;
1176  regRecord.index = atoi(&buf[1]);
1177  } else if (std::tolower(buf[0]) == 'p' && isdigit(buf[1])) {
1178  // P (SVE predicate) register
1179  regRecord.type = REG_P;
1180  regRecord.index = atoi(&buf[1]);
1181  } else if (strncmp(buf, "SP_EL", 5) == 0) {
1182  // A64 stack pointer
1183  regRecord.type = REG_X;
1184  regRecord.index = int_reg::Sp0 + atoi(&buf[5]);
1185  } else if (miscRegMap.count(buf)) {
1186  // Misc. register
1189  } else {
1190  // Try match with upper case name (misc. register)
1191  std::string reg_name = buf;
1192  std::transform(reg_name.begin(), reg_name.end(), reg_name.begin(),
1193  ::tolower);
1194  if (miscRegMap.count(reg_name.c_str())) {
1196  regRecord.index = miscRegMap[reg_name.c_str()];
1197  } else {
1198  warn("Unknown register in TARMAC trace (%s).\n", buf);
1200  trace.ignore(MaxLineLength, '\n');
1201  buf[0] = 0;
1202  return true;
1203  }
1204  }
1205  if (regRecord.type == REG_Q) {
1206  trace.ignore();
1207  trace.get(buf, 17);
1208  uint64_t hi = strtoull(buf, NULL, 16);
1209  trace.get(buf, 17);
1210  uint64_t lo = strtoull(buf, NULL, 16);
1211  regRecord.values.push_back(lo);
1212  regRecord.values.push_back(hi);
1213  } else if (regRecord.type == REG_Z) {
1215  for (uint8_t i = 0; i < maxVectorLength; ++i) {
1216  uint64_t v;
1217  trace >> v;
1218  char c;
1219  trace >> c;
1220  assert(c == '_');
1221 
1222  uint64_t lsw = 0;
1223  trace >> lsw;
1224  v = (v << 32) | lsw;
1225  if (i < maxVectorLength - 1) trace >> c;
1226  regRecord.values[i] = v;
1227  }
1228  } else {
1229  // REG_P values are also parsed here
1230  uint64_t v;
1231  trace >> v;
1232  char c = trace.peek();
1233  if ((c == ':') || (c == '_')) {
1234  // 64-bit value with : or _ in the middle
1235  uint64_t lsw = 0;
1236  trace >> c >> lsw;
1237  v = (v << 32) | lsw;
1238  }
1239  regRecord.values.push_back(v);
1240  }
1241  trace.ignore(MaxLineLength, '\n');
1242  buf[0] = 0;
1243  } else if (buf[0] == 'M' && (parent.memWrCheck && buf[1] == 'W')) {
1245  memRecord.size = atoi(&buf[2]);
1246  trace >> memRecord.addr;
1247  char c = trace.peek();
1248  if (c == ':') {
1249  // Skip phys. address and _S/_NS suffix
1250  trace >> c >> buf;
1251  }
1252  uint64_t data = 0;
1253  trace >> data;
1254  c = trace.peek();
1255  if (c == '_') {
1256  // 64-bit value with _ in the middle
1257  uint64_t lsw = 0;
1258  trace >> c >> lsw;
1259  data = (data << 32) | lsw;
1260  }
1261  memRecord.data = data;
1262  trace.ignore(MaxLineLength, '\n');
1263  buf[0] = 0;
1264  } else {
1266  trace.ignore(MaxLineLength, '\n');
1267  buf[0] = 0;
1268  }
1269 
1270  return true;
1271 }
1272 
1273 bool
1275  unsigned flags)
1276 {
1277  const RequestPtr &req = memReq;
1278  auto mmu = static_cast<MMU*>(thread->getMMUPtr());
1279 
1280  req->setVirt(addr, size, flags, thread->pcState().instAddr(),
1282 
1283  // Translate to physical address
1284  Fault fault = mmu->translateAtomic(req, thread, BaseMMU::Read);
1285 
1286  // Ignore read if the address falls into the ignored range
1288  return false;
1289 
1290  // Now do the access
1291  if (fault == NoFault &&
1292  !req->getFlags().isSet(Request::NO_ACCESS)) {
1293  if (req->isLLSC() || req->isLocalAccess())
1294  // LLSCs and local accesses are ignored
1295  return false;
1296  // the translating proxy will perform the virtual to physical
1297  // translation again
1298  TranslatingPortProxy fs_proxy(thread);
1299  SETranslatingPortProxy se_proxy(thread);
1300  PortProxy &virt_proxy = FullSystem ? fs_proxy : se_proxy;
1301 
1302  virt_proxy.readBlob(addr, data, size);
1303  } else {
1304  return false;
1305  }
1306 
1307  if (fault != NoFault) {
1308  return false;
1309  }
1310 
1311  return true;
1312 }
1313 
1314 void
1316 {
1318  Addr pc;
1319  int saved_offset;
1320 
1321  trace >> std::hex; // All integer values are in hex base
1322 
1323  while (true) {
1324  saved_offset = trace.tellg();
1325  trace >> buf >> buf >> buf;
1326  if (cpuId)
1327  trace >> buf;
1328  if (buf[0] == 'I') {
1329  trace >> buf >> pc;
1330  if (pc == startPc) {
1331  // Set file pointer to the beginning of this line
1332  trace.seekg(saved_offset, std::ios::beg);
1333  return;
1334  } else {
1336  }
1337  } else {
1339  }
1340  if (trace.eof())
1341  panic("End of TARMAC trace reached before start PC\n");
1342  }
1343 }
1344 
1345 const char*
1347 {
1348  switch (isetstate) {
1349  case ISET_ARM:
1350  return "ARM (A32)";
1351  case ISET_THUMB:
1352  return "Thumb (A32)";
1353  case ISET_A64:
1354  return "A64";
1355  default:
1356  return "UNSUPPORTED";
1357  }
1358 }
1359 
1360 } // namespace trace
1361 } // namespace gem5
const char data[]
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) override
Definition: mmu.hh:245
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:87
void readBlob(Addr addr, void *p, int size) const
Higher level interfaces based on the above.
Definition: port_proxy.hh:182
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:227
@ NO_ACCESS
The request should not cause a memory access.
Definition: request.hh:146
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:279
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:60
virtual uint64_t getEMI() const
Definition: static_inst.hh:236
bool isLastMicroop() const
Definition: static_inst.hh:188
bool isMicroop() const
Definition: static_inst.hh:186
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual const PCStateBase & pcState() const =0
virtual BaseMMU * getMMUPtr()=0
This proxy attempts to translate virtual addresses using the TLBs.
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:124
VecElem * as()
View interposers.
Definition: vec_reg.hh:189
Addr addr
The address that was accessed.
Definition: insttracer.hh:85
StaticInstPtr staticInst
Definition: insttracer.hh:70
ThreadContext * thread
Definition: insttracer.hh:67
unsigned flags
The flags that were assigned to the request.
Definition: insttracer.hh:87
std::unique_ptr< PCStateBase > pc
Definition: insttracer.hh:71
union gem5::trace::InstRecord::Data data
Addr size
The size of the memory request.
Definition: insttracer.hh:86
ISetState
ARM instruction set state.
Definition: tarmac_base.hh:78
static ISetState pcToISetState(const PCStateBase &pc)
Returns the Instruction Set State according to the current PCState.
Definition: tarmac_base.cc:103
bool advanceTrace()
Advances the TARMAC trace up to the next instruction, register, or memory access record.
const char * iSetStateToStr(ISetState isetstate) const
Returns the string representation of an instruction set state.
static ParserInstEntry instRecord
Buffer for instruction trace records.
static std::list< ParserRegEntry > destRegRecords
List of records of destination registers.
bool mismatchOnPcOrOpcode
True if a mismatch has been detected for this instruction on PC or opcode.
static char buf[MaxLineLength]
Buffer used for trace file parsing.
static ParserRegEntry regRecord
Buffer for register trace records.
static void printMismatchHeader(const StaticInstPtr inst, const PCStateBase &pc)
Print a mismatch header containing the instruction fields as reported by gem5.
static TarmacRecordType currRecordType
Type of last parsed record.
bool mismatch
True if a mismatch has been detected for this instruction.
RequestPtr memReq
Request for memory write checks.
bool parsingStarted
True if a TARMAC instruction record has already been parsed for this instruction.
bool readMemNoEffect(Addr addr, uint8_t *data, unsigned size, unsigned flags)
Performs a memory access to read the value written by a previous write.
static ParserMemEntry memRecord
Buffer for memory access trace records (stores only).
Tarmac Parser: this tracer parses an existing Tarmac trace and it diffs it with gem5 simulation statu...
std::ifstream trace
TARMAC trace file.
bool cpuId
If true, the trace format includes the CPU id.
void advanceTraceToStartPc()
Helper function to advance the trace up to startPc.
bool exitOnDiff
If true, the simulation is stopped as the first mismatch is detected.
bool macroopInProgress
True if a macroop is currently in progress.
bool exitOnInsnDiff
If true, the simulation is stopped as the first mismatch is detected on PC or opcode.
AddrRange ignoredAddrRange
Ignored addresses (ignored if empty).
bool memWrCheck
If true, memory write accesses are checked.
Addr startPc
Tracing starts when the PC gets this value for the first time (ignored if 0x0).
STL list class.
Definition: stl.hh:51
bool contains(const Addr &a) const
Determine if the range contains an address.
Definition: addr_range.hh:471
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
uint8_t flags
Definition: helpers.cc:66
#define warn(...)
Definition: logging.hh:246
constexpr RegId V
Definition: cc.hh:75
constexpr RegId C
Definition: cc.hh:74
constexpr RegId Ge
Definition: cc.hh:76
constexpr RegId Nz
Definition: cc.hh:73
static const RegId & hyp(unsigned index)
Definition: int.hh:473
static const RegId & und(unsigned index)
Definition: int.hh:529
constexpr RegId Sp0
Definition: int.hh:233
static const RegId & abt(unsigned index)
Definition: int.hh:515
static const RegId & svc(unsigned index)
Definition: int.hh:487
static const RegId & mon(unsigned index)
Definition: int.hh:501
Bitfield< 28 > v
Definition: misc_types.hh:54
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:71
Bitfield< 7 > i
Definition: misc_types.hh:67
Bitfield< 19, 16 > lo
Definition: misc_types.hh:141
constexpr RegClass vecElemClass
Definition: vec.hh:105
Bitfield< 2 > fiq
Definition: misc_types.hh:336
constexpr RegClass intRegClass
Definition: int.hh:173
constexpr RegClass vecPredRegClass
Definition: vec.hh:109
Bitfield< 1 > irq
Definition: misc_types.hh:337
@ MISCREG_PMXEVTYPER_EL0
Definition: misc.hh:726
@ MISCREG_AMAIR_EL3
Definition: misc.hh:738
@ MISCREG_DBGWVR1_EL1
Definition: misc.hh:496
@ MISCREG_DBGDRAR
Definition: misc.hh:175
@ MISCREG_NSACR
Definition: misc.hh:250
@ MISCREG_DL1DATA1
Definition: misc.hh:445
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:566
@ MISCREG_DBGWCR5
Definition: misc.hh:164
@ MISCREG_CSSELR_NS
Definition: misc.hh:236
@ MISCREG_HSTR_EL2
Definition: misc.hh:594
@ MISCREG_DBGWVR13_EL1
Definition: misc.hh:508
@ MISCREG_PMUSERENR
Definition: misc.hh:368
@ MISCREG_DBGBCR15
Definition: misc.hh:142
@ MISCREG_DBGOSLSR
Definition: misc.hh:193
@ MISCREG_DBGDTRRXext
Definition: misc.hh:107
@ MISCREG_ID_MMFR2_EL1
Definition: misc.hh:553
@ MISCREG_DCCISW
Definition: misc.hh:323
@ MISCREG_DACR_S
Definition: misc.hh:272
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:764
@ MISCREG_DBGWCR8
Definition: misc.hh:167
@ MISCREG_HCR
Definition: misc.hh:253
@ MISCREG_NMRR_NS
Definition: misc.hh:381
@ MISCREG_TLBI_ALLE3
Definition: misc.hh:712
@ MISCREG_TLBI_ALLE1IS
Definition: misc.hh:699
@ MISCREG_DBGWVR14
Definition: misc.hh:157
@ MISCREG_HDFAR
Definition: misc.hh:294
@ MISCREG_MPIDR_EL1
Definition: misc.hh:545
@ MISCREG_DFSR_S
Definition: misc.hh:275
@ MISCREG_IL1DATA1
Definition: misc.hh:441
@ MISCREG_DBGWVR10_EL1
Definition: misc.hh:505
@ MISCREG_DL1DATA0
Definition: misc.hh:444
@ MISCREG_CPUECTLR_EL1
Definition: misc.hh:818
@ MISCREG_ATS1HR
Definition: misc.hh:324
@ MISCREG_SCTLR_EL2
Definition: misc.hh:589
@ MISCREG_PMSELR_EL0
Definition: misc.hh:722
@ MISCREG_ID_DFR0_EL1
Definition: misc.hh:549
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: misc.hh:695
@ MISCREG_CP15ISB
Definition: misc.hh:304
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:761
@ MISCREG_DFAR_NS
Definition: misc.hh:289
@ MISCREG_DBGBXVR8
Definition: misc.hh:184
@ MISCREG_TLBIMVALIS
Definition: misc.hh:330
@ MISCREG_PMOVSSET
Definition: misc.hh:371
@ MISCREG_DBGWCR1
Definition: misc.hh:160
@ MISCREG_SPSEL
Definition: misc.hh:622
@ MISCREG_TCR_EL2
Definition: misc.hh:609
@ MISCREG_AT_S1E1W_Xt
Definition: misc.hh:665
@ MISCREG_ID_ISAR0_EL1
Definition: misc.hh:556
@ MISCREG_DBGWCR5_EL1
Definition: misc.hh:516
@ MISCREG_DBGWVR2
Definition: misc.hh:145
@ MISCREG_DBGDSCRint
Definition: misc.hh:101
@ MISCREG_IL1DATA0_EL1
Definition: misc.hh:807
@ MISCREG_MIDR_EL1
Definition: misc.hh:544
@ MISCREG_SDER
Definition: misc.hh:249
@ MISCREG_DBGWCR12_EL1
Definition: misc.hh:523
@ MISCREG_OSDLR_EL1
Definition: misc.hh:535
@ MISCREG_DL1DATA3
Definition: misc.hh:447
@ MISCREG_HTPIDR
Definition: misc.hh:416
@ MISCREG_DBGBXVR15
Definition: misc.hh:191
@ MISCREG_TLBIMVAALIS
Definition: misc.hh:331
@ MISCREG_DBGDEVID0
Definition: misc.hh:202
@ MISCREG_CNTFRQ
Definition: misc.hh:418
@ MISCREG_DBGDSAR
Definition: misc.hh:196
@ MISCREG_CPUMERRSR
Definition: misc.hh:454
@ MISCREG_DBGBVR5_EL1
Definition: misc.hh:468
@ MISCREG_MAIR_EL1
Definition: misc.hh:731
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: misc.hh:702
@ MISCREG_DBGBCR2_EL1
Definition: misc.hh:481
@ MISCREG_ID_ISAR2_EL1
Definition: misc.hh:558
@ MISCREG_TLBIMVAAL
Definition: misc.hh:343
@ MISCREG_DBGBVR1_EL1
Definition: misc.hh:464
@ MISCREG_PAR_NS
Definition: misc.hh:300
@ MISCREG_HAMAIR1
Definition: misc.hh:395
@ MISCREG_PMXEVCNTR_EL0
Definition: misc.hh:728
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:750
@ MISCREG_CNTV_TVAL
Definition: misc.hh:432
@ MISCREG_VBAR_EL3
Definition: misc.hh:747
@ MISCREG_AIFSR_NS
Definition: misc.hh:283
@ MISCREG_DBGWCR10
Definition: misc.hh:169
@ MISCREG_DBGBXVR9
Definition: misc.hh:185
@ MISCREG_CNTPS_TVAL_EL1
Definition: misc.hh:777
@ MISCREG_HCPTR
Definition: misc.hh:256
@ MISCREG_SPSR_EL2
Definition: misc.hh:630
@ MISCREG_DBGWFAR
Definition: misc.hh:105
@ MISCREG_TLBI_ALLE1
Definition: misc.hh:706
@ MISCREG_FCSEIDR
Definition: misc.hh:403
@ MISCREG_DBGWVR7
Definition: misc.hh:150
@ MISCREG_ID_MMFR1
Definition: misc.hh:221
@ MISCREG_AT_S1E2W_Xt
Definition: misc.hh:676
@ MISCREG_PMEVTYPER1_EL0
Definition: misc.hh:802
@ MISCREG_DBGBXVR12
Definition: misc.hh:188
@ MISCREG_DBGWCR6_EL1
Definition: misc.hh:517
@ MISCREG_ID_AFR0_EL1
Definition: misc.hh:550
@ MISCREG_DBGBVR2
Definition: misc.hh:113
@ MISCREG_DBGBVR7_EL1
Definition: misc.hh:470
@ MISCREG_PAR_EL1
Definition: misc.hh:660
@ MISCREG_DBGWVR3_EL1
Definition: misc.hh:498
@ MISCREG_AT_S12E1W_Xt
Definition: misc.hh:678
@ MISCREG_TLBIIPAS2
Definition: misc.hh:350
@ MISCREG_ATS12NSOUW
Definition: misc.hh:316
@ MISCREG_MAIR_EL2
Definition: misc.hh:735
@ MISCREG_CNTV_CVAL
Definition: misc.hh:431
@ MISCREG_MDRAR_EL1
Definition: misc.hh:532
@ MISCREG_CPACR
Definition: misc.hh:246
@ MISCREG_TLBI_VAE2_Xt
Definition: misc.hh:705
@ MISCREG_HAMAIR0
Definition: misc.hh:394
@ MISCREG_TLBIIPAS2L
Definition: misc.hh:351
@ MISCREG_DBGBVR8
Definition: misc.hh:119
@ MISCREG_ADFSR_S
Definition: misc.hh:281
@ MISCREG_SCR_EL3
Definition: misc.hh:598
@ MISCREG_TTBR0_S
Definition: misc.hh:261
@ MISCREG_TLBIALLHIS
Definition: misc.hh:346
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: misc.hh:685
@ MISCREG_IL1DATA1_EL1
Definition: misc.hh:808
@ MISCREG_TLBIIPAS2LIS
Definition: misc.hh:345
@ MISCREG_TLBIASIDIS
Definition: misc.hh:328
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:568
@ MISCREG_ID_ISAR6
Definition: misc.hh:231
@ MISCREG_DBGCLAIMCLR
Definition: misc.hh:198
@ MISCREG_TPIDRRO_EL0
Definition: misc.hh:754
@ MISCREG_DBGBVR3
Definition: misc.hh:114
@ MISCREG_DBGWVR5_EL1
Definition: misc.hh:500
@ MISCREG_DBGOSLAR
Definition: misc.hh:192
@ MISCREG_PMEVTYPER3_EL0
Definition: misc.hh:804
@ MISCREG_DBGBCR10
Definition: misc.hh:137
@ MISCREG_REVIDR_EL1
Definition: misc.hh:546
@ MISCREG_DBGDSCRext
Definition: misc.hh:108
@ MISCREG_TLBI_VAE2IS_Xt
Definition: misc.hh:698
@ MISCREG_TCR_EL3
Definition: misc.hh:615
@ MISCREG_FPSR
Definition: misc.hh:627
@ MISCREG_DBGDIDR
Definition: misc.hh:100
@ MISCREG_DBGBVR9_EL1
Definition: misc.hh:472
@ MISCREG_HDCR
Definition: misc.hh:255
@ MISCREG_AIFSR_S
Definition: misc.hh:284
@ MISCREG_ESR_EL1
Definition: misc.hh:644
@ MISCREG_PMCCNTR_EL0
Definition: misc.hh:725
@ MISCREG_MDCCSR_EL0
Definition: misc.hh:527
@ MISCREG_DTLBIMVA
Definition: misc.hh:336
@ MISCREG_SPSR_UND_AA64
Definition: misc.hh:635
@ MISCREG_DBGWVR13
Definition: misc.hh:156
@ MISCREG_AT_S12E0W_Xt
Definition: misc.hh:680
@ MISCREG_DBGBXVR4
Definition: misc.hh:180
@ MISCREG_TCR_EL1
Definition: misc.hh:606
@ MISCREG_PMINTENSET
Definition: misc.hh:369
@ MISCREG_TTBCR_NS
Definition: misc.hh:266
@ MISCREG_PMXEVTYPER
Definition: misc.hh:365
@ MISCREG_DBGBCR13_EL1
Definition: misc.hh:492
@ MISCREG_TPIDR_EL3
Definition: misc.hh:756
@ MISCREG_DBGBVR11
Definition: misc.hh:122
@ MISCREG_VMPIDR
Definition: misc.hh:239
@ MISCREG_TLBI_VAAE1_Xt
Definition: misc.hh:692
@ MISCREG_TPIDRURW_S
Definition: misc.hh:409
@ MISCREG_CCSIDR_EL1
Definition: misc.hh:576
@ MISCREG_DBGBXVR5
Definition: misc.hh:181
@ MISCREG_CNTVCT
Definition: misc.hh:420
@ MISCREG_TLBIMVALH
Definition: misc.hh:355
@ MISCREG_DL1DATA1_EL1
Definition: misc.hh:812
@ MISCREG_DBGWCR8_EL1
Definition: misc.hh:519
@ MISCREG_AFSR0_EL1
Definition: misc.hh:640
@ MISCREG_TCMTR
Definition: misc.hh:212
@ MISCREG_DBGWCR13_EL1
Definition: misc.hh:524
@ MISCREG_DBGOSDLR
Definition: misc.hh:194
@ MISCREG_DBGBXVR3
Definition: misc.hh:179
@ MISCREG_DBGWCR11_EL1
Definition: misc.hh:522
@ MISCREG_DBGWVR11_EL1
Definition: misc.hh:506
@ MISCREG_TLBI_ALLE2IS
Definition: misc.hh:697
@ MISCREG_ID_ISAR5
Definition: misc.hh:230
@ MISCREG_BPIALL
Definition: misc.hh:305
@ MISCREG_DBGBVR10_EL1
Definition: misc.hh:473
@ MISCREG_ID_ISAR3_EL1
Definition: misc.hh:559
@ MISCREG_PMEVTYPER4_EL0
Definition: misc.hh:805
@ MISCREG_ATS1CUR
Definition: misc.hh:311
@ MISCREG_DC_CVAC_Xt
Definition: misc.hh:672
@ MISCREG_VPIDR_EL2
Definition: misc.hh:582
@ MISCREG_DBGWCR2
Definition: misc.hh:161
@ MISCREG_OSLAR_EL1
Definition: misc.hh:533
@ MISCREG_CNTPCT_EL0
Definition: misc.hh:759
@ MISCREG_DBGWCR4_EL1
Definition: misc.hh:515
@ MISCREG_AMAIR0_NS
Definition: misc.hh:387
@ MISCREG_DBGBCR14_EL1
Definition: misc.hh:493
@ MISCREG_DBGWVR0_EL1
Definition: misc.hh:495
@ MISCREG_AFSR1_EL2
Definition: misc.hh:648
@ MISCREG_CP15DMB
Definition: misc.hh:320
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:479
@ MISCREG_DBGWVR15
Definition: misc.hh:158
@ MISCREG_TLBIMVA
Definition: misc.hh:339
@ MISCREG_PMEVCNTR4_EL0
Definition: misc.hh:799
@ MISCREG_CONTEXTIDR_NS
Definition: misc.hh:405
@ MISCREG_DBGBCR6_EL1
Definition: misc.hh:485
@ MISCREG_ID_ISAR4
Definition: misc.hh:229
@ MISCREG_DBGBCR3_EL1
Definition: misc.hh:482
@ MISCREG_SCTLR_EL1
Definition: misc.hh:584
@ MISCREG_DBGWVR4_EL1
Definition: misc.hh:499
@ MISCREG_TPIDRPRW_NS
Definition: misc.hh:414
@ MISCREG_AIDR_EL1
Definition: misc.hh:578
@ MISCREG_DC_CIVAC_Xt
Definition: misc.hh:674
@ MISCREG_DBGDEVID1
Definition: misc.hh:201
@ MISCREG_TEECR
Definition: misc.hh:203
@ MISCREG_DC_CVAU_Xt
Definition: misc.hh:673
@ MISCREG_DBGBXVR7
Definition: misc.hh:183
@ MISCREG_AMAIR1_S
Definition: misc.hh:391
@ MISCREG_DBGWVR7_EL1
Definition: misc.hh:502
@ MISCREG_DBGBVR9
Definition: misc.hh:120
@ MISCREG_PMEVTYPER0_EL0
Definition: misc.hh:801
@ MISCREG_CPTR_EL2
Definition: misc.hh:593
@ MISCREG_DBGBCR8_EL1
Definition: misc.hh:487
@ MISCREG_CCSIDR
Definition: misc.hh:232
@ MISCREG_FAR_EL1
Definition: misc.hh:654
@ MISCREG_TPIDR_EL1
Definition: misc.hh:752
@ MISCREG_PMUSERENR_EL0
Definition: misc.hh:729
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: misc.hh:686
@ MISCREG_DBGWCR0
Definition: misc.hh:159
@ MISCREG_AT_S1E2R_Xt
Definition: misc.hh:675
@ MISCREG_PMCR
Definition: misc.hh:356
@ MISCREG_CNTP_TVAL_NS
Definition: misc.hh:428
@ MISCREG_CNTV_CTL
Definition: misc.hh:430
@ MISCREG_AFSR1_EL3
Definition: misc.hh:652
@ MISCREG_ADFSR_NS
Definition: misc.hh:280
@ MISCREG_ID_AA64DFR1_EL1
Definition: misc.hh:569
@ MISCREG_DC_CSW_Xt
Definition: misc.hh:668
@ MISCREG_JMCR
Definition: misc.hh:207
@ MISCREG_RMR_EL3
Definition: misc.hh:749
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:573
@ MISCREG_TLBIMVAL
Definition: misc.hh:342
@ MISCREG_DL1DATA2_EL1
Definition: misc.hh:813
@ MISCREG_DBGBVR0
Definition: misc.hh:111
@ MISCREG_PMEVCNTR0_EL0
Definition: misc.hh:795
@ MISCREG_TEECR32_EL1
Definition: misc.hh:540
@ MISCREG_AFSR0_EL3
Definition: misc.hh:651
@ MISCREG_CSSELR_EL1
Definition: misc.hh:579
@ MISCREG_MAIR_EL3
Definition: misc.hh:737
@ MISCREG_ITLBIALL
Definition: misc.hh:332
@ MISCREG_L2MERRSR
Definition: misc.hh:455
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:575
@ MISCREG_DBGPRCR_EL1
Definition: misc.hh:536
@ MISCREG_PMOVSR
Definition: misc.hh:359
@ MISCREG_TLBIALLNSNH
Definition: misc.hh:354
@ MISCREG_CNTHP_TVAL
Definition: misc.hh:437
@ MISCREG_ATS12NSOUR
Definition: misc.hh:315
@ MISCREG_DBGWCR10_EL1
Definition: misc.hh:521
@ MISCREG_CNTVCT_EL0
Definition: misc.hh:760
@ MISCREG_DBGBVR14
Definition: misc.hh:125
@ MISCREG_TLBI_VMALLE1
Definition: misc.hh:689
@ MISCREG_DBGBVR8_EL1
Definition: misc.hh:471
@ MISCREG_CBAR_EL1
Definition: misc.hh:821
@ MISCREG_DL1DATA3_EL1
Definition: misc.hh:814
@ MISCREG_RVBAR_EL2
Definition: misc.hh:746
@ MISCREG_DBGDEVID2
Definition: misc.hh:200
@ MISCREG_SP_EL0
Definition: misc.hh:621
@ MISCREG_PMCNTENCLR
Definition: misc.hh:358
@ MISCREG_TLBI_VMALLS12E1
Definition: misc.hh:708
@ MISCREG_DFAR_S
Definition: misc.hh:290
@ MISCREG_DBGBVR0_EL1
Definition: misc.hh:463
@ MISCREG_DBGBCR4_EL1
Definition: misc.hh:483
@ MISCREG_CPSR
Definition: misc.hh:65
@ MISCREG_FPCR
Definition: misc.hh:626
@ MISCREG_DBGWCR4
Definition: misc.hh:163
@ MISCREG_RMR
Definition: misc.hh:400
@ MISCREG_CPACR_EL1
Definition: misc.hh:587
@ MISCREG_HACR
Definition: misc.hh:258
@ MISCREG_DBGBXVR13
Definition: misc.hh:189
@ MISCREG_IFSR_NS
Definition: misc.hh:277
@ MISCREG_ID_MMFR0
Definition: misc.hh:220
@ MISCREG_PMEVTYPER5_EL0
Definition: misc.hh:806
@ MISCREG_ID_ISAR0
Definition: misc.hh:225
@ MISCREG_DBGBVR2_EL1
Definition: misc.hh:465
@ MISCREG_DL1DATA4
Definition: misc.hh:448
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:773
@ MISCREG_HMAIR0
Definition: misc.hh:392
@ MISCREG_DBGWVR11
Definition: misc.hh:154
@ MISCREG_CNTPCT
Definition: misc.hh:419
@ MISCREG_SP_EL2
Definition: misc.hh:639
@ MISCREG_PMCCFILTR_EL0
Definition: misc.hh:727
@ MISCREG_CNTPS_CTL_EL1
Definition: misc.hh:775
@ MISCREG_TLBI_VALE2_Xt
Definition: misc.hh:707
@ MISCREG_TLBI_VMALLS12E1IS
Definition: misc.hh:701
@ MISCREG_DBGBVR12_EL1
Definition: misc.hh:475
@ MISCREG_PMSWINC_EL0
Definition: misc.hh:721
@ MISCREG_DBGBVR10
Definition: misc.hh:121
@ MISCREG_TTBR1_EL1
Definition: misc.hh:604
@ MISCREG_PMEVTYPER2_EL0
Definition: misc.hh:803
@ MISCREG_TLBI_VAE3IS_Xt
Definition: misc.hh:710
@ MISCREG_DAIF
Definition: misc.hh:625
@ MISCREG_SPSR_ABT_AA64
Definition: misc.hh:634
@ MISCREG_ACTLR_NS
Definition: misc.hh:244
@ MISCREG_PMINTENSET_EL1
Definition: misc.hh:715
@ MISCREG_PMINTENCLR_EL1
Definition: misc.hh:716
@ MISCREG_REVIDR
Definition: misc.hh:215
@ MISCREG_DBGBCR9
Definition: misc.hh:136
@ MISCREG_DL1DATA0_EL1
Definition: misc.hh:811
@ MISCREG_TLBI_VAE1IS_Xt
Definition: misc.hh:684
@ MISCREG_PMCCFILTR
Definition: misc.hh:366
@ MISCREG_ACTLR_EL3
Definition: misc.hh:597
@ MISCREG_ID_PFR1_EL1
Definition: misc.hh:548
@ MISCREG_DBGBCR11_EL1
Definition: misc.hh:490
@ MISCREG_DBGBCR1_EL1
Definition: misc.hh:480
@ MISCREG_TLBIIPAS2IS
Definition: misc.hh:344
@ MISCREG_DBGBVR11_EL1
Definition: misc.hh:474
@ MISCREG_DBGBCR14
Definition: misc.hh:141
@ MISCREG_DBGBCR11
Definition: misc.hh:138
@ MISCREG_TEEHBR32_EL1
Definition: misc.hh:541
@ MISCREG_DBGBVR13
Definition: misc.hh:124
@ MISCREG_ID_MMFR3
Definition: misc.hh:223
@ MISCREG_CSSELR_S
Definition: misc.hh:237
@ MISCREG_DBGBCR12
Definition: misc.hh:139
@ MISCREG_DBGVCR32_EL2
Definition: misc.hh:531
@ MISCREG_DBGWVR9_EL1
Definition: misc.hh:504
@ MISCREG_L2ECTLR
Definition: misc.hh:373
@ MISCREG_ID_PFR0_EL1
Definition: misc.hh:547
@ MISCREG_DL1DATA4_EL1
Definition: misc.hh:815
@ MISCREG_TLBIMVAAIS
Definition: misc.hh:329
@ MISCREG_CNTP_CVAL_NS
Definition: misc.hh:425
@ MISCREG_OSECCR_EL1
Definition: misc.hh:462
@ MISCREG_RVBAR_EL1
Definition: misc.hh:743
@ MISCREG_ISR
Definition: misc.hh:401
@ MISCREG_DBGWCR7_EL1
Definition: misc.hh:518
@ MISCREG_HAIFSR
Definition: misc.hh:286
@ MISCREG_ID_ISAR5_EL1
Definition: misc.hh:561
@ MISCREG_PMCEID1
Definition: misc.hh:363
@ MISCREG_TLBI_ALLE3IS
Definition: misc.hh:709
@ MISCREG_DBGBVR15_EL1
Definition: misc.hh:478
@ MISCREG_ID_ISAR4_EL1
Definition: misc.hh:560
@ MISCREG_SCR
Definition: misc.hh:248
@ MISCREG_DC_IVAC_Xt
Definition: misc.hh:662
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: misc.hh:696
@ MISCREG_PMCNTENSET
Definition: misc.hh:357
@ MISCREG_DBGBVR7
Definition: misc.hh:118
@ MISCREG_DBGWVR9
Definition: misc.hh:152
@ MISCREG_ELR_EL2
Definition: misc.hh:631
@ MISCREG_MAIR0_S
Definition: misc.hh:379
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:822
@ MISCREG_CNTP_TVAL_S
Definition: misc.hh:429
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:778
@ MISCREG_DBGBXVR6
Definition: misc.hh:182
@ MISCREG_DBGBXVR0
Definition: misc.hh:176
@ MISCREG_TEEHBR
Definition: misc.hh:205
@ MISCREG_MDSCR_EL1
Definition: misc.hh:460
@ MISCREG_AMAIR1_NS
Definition: misc.hh:390
@ MISCREG_DL1DATA2
Definition: misc.hh:446
@ MISCREG_DBGWCR2_EL1
Definition: misc.hh:513
@ MISCREG_ID_MMFR4_EL1
Definition: misc.hh:555
@ MISCREG_PAR_S
Definition: misc.hh:301
@ MISCREG_DBGBCR12_EL1
Definition: misc.hh:491
@ MISCREG_ID_DFR0
Definition: misc.hh:218
@ MISCREG_CNTP_CTL_S
Definition: misc.hh:423
@ MISCREG_DBGDTRTXint
Definition: misc.hh:103
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:574
@ MISCREG_HPFAR
Definition: misc.hh:296
@ MISCREG_TPIDRPRW_S
Definition: misc.hh:415
@ MISCREG_TLBIMVAHIS
Definition: misc.hh:347
@ MISCREG_IC_IALLU
Definition: misc.hh:661
@ MISCREG_DBGWCR9
Definition: misc.hh:168
@ MISCREG_SPSR_EL3
Definition: misc.hh:637
@ MISCREG_AT_S1E1R_Xt
Definition: misc.hh:664
@ MISCREG_DTLBIALL
Definition: misc.hh:335
@ MISCREG_TLBIALLIS
Definition: misc.hh:326
@ MISCREG_AMAIR_EL1
Definition: misc.hh:733
@ MISCREG_ESR_EL3
Definition: misc.hh:653
@ MISCREG_IL1DATA0
Definition: misc.hh:440
@ MISCREG_ATS1HW
Definition: misc.hh:325
@ MISCREG_VBAR_S
Definition: misc.hh:398
@ MISCREG_AT_S1E3R_Xt
Definition: misc.hh:681
@ MISCREG_DC_ZVA_Xt
Definition: misc.hh:670
@ MISCREG_ATS1CPR
Definition: misc.hh:309
@ MISCREG_TLBIASID
Definition: misc.hh:340
@ MISCREG_DBGBXVR10
Definition: misc.hh:186
@ MISCREG_ITLBIMVA
Definition: misc.hh:333
@ MISCREG_NZCV
Definition: misc.hh:624
@ MISCREG_HTTBR
Definition: misc.hh:452
@ MISCREG_IFSR32_EL2
Definition: misc.hh:646
@ MISCREG_SPSR_EL1
Definition: misc.hh:617
@ MISCREG_MAIR0_NS
Definition: misc.hh:378
@ MISCREG_CP15DSB
Definition: misc.hh:319
@ MISCREG_DBGDCCINT
Definition: misc.hh:102
@ MISCREG_TLBIALLNSNHIS
Definition: misc.hh:348
@ MISCREG_CNTP_CVAL_EL0
Definition: misc.hh:762
@ MISCREG_HCR_EL2
Definition: misc.hh:591
@ MISCREG_L2ACTLR_EL1
Definition: misc.hh:816
@ MISCREG_DCIMVAC
Definition: misc.hh:307
@ MISCREG_ATS1CPW
Definition: misc.hh:310
@ MISCREG_AT_S12E0R_Xt
Definition: misc.hh:679
@ MISCREG_MPIDR
Definition: misc.hh:214
@ MISCREG_DBGCLAIMSET
Definition: misc.hh:197
@ MISCREG_TLBIMVALHIS
Definition: misc.hh:349
@ MISCREG_PRRR_NS
Definition: misc.hh:375
@ MISCREG_PMCEID0_EL0
Definition: misc.hh:723
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:827
@ MISCREG_SDER32_EL3
Definition: misc.hh:599
@ MISCREG_TPIDR_EL0
Definition: misc.hh:753
@ MISCREG_DBGDTRTXext
Definition: misc.hh:109
@ MISCREG_DBGOSECCR
Definition: misc.hh:110
@ MISCREG_VTCR_EL2
Definition: misc.hh:611
@ MISCREG_DBGWCR3
Definition: misc.hh:162
@ MISCREG_ELR_EL3
Definition: misc.hh:638
@ MISCREG_ITLBIASID
Definition: misc.hh:334
@ MISCREG_DBGWCR11
Definition: misc.hh:170
@ MISCREG_DBGCLAIMSET_EL1
Definition: misc.hh:537
@ MISCREG_VTTBR
Definition: misc.hh:453
@ MISCREG_MDDTRRX_EL0
Definition: misc.hh:530
@ MISCREG_CNTVOFF_EL2
Definition: misc.hh:793
@ MISCREG_DBGWCR6
Definition: misc.hh:165
@ MISCREG_TLBI_VAALE1_Xt
Definition: misc.hh:694
@ MISCREG_VPIDR
Definition: misc.hh:238
@ MISCREG_BPIALLIS
Definition: misc.hh:298
@ MISCREG_DBGWCR15
Definition: misc.hh:174
@ MISCREG_CNTHCTL
Definition: misc.hh:434
@ MISCREG_TTBR1_NS
Definition: misc.hh:263
@ MISCREG_FAR_EL3
Definition: misc.hh:658
@ MISCREG_ACTLR_EL1
Definition: misc.hh:586
@ MISCREG_DBGBVR3_EL1
Definition: misc.hh:466
@ MISCREG_DBGVCR
Definition: misc.hh:106
@ MISCREG_MDCCINT_EL1
Definition: misc.hh:458
@ MISCREG_DBGBVR6_EL1
Definition: misc.hh:469
@ MISCREG_DBGWCR9_EL1
Definition: misc.hh:520
@ MISCREG_IL1DATA3_EL1
Definition: misc.hh:810
@ MISCREG_DC_CISW_Xt
Definition: misc.hh:669
@ MISCREG_VBAR_EL2
Definition: misc.hh:745
@ MISCREG_DBGBCR7_EL1
Definition: misc.hh:486
@ MISCREG_ICIMVAU
Definition: misc.hh:303
@ MISCREG_DBGWCR14
Definition: misc.hh:173
@ MISCREG_DBGBCR5_EL1
Definition: misc.hh:484
@ MISCREG_L2ACTLR
Definition: misc.hh:450
@ MISCREG_ACTLR_EL2
Definition: misc.hh:590
@ MISCREG_CPUMERRSR_EL1
Definition: misc.hh:819
@ MISCREG_IFAR_NS
Definition: misc.hh:292
@ MISCREG_DBGWVR15_EL1
Definition: misc.hh:510
@ MISCREG_CTR
Definition: misc.hh:211
@ MISCREG_HPFAR_EL2
Definition: misc.hh:657
@ MISCREG_DBGBXVR11
Definition: misc.hh:187
@ MISCREG_CLIDR
Definition: misc.hh:233
@ MISCREG_SCTLR_S
Definition: misc.hh:242
@ MISCREG_DBGDTRRXint
Definition: misc.hh:104
@ MISCREG_MDCR_EL2
Definition: misc.hh:592
@ MISCREG_PMSELR
Definition: misc.hh:361
@ MISCREG_ICIALLUIS
Definition: misc.hh:297
@ MISCREG_HACTLR
Definition: misc.hh:252
@ MISCREG_ID_MMFR0_EL1
Definition: misc.hh:551
@ MISCREG_VBAR_EL1
Definition: misc.hh:741
@ MISCREG_MIDR
Definition: misc.hh:210
@ MISCREG_PMEVCNTR2_EL0
Definition: misc.hh:797
@ MISCREG_CNTPS_CVAL_EL1
Definition: misc.hh:776
@ MISCREG_HTCR
Definition: misc.hh:268
@ MISCREG_AMAIR_EL2
Definition: misc.hh:736
@ MISCREG_TLBIMVAIS
Definition: misc.hh:327
@ MISCREG_TTBR1_S
Definition: misc.hh:264
@ MISCREG_HVBAR
Definition: misc.hh:402
@ MISCREG_JIDR
Definition: misc.hh:204
@ MISCREG_DC_ISW_Xt
Definition: misc.hh:663
@ MISCREG_L2CTLR
Definition: misc.hh:372
@ MISCREG_DBGPRCR
Definition: misc.hh:195
@ MISCREG_DBGWVR10
Definition: misc.hh:153
@ MISCREG_TTBR0_EL3
Definition: misc.hh:614
@ MISCREG_DBGWCR0_EL1
Definition: misc.hh:511
@ MISCREG_DCZID_EL0
Definition: misc.hh:581
@ MISCREG_TLBIALLH
Definition: misc.hh:352
@ MISCREG_ATS12NSOPW
Definition: misc.hh:314
@ MISCREG_TLBI_VAE3_Xt
Definition: misc.hh:713
@ MISCREG_DACR_NS
Definition: misc.hh:271
@ MISCREG_TLBIMVAH
Definition: misc.hh:353
@ MISCREG_DBGWVR12
Definition: misc.hh:155
@ MISCREG_TLBI_VALE3IS_Xt
Definition: misc.hh:711
@ MISCREG_ISR_EL1
Definition: misc.hh:744
@ MISCREG_HACR_EL2
Definition: misc.hh:595
@ MISCREG_DBGBCR4
Definition: misc.hh:131
@ MISCREG_OSDTRTX_EL1
Definition: misc.hh:461
@ MISCREG_CNTVOFF
Definition: misc.hh:438
@ MISCREG_DBGCLAIMCLR_EL1
Definition: misc.hh:538
@ MISCREG_AT_S1E0W_Xt
Definition: misc.hh:667
@ MISCREG_AMAIR0_S
Definition: misc.hh:388
@ MISCREG_DCCSW
Definition: misc.hh:318
@ MISCREG_AT_S12E1R_Xt
Definition: misc.hh:677
@ MISCREG_DBGBXVR2
Definition: misc.hh:178
@ MISCREG_TLBTR
Definition: misc.hh:213
@ MISCREG_DBGWVR0
Definition: misc.hh:143
@ MISCREG_ID_AA64AFR1_EL1
Definition: misc.hh:571
@ MISCREG_DBGWCR12
Definition: misc.hh:171
@ MISCREG_DCCMVAU
Definition: misc.hh:321
@ MISCREG_IL1DATA2_EL1
Definition: misc.hh:809
@ MISCREG_DBGBVR14_EL1
Definition: misc.hh:477
@ MISCREG_DTLBIASID
Definition: misc.hh:337
@ MISCREG_ID_ISAR6_EL1
Definition: misc.hh:562
@ MISCREG_ELR_EL1
Definition: misc.hh:619
@ MISCREG_PMXEVCNTR
Definition: misc.hh:367
@ MISCREG_DBGBVR1
Definition: misc.hh:112
@ MISCREG_CNTHP_CTL
Definition: misc.hh:435
@ MISCREG_DBGWCR15_EL1
Definition: misc.hh:526
@ MISCREG_PMCEID0
Definition: misc.hh:362
@ MISCREG_TPIDR_EL2
Definition: misc.hh:755
@ MISCREG_DBGBXVR14
Definition: misc.hh:190
@ MISCREG_DFSR_NS
Definition: misc.hh:274
@ MISCREG_ID_PFR1
Definition: misc.hh:217
@ MISCREG_CNTHP_CVAL_EL2
Definition: misc.hh:780
@ MISCREG_CNTV_TVAL_EL0
Definition: misc.hh:766
@ MISCREG_DBGBCR2
Definition: misc.hh:129
@ MISCREG_DBGWCR14_EL1
Definition: misc.hh:525
@ MISCREG_DCCIMVAC
Definition: misc.hh:322
@ MISCREG_L2CTLR_EL1
Definition: misc.hh:739
@ MISCREG_VTCR
Definition: misc.hh:269
@ MISCREG_FPSCR
Definition: misc.hh:76
@ MISCREG_DBGWVR14_EL1
Definition: misc.hh:509
@ MISCREG_DBGWVR1
Definition: misc.hh:144
@ MISCREG_TTBR0_EL2
Definition: misc.hh:608
@ MISCREG_HSCTLR
Definition: misc.hh:251
@ MISCREG_SCTLR_NS
Definition: misc.hh:241
@ MISCREG_DBGWVR2_EL1
Definition: misc.hh:497
@ MISCREG_ACTLR_S
Definition: misc.hh:245
@ MISCREG_BPIMVA
Definition: misc.hh:306
@ MISCREG_PMINTENCLR
Definition: misc.hh:370
@ MISCREG_PMCNTENCLR_EL0
Definition: misc.hh:719
@ MISCREG_IL1DATA2
Definition: misc.hh:442
@ MISCREG_TTBR0_EL1
Definition: misc.hh:602
@ MISCREG_JOSCR
Definition: misc.hh:206
@ MISCREG_ICIALLU
Definition: misc.hh:302
@ MISCREG_IL1DATA3
Definition: misc.hh:443
@ MISCREG_CNTP_CTL_NS
Definition: misc.hh:422
@ MISCREG_PMEVCNTR5_EL0
Definition: misc.hh:800
@ MISCREG_TLBIALL
Definition: misc.hh:338
@ MISCREG_SCTLR_EL3
Definition: misc.hh:596
@ MISCREG_CNTP_TVAL_EL0
Definition: misc.hh:763
@ MISCREG_CURRENTEL
Definition: misc.hh:623
@ MISCREG_DBGBVR13_EL1
Definition: misc.hh:476
@ MISCREG_DBGWVR6
Definition: misc.hh:149
@ MISCREG_DBGAUTHSTATUS
Definition: misc.hh:199
@ MISCREG_MVFR0_EL1
Definition: misc.hh:563
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: misc.hh:688
@ MISCREG_ID_ISAR1
Definition: misc.hh:226
@ MISCREG_DBGBCR0
Definition: misc.hh:127
@ MISCREG_TTBCR_S
Definition: misc.hh:267
@ MISCREG_IFSR_S
Definition: misc.hh:278
@ MISCREG_PMSWINC
Definition: misc.hh:360
@ MISCREG_MVFR1_EL1
Definition: misc.hh:564
@ MISCREG_ID_AA64AFR0_EL1
Definition: misc.hh:570
@ MISCREG_ATS12NSOPR
Definition: misc.hh:313
@ MISCREG_MVFR2_EL1
Definition: misc.hh:565
@ MISCREG_DBGBCR3
Definition: misc.hh:130
@ MISCREG_OSLSR_EL1
Definition: misc.hh:534
@ MISCREG_DBGBCR9_EL1
Definition: misc.hh:488
@ MISCREG_PMCNTENSET_EL0
Definition: misc.hh:718
@ MISCREG_ID_ISAR1_EL1
Definition: misc.hh:557
@ MISCREG_AIDR
Definition: misc.hh:234
@ MISCREG_DBGWVR12_EL1
Definition: misc.hh:507
@ MISCREG_CPUACTLR_EL1
Definition: misc.hh:817
@ MISCREG_DBGBCR15_EL1
Definition: misc.hh:494
@ MISCREG_DLR_EL0
Definition: misc.hh:629
@ MISCREG_TLBI_VALE2IS_Xt
Definition: misc.hh:700
@ MISCREG_DBGBVR5
Definition: misc.hh:116
@ MISCREG_DBGWVR5
Definition: misc.hh:148
@ MISCREG_ID_MMFR1_EL1
Definition: misc.hh:552
@ MISCREG_MAIR1_S
Definition: misc.hh:385
@ MISCREG_TLBI_VMALLE1IS
Definition: misc.hh:683
@ MISCREG_DACR32_EL2
Definition: misc.hh:616
@ MISCREG_ID_AA64ISAR0_EL1
Definition: misc.hh:572
@ MISCREG_HIFAR
Definition: misc.hh:295
@ MISCREG_DBGWVR8
Definition: misc.hh:151
@ MISCREG_CNTHP_TVAL_EL2
Definition: misc.hh:781
@ MISCREG_AT_S1E3W_Xt
Definition: misc.hh:682
@ MISCREG_TLBI_ALLE2
Definition: misc.hh:704
@ MISCREG_DBGWCR1_EL1
Definition: misc.hh:512
@ MISCREG_DCISW
Definition: misc.hh:308
@ MISCREG_ID_MMFR2
Definition: misc.hh:222
@ MISCREG_HMAIR1
Definition: misc.hh:393
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:583
@ MISCREG_IC_IVAU_Xt
Definition: misc.hh:671
@ MISCREG_DBGBCR8
Definition: misc.hh:135
@ MISCREG_VBAR_NS
Definition: misc.hh:397
@ MISCREG_DBGWCR3_EL1
Definition: misc.hh:514
@ MISCREG_PMOVSCLR_EL0
Definition: misc.hh:720
@ MISCREG_DBGBCR5
Definition: misc.hh:132
@ MISCREG_PMCCNTR
Definition: misc.hh:364
@ MISCREG_HSR
Definition: misc.hh:287
@ MISCREG_HCR2
Definition: misc.hh:254
@ MISCREG_TLBI_VALE1IS_Xt
Definition: misc.hh:687
@ MISCREG_DSPSR_EL0
Definition: misc.hh:628
@ MISCREG_L2MERRSR_EL1
Definition: misc.hh:820
@ MISCREG_CNTHP_CVAL
Definition: misc.hh:436
@ MISCREG_TTBR0_NS
Definition: misc.hh:260
@ MISCREG_FAR_EL2
Definition: misc.hh:656
@ MISCREG_DBGBCR7
Definition: misc.hh:134
@ MISCREG_DBGWVR3
Definition: misc.hh:146
@ MISCREG_PMEVCNTR3_EL0
Definition: misc.hh:798
@ MISCREG_RVBAR_EL3
Definition: misc.hh:748
@ MISCREG_TLBI_VALE3_Xt
Definition: misc.hh:714
@ MISCREG_TLBI_ASIDE1_Xt
Definition: misc.hh:691
@ MISCREG_DBGBCR10_EL1
Definition: misc.hh:489
@ MISCREG_OSDTRRX_EL1
Definition: misc.hh:459
@ MISCREG_AT_S1E0R_Xt
Definition: misc.hh:666
@ MISCREG_MDDTRTX_EL0
Definition: misc.hh:529
@ MISCREG_DBGWVR6_EL1
Definition: misc.hh:501
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: misc.hh:703
@ MISCREG_ID_ISAR3
Definition: misc.hh:228
@ MISCREG_CNTHP_CTL_EL2
Definition: misc.hh:779
@ MISCREG_MVBAR
Definition: misc.hh:399
@ MISCREG_DBGBCR6
Definition: misc.hh:133
@ MISCREG_DBGWVR8_EL1
Definition: misc.hh:503
@ MISCREG_PMCR_EL0
Definition: misc.hh:717
@ MISCREG_CBAR
Definition: misc.hh:451
@ MISCREG_CPTR_EL3
Definition: misc.hh:600
@ MISCREG_ESR_EL2
Definition: misc.hh:649
@ MISCREG_HADFSR
Definition: misc.hh:285
@ MISCREG_SPSR_FIQ_AA64
Definition: misc.hh:636
@ MISCREG_IC_IALLUIS
Definition: misc.hh:659
@ MISCREG_ID_PFR0
Definition: misc.hh:216
@ MISCREG_CLIDR_EL1
Definition: misc.hh:577
@ MISCREG_DBGBVR6
Definition: misc.hh:117
@ MISCREG_NMRR_S
Definition: misc.hh:382
@ MISCREG_DCCMVAC
Definition: misc.hh:317
@ MISCREG_L2ECTLR_EL1
Definition: misc.hh:740
@ MISCREG_IFAR_S
Definition: misc.hh:293
@ MISCREG_ID_MMFR3_EL1
Definition: misc.hh:554
@ MISCREG_SPSR_IRQ_AA64
Definition: misc.hh:633
@ MISCREG_TLBI_VALE1_Xt
Definition: misc.hh:693
@ MISCREG_ID_MMFR4
Definition: misc.hh:224
@ MISCREG_DBGBXVR1
Definition: misc.hh:177
@ MISCREG_AFSR1_EL1
Definition: misc.hh:642
@ MISCREG_CNTP_CVAL_S
Definition: misc.hh:426
@ MISCREG_TPIDRURO_S
Definition: misc.hh:412
@ MISCREG_DBGBVR4_EL1
Definition: misc.hh:467
@ MISCREG_CNTKCTL
Definition: misc.hh:433
@ MISCREG_DBGWVR4
Definition: misc.hh:147
@ MISCREG_CONTEXTIDR_S
Definition: misc.hh:406
@ MISCREG_PMCEID1_EL0
Definition: misc.hh:724
@ MISCREG_TPIDRURW_NS
Definition: misc.hh:408
@ MISCREG_CTR_EL0
Definition: misc.hh:580
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:758
@ MISCREG_ID_AFR0
Definition: misc.hh:219
@ MISCREG_DBGAUTHSTATUS_EL1
Definition: misc.hh:539
@ MISCREG_DBGBCR1
Definition: misc.hh:128
@ MISCREG_FPEXC32_EL2
Definition: misc.hh:650
@ MISCREG_TPIDRURO_NS
Definition: misc.hh:411
@ MISCREG_DBGBCR13
Definition: misc.hh:140
@ MISCREG_MDDTR_EL0
Definition: misc.hh:528
@ MISCREG_TLBIMVAA
Definition: misc.hh:341
@ MISCREG_TLBI_VAE1_Xt
Definition: misc.hh:690
@ MISCREG_PMEVCNTR1_EL0
Definition: misc.hh:796
@ MISCREG_DBGBVR12
Definition: misc.hh:123
@ MISCREG_VTTBR_EL2
Definition: misc.hh:610
@ MISCREG_DBGWCR7
Definition: misc.hh:166
@ MISCREG_MAIR1_NS
Definition: misc.hh:384
@ MISCREG_DBGBVR15
Definition: misc.hh:126
@ MISCREG_DBGBVR4
Definition: misc.hh:115
@ MISCREG_ID_AA64PFR1_EL1
Definition: misc.hh:567
@ MISCREG_RAMINDEX
Definition: misc.hh:449
@ MISCREG_HSTR
Definition: misc.hh:257
@ MISCREG_MDCR_EL3
Definition: misc.hh:601
@ MISCREG_AFSR0_EL2
Definition: misc.hh:647
@ MISCREG_ID_ISAR2
Definition: misc.hh:227
@ MISCREG_PRRR_S
Definition: misc.hh:376
@ MISCREG_CNTV_CVAL_EL0
Definition: misc.hh:765
@ MISCREG_DBGWCR13
Definition: misc.hh:172
@ MISCREG_SP_EL1
Definition: misc.hh:632
@ MISCREG_ATS1CUW
Definition: misc.hh:312
@ MISCREG_PMOVSSET_EL0
Definition: misc.hh:730
constexpr RegClass vecRegClass
Definition: vec.hh:101
uint32_t VecElem
Definition: vec.hh:63
Bitfield< 4 > pc
Bitfield< 10, 5 > event
Bitfield< 0 > v
Definition: pagetable.hh:65
Bitfield< 2 > c
Definition: pagetable.hh:63
Bitfield< 54 > p
Definition: pagetable.hh:70
Bitfield< 3 > addr
Definition: types.hh:84
Bitfield< 16 > usr
Definition: misc.hh:809
std::ostream & output()
Get the ostream from the current global logger.
Definition: trace.cc:79
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
uint64_t Tick
Tick count type.
Definition: types.hh:58
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
Definition: sim_events.cc:88
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
std::vector< EventQueue * > mainEventQueue
Array for main event queues.
Definition: eventq.cc:57
Declaration of the Packet class.
PortProxy Object Declaration.
Event triggered to check the value of the destination registers.

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