gem5  v22.0.0.2
tarmac_parser.cc
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1 /*
2  * Copyright (c) 2011,2017-2020 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
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17  * notice, this list of conditions and the following disclaimer;
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23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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36  */
37 
38 #include <algorithm>
39 #include <cctype>
40 #include <cstring>
41 #include <iomanip>
42 #include <string>
43 
45 
47 #include "arch/arm/mmu.hh"
48 #include "cpu/static_inst.hh"
49 #include "cpu/thread_context.hh"
50 #include "mem/packet.hh"
51 #include "mem/port_proxy.hh"
54 #include "sim/core.hh"
55 #include "sim/cur_tick.hh"
56 #include "sim/faults.hh"
57 #include "sim/full_system.hh"
58 #include "sim/sim_exit.hh"
59 
60 namespace gem5
61 {
62 
63 using namespace ArmISA;
64 
65 namespace Trace {
66 
67 // TARMAC Parser static variables
68 const int TarmacParserRecord::MaxLineLength;
69 int8_t TarmacParserRecord::maxVectorLength = 0;
70 
71 TarmacParserRecord::ParserInstEntry TarmacParserRecord::instRecord;
72 TarmacParserRecord::ParserRegEntry TarmacParserRecord::regRecord;
73 TarmacParserRecord::ParserMemEntry TarmacParserRecord::memRecord;
74 TarmacBaseRecord::TarmacRecordType TarmacParserRecord::currRecordType;
75 
77  TarmacParserRecord::destRegRecords;
78 char TarmacParserRecord::buf[TarmacParserRecord::MaxLineLength];
79 TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
80 
81  { "cpsr", MISCREG_CPSR },
82  { "nzcv", MISCREG_NZCV },
83 
84  // AArch32 CP14 registers
85  { "dbgdidr", MISCREG_DBGDIDR },
86  { "dbgdscrint", MISCREG_DBGDSCRint },
87  { "dbgdccint", MISCREG_DBGDCCINT },
88  { "dbgdtrtxint", MISCREG_DBGDTRTXint },
89  { "dbgdtrrxint", MISCREG_DBGDTRRXint },
90  { "dbgwfar", MISCREG_DBGWFAR },
91  { "dbgvcr", MISCREG_DBGVCR },
92  { "dbgdtrrxext", MISCREG_DBGDTRRXext },
93  { "dbgdscrext", MISCREG_DBGDSCRext },
94  { "dbgdtrtxext", MISCREG_DBGDTRTXext },
95  { "dbgoseccr", MISCREG_DBGOSECCR },
96  { "dbgbvr0", MISCREG_DBGBVR0 },
97  { "dbgbvr1", MISCREG_DBGBVR1 },
98  { "dbgbvr2", MISCREG_DBGBVR2 },
99  { "dbgbvr3", MISCREG_DBGBVR3 },
100  { "dbgbvr4", MISCREG_DBGBVR4 },
101  { "dbgbvr5", MISCREG_DBGBVR5 },
102  { "dbgbvr6", MISCREG_DBGBVR6 },
103  { "dbgbvr7", MISCREG_DBGBVR7 },
104  { "dbgbvr8", MISCREG_DBGBVR8 },
105  { "dbgbvr9", MISCREG_DBGBVR9 },
106  { "dbgbvr10", MISCREG_DBGBVR10 },
107  { "dbgbvr11", MISCREG_DBGBVR11 },
108  { "dbgbvr12", MISCREG_DBGBVR12 },
109  { "dbgbvr13", MISCREG_DBGBVR13 },
110  { "dbgbvr14", MISCREG_DBGBVR14 },
111  { "dbgbvr15", MISCREG_DBGBVR15 },
112  { "dbgbcr0", MISCREG_DBGBCR0 },
113  { "dbgbcr1", MISCREG_DBGBCR1 },
114  { "dbgbcr2", MISCREG_DBGBCR2 },
115  { "dbgbcr3", MISCREG_DBGBCR3 },
116  { "dbgbcr4", MISCREG_DBGBCR4 },
117  { "dbgbcr5", MISCREG_DBGBCR5 },
118  { "dbgbcr6", MISCREG_DBGBCR6 },
119  { "dbgbcr7", MISCREG_DBGBCR7 },
120  { "dbgbcr8", MISCREG_DBGBCR8 },
121  { "dbgbcr9", MISCREG_DBGBCR9 },
122  { "dbgbcr10", MISCREG_DBGBCR10 },
123  { "dbgbcr11", MISCREG_DBGBCR11 },
124  { "dbgbcr12", MISCREG_DBGBCR12 },
125  { "dbgbcr13", MISCREG_DBGBCR13 },
126  { "dbgbcr14", MISCREG_DBGBCR14 },
127  { "dbgbcr15", MISCREG_DBGBCR15 },
128  { "dbgwvr0", MISCREG_DBGWVR0 },
129  { "dbgwvr1", MISCREG_DBGWVR1 },
130  { "dbgwvr2", MISCREG_DBGWVR2 },
131  { "dbgwvr3", MISCREG_DBGWVR3 },
132  { "dbgwvr4", MISCREG_DBGWVR4 },
133  { "dbgwvr5", MISCREG_DBGWVR5 },
134  { "dbgwvr6", MISCREG_DBGWVR6 },
135  { "dbgwvr7", MISCREG_DBGWVR7 },
136  { "dbgwvr8", MISCREG_DBGWVR8 },
137  { "dbgwvr9", MISCREG_DBGWVR9 },
138  { "dbgwvr10", MISCREG_DBGWVR10 },
139  { "dbgwvr11", MISCREG_DBGWVR11 },
140  { "dbgwvr12", MISCREG_DBGWVR12 },
141  { "dbgwvr13", MISCREG_DBGWVR13 },
142  { "dbgwvr14", MISCREG_DBGWVR14 },
143  { "dbgwvr15", MISCREG_DBGWVR15 },
144  { "dbgwcr0", MISCREG_DBGWCR0 },
145  { "dbgwcr1", MISCREG_DBGWCR1 },
146  { "dbgwcr2", MISCREG_DBGWCR2 },
147  { "dbgwcr3", MISCREG_DBGWCR3 },
148  { "dbgwcr4", MISCREG_DBGWCR4 },
149  { "dbgwcr5", MISCREG_DBGWCR5 },
150  { "dbgwcr6", MISCREG_DBGWCR6 },
151  { "dbgwcr7", MISCREG_DBGWCR7 },
152  { "dbgwcr8", MISCREG_DBGWCR8 },
153  { "dbgwcr9", MISCREG_DBGWCR9 },
154  { "dbgwcr10", MISCREG_DBGWCR10 },
155  { "dbgwcr11", MISCREG_DBGWCR11 },
156  { "dbgwcr12", MISCREG_DBGWCR12 },
157  { "dbgwcr13", MISCREG_DBGWCR13 },
158  { "dbgwcr14", MISCREG_DBGWCR14 },
159  { "dbgwcr15", MISCREG_DBGWCR15 },
160  { "dbgdrar", MISCREG_DBGDRAR },
161  { "dbgbxvr0", MISCREG_DBGBXVR0 },
162  { "dbgbxvr1", MISCREG_DBGBXVR1 },
163  { "dbgbxvr2", MISCREG_DBGBXVR2 },
164  { "dbgbxvr3", MISCREG_DBGBXVR3 },
165  { "dbgbxvr4", MISCREG_DBGBXVR4 },
166  { "dbgbxvr5", MISCREG_DBGBXVR5 },
167  { "dbgbxvr6", MISCREG_DBGBXVR6 },
168  { "dbgbxvr7", MISCREG_DBGBXVR7 },
169  { "dbgbxvr8", MISCREG_DBGBXVR8 },
170  { "dbgbxvr9", MISCREG_DBGBXVR9 },
171  { "dbgbxvr10", MISCREG_DBGBXVR10 },
172  { "dbgbxvr11", MISCREG_DBGBXVR11 },
173  { "dbgbxvr12", MISCREG_DBGBXVR12 },
174  { "dbgbxvr13", MISCREG_DBGBXVR13 },
175  { "dbgbxvr14", MISCREG_DBGBXVR14 },
176  { "dbgbxvr15", MISCREG_DBGBXVR15 },
177  { "dbgoslar", MISCREG_DBGOSLAR },
178  { "dbgoslsr", MISCREG_DBGOSLSR },
179  { "dbgosdlr", MISCREG_DBGOSDLR },
180  { "dbgprcr", MISCREG_DBGPRCR },
181  { "dbgdsar", MISCREG_DBGDSAR },
182  { "dbgclaimset", MISCREG_DBGCLAIMSET },
183  { "dbgclaimclr", MISCREG_DBGCLAIMCLR },
184  { "dbgauthstatus", MISCREG_DBGAUTHSTATUS },
185  { "dbgdevid2", MISCREG_DBGDEVID2 },
186  { "dbgdevid1", MISCREG_DBGDEVID1 },
187  { "dbgdevid0", MISCREG_DBGDEVID0 },
188  { "teecr", MISCREG_TEECR },
189  { "jidr", MISCREG_JIDR },
190  { "teehbr", MISCREG_TEEHBR },
191  { "joscr", MISCREG_JOSCR },
192  { "jmcr", MISCREG_JMCR },
193 
194  // AArch32 CP15 registers
195  { "midr", MISCREG_MIDR },
196  { "ctr", MISCREG_CTR },
197  { "tcmtr", MISCREG_TCMTR },
198  { "tlbtr", MISCREG_TLBTR },
199  { "mpidr", MISCREG_MPIDR },
200  { "revidr", MISCREG_REVIDR },
201  { "id_pfr0", MISCREG_ID_PFR0 },
202  { "id_pfr1", MISCREG_ID_PFR1 },
203  { "id_dfr0", MISCREG_ID_DFR0 },
204  { "id_afr0", MISCREG_ID_AFR0 },
205  { "id_mmfr0", MISCREG_ID_MMFR0 },
206  { "id_mmfr1", MISCREG_ID_MMFR1 },
207  { "id_mmfr2", MISCREG_ID_MMFR2 },
208  { "id_mmfr3", MISCREG_ID_MMFR3 },
209  { "id_mmfr4", MISCREG_ID_MMFR4 },
210  { "id_isar0", MISCREG_ID_ISAR0 },
211  { "id_isar1", MISCREG_ID_ISAR1 },
212  { "id_isar2", MISCREG_ID_ISAR2 },
213  { "id_isar3", MISCREG_ID_ISAR3 },
214  { "id_isar4", MISCREG_ID_ISAR4 },
215  { "id_isar5", MISCREG_ID_ISAR5 },
216  { "id_isar6", MISCREG_ID_ISAR6 },
217  { "ccsidr", MISCREG_CCSIDR },
218  { "clidr", MISCREG_CLIDR },
219  { "aidr", MISCREG_AIDR },
220  { "csselr_ns", MISCREG_CSSELR_NS },
221  { "csselr_s", MISCREG_CSSELR_S },
222  { "vpidr", MISCREG_VPIDR },
223  { "vmpidr", MISCREG_VMPIDR },
224  { "sctlr_ns", MISCREG_SCTLR_NS },
225  { "sctlr_s", MISCREG_SCTLR_S },
226  { "actlr_ns", MISCREG_ACTLR_NS },
227  { "actlr_s", MISCREG_ACTLR_S },
228  { "cpacr", MISCREG_CPACR },
229  { "scr", MISCREG_SCR },
230  { "sder", MISCREG_SDER },
231  { "nsacr", MISCREG_NSACR },
232  { "hsctlr", MISCREG_HSCTLR },
233  { "hactlr", MISCREG_HACTLR },
234  { "hcr", MISCREG_HCR },
235  { "hcr2", MISCREG_HCR2 },
236  { "hdcr", MISCREG_HDCR },
237  { "hcptr", MISCREG_HCPTR },
238  { "hstr", MISCREG_HSTR },
239  { "hacr", MISCREG_HACR },
240  { "ttbr0_ns", MISCREG_TTBR0_NS },
241  { "ttbr0_s", MISCREG_TTBR0_S },
242  { "ttbr1_ns", MISCREG_TTBR1_NS },
243  { "ttbr1_s", MISCREG_TTBR1_S },
244  { "ttbcr_ns", MISCREG_TTBCR_NS },
245  { "ttbcr_s", MISCREG_TTBCR_S },
246  { "htcr", MISCREG_HTCR },
247  { "vtcr", MISCREG_VTCR },
248  { "dacr_ns", MISCREG_DACR_NS },
249  { "dacr_s", MISCREG_DACR_S },
250  { "dfsr_ns", MISCREG_DFSR_NS },
251  { "dfsr_s", MISCREG_DFSR_S },
252  { "ifsr_ns", MISCREG_IFSR_NS },
253  { "ifsr_s", MISCREG_IFSR_S },
254  { "adfsr_ns", MISCREG_ADFSR_NS },
255  { "adfsr_s", MISCREG_ADFSR_S },
256  { "aifsr_ns", MISCREG_AIFSR_NS },
257  { "aifsr_s", MISCREG_AIFSR_S },
258  { "hadfsr", MISCREG_HADFSR },
259  { "haifsr", MISCREG_HAIFSR },
260  { "hsr", MISCREG_HSR },
261  { "dfar_ns", MISCREG_DFAR_NS },
262  { "dfar_s", MISCREG_DFAR_S },
263  { "ifar_ns", MISCREG_IFAR_NS },
264  { "ifar_s", MISCREG_IFAR_S },
265  { "hdfar", MISCREG_HDFAR },
266  { "hifar", MISCREG_HIFAR },
267  { "hpfar", MISCREG_HPFAR },
268  { "icialluis", MISCREG_ICIALLUIS },
269  { "bpiallis", MISCREG_BPIALLIS },
270  { "par_ns", MISCREG_PAR_NS },
271  { "par_s", MISCREG_PAR_S },
272  { "iciallu", MISCREG_ICIALLU },
273  { "icimvau", MISCREG_ICIMVAU },
274  { "cp15isb", MISCREG_CP15ISB },
275  { "bpiall", MISCREG_BPIALL },
276  { "bpimva", MISCREG_BPIMVA },
277  { "dcimvac", MISCREG_DCIMVAC },
278  { "dcisw", MISCREG_DCISW },
279  { "ats1cpr", MISCREG_ATS1CPR },
280  { "ats1cpw", MISCREG_ATS1CPW },
281  { "ats1cur", MISCREG_ATS1CUR },
282  { "ats1cuw", MISCREG_ATS1CUW },
283  { "ats12nsopr", MISCREG_ATS12NSOPR },
284  { "ats12nsopw", MISCREG_ATS12NSOPW },
285  { "ats12nsour", MISCREG_ATS12NSOUR },
286  { "ats12nsouw", MISCREG_ATS12NSOUW },
287  { "dccmvac", MISCREG_DCCMVAC },
288  { "dccsw", MISCREG_DCCSW },
289  { "cp15dsb", MISCREG_CP15DSB },
290  { "cp15dmb", MISCREG_CP15DMB },
291  { "dccmvau", MISCREG_DCCMVAU },
292  { "dccimvac", MISCREG_DCCIMVAC },
293  { "dccisw", MISCREG_DCCISW },
294  { "ats1hr", MISCREG_ATS1HR },
295  { "ats1hw", MISCREG_ATS1HW },
296  { "tlbiallis", MISCREG_TLBIALLIS },
297  { "tlbimvais", MISCREG_TLBIMVAIS },
298  { "tlbiasidis", MISCREG_TLBIASIDIS },
299  { "tlbimvaais", MISCREG_TLBIMVAAIS },
300  { "tlbimvalis", MISCREG_TLBIMVALIS },
301  { "tlbimvaalis", MISCREG_TLBIMVAALIS },
302  { "itlbiall", MISCREG_ITLBIALL },
303  { "itlbimva", MISCREG_ITLBIMVA },
304  { "itlbiasid", MISCREG_ITLBIASID },
305  { "dtlbiall", MISCREG_DTLBIALL },
306  { "dtlbimva", MISCREG_DTLBIMVA },
307  { "dtlbiasid", MISCREG_DTLBIASID },
308  { "tlbiall", MISCREG_TLBIALL },
309  { "tlbimva", MISCREG_TLBIMVA },
310  { "tlbiasid", MISCREG_TLBIASID },
311  { "tlbimvaa", MISCREG_TLBIMVAA },
312  { "tlbimval", MISCREG_TLBIMVAL },
313  { "tlbimvaal", MISCREG_TLBIMVAAL },
314  { "tlbiipas2is", MISCREG_TLBIIPAS2IS },
315  { "tlbiipas2lis", MISCREG_TLBIIPAS2LIS },
316  { "tlbiallhis", MISCREG_TLBIALLHIS },
317  { "tlbimvahis", MISCREG_TLBIMVAHIS },
318  { "tlbiallnsnhis", MISCREG_TLBIALLNSNHIS },
319  { "tlbimvalhis", MISCREG_TLBIMVALHIS },
320  { "tlbiipas2", MISCREG_TLBIIPAS2 },
321  { "tlbiipas2l", MISCREG_TLBIIPAS2L },
322  { "tlbiallh", MISCREG_TLBIALLH },
323  { "tlbimvah", MISCREG_TLBIMVAH },
324  { "tlbiallnsnh", MISCREG_TLBIALLNSNH },
325  { "tlbimvalh", MISCREG_TLBIMVALH },
326  { "pmcr", MISCREG_PMCR },
327  { "pmcntenset", MISCREG_PMCNTENSET },
328  { "pmcntenclr", MISCREG_PMCNTENCLR },
329  { "pmovsr", MISCREG_PMOVSR },
330  { "pmswinc", MISCREG_PMSWINC },
331  { "pmselr", MISCREG_PMSELR },
332  { "pmceid0", MISCREG_PMCEID0 },
333  { "pmceid1", MISCREG_PMCEID1 },
334  { "pmccntr", MISCREG_PMCCNTR },
335  { "pmxevtyper", MISCREG_PMXEVTYPER },
336  { "pmccfiltr", MISCREG_PMCCFILTR },
337  { "pmxevcntr", MISCREG_PMXEVCNTR },
338  { "pmuserenr", MISCREG_PMUSERENR },
339  { "pmintenset", MISCREG_PMINTENSET },
340  { "pmintenclr", MISCREG_PMINTENCLR },
341  { "pmovsset", MISCREG_PMOVSSET },
342  { "l2ctlr", MISCREG_L2CTLR },
343  { "l2ectlr", MISCREG_L2ECTLR },
344  { "prrr_ns", MISCREG_PRRR_NS },
345  { "prrr_s", MISCREG_PRRR_S },
346  { "mair0_ns", MISCREG_MAIR0_NS },
347  { "mair0_s", MISCREG_MAIR0_S },
348  { "nmrr_ns", MISCREG_NMRR_NS },
349  { "nmrr_s", MISCREG_NMRR_S },
350  { "mair1_ns", MISCREG_MAIR1_NS },
351  { "mair1_s", MISCREG_MAIR1_S },
352  { "amair0_ns", MISCREG_AMAIR0_NS },
353  { "amair0_s", MISCREG_AMAIR0_S },
354  { "amair1_ns", MISCREG_AMAIR1_NS },
355  { "amair1_s", MISCREG_AMAIR1_S },
356  { "hmair0", MISCREG_HMAIR0 },
357  { "hmair1", MISCREG_HMAIR1 },
358  { "hamair0", MISCREG_HAMAIR0 },
359  { "hamair1", MISCREG_HAMAIR1 },
360  { "vbar_ns", MISCREG_VBAR_NS },
361  { "vbar_s", MISCREG_VBAR_S },
362  { "mvbar", MISCREG_MVBAR },
363  { "rmr", MISCREG_RMR },
364  { "isr", MISCREG_ISR },
365  { "hvbar", MISCREG_HVBAR },
366  { "fcseidr", MISCREG_FCSEIDR },
367  { "contextidr_ns", MISCREG_CONTEXTIDR_NS },
368  { "contextidr_s", MISCREG_CONTEXTIDR_S },
369  { "tpidrurw_ns", MISCREG_TPIDRURW_NS },
370  { "tpidrurw_s", MISCREG_TPIDRURW_S },
371  { "tpidruro_ns", MISCREG_TPIDRURO_NS },
372  { "tpidruro_s", MISCREG_TPIDRURO_S },
373  { "tpidrprw_ns", MISCREG_TPIDRPRW_NS },
374  { "tpidrprw_s", MISCREG_TPIDRPRW_S },
375  { "htpidr", MISCREG_HTPIDR },
376  { "cntfrq", MISCREG_CNTFRQ },
377  { "cntkctl", MISCREG_CNTKCTL },
378  { "cntp_tval_ns", MISCREG_CNTP_TVAL_NS },
379  { "cntp_tval_s", MISCREG_CNTP_TVAL_S },
380  { "cntp_ctl_ns", MISCREG_CNTP_CTL_NS },
381  { "cntp_ctl_s", MISCREG_CNTP_CTL_S },
382  { "cntv_tval", MISCREG_CNTV_TVAL },
383  { "cntv_ctl", MISCREG_CNTV_CTL },
384  { "cnthctl", MISCREG_CNTHCTL },
385  { "cnthp_tval", MISCREG_CNTHP_TVAL },
386  { "cnthp_ctl", MISCREG_CNTHP_CTL },
387  { "il1data0", MISCREG_IL1DATA0 },
388  { "il1data1", MISCREG_IL1DATA1 },
389  { "il1data2", MISCREG_IL1DATA2 },
390  { "il1data3", MISCREG_IL1DATA3 },
391  { "dl1data0", MISCREG_DL1DATA0 },
392  { "dl1data1", MISCREG_DL1DATA1 },
393  { "dl1data2", MISCREG_DL1DATA2 },
394  { "dl1data3", MISCREG_DL1DATA3 },
395  { "dl1data4", MISCREG_DL1DATA4 },
396  { "ramindex", MISCREG_RAMINDEX },
397  { "l2actlr", MISCREG_L2ACTLR },
398  { "cbar", MISCREG_CBAR },
399  { "httbr", MISCREG_HTTBR },
400  { "vttbr", MISCREG_VTTBR },
401  { "cntpct", MISCREG_CNTPCT },
402  { "cntvct", MISCREG_CNTVCT },
403  { "cntp_cval_ns", MISCREG_CNTP_CVAL_NS },
404  { "cntp_cval_s", MISCREG_CNTP_CVAL_S },
405  { "cntv_cval", MISCREG_CNTV_CVAL },
406  { "cntvoff", MISCREG_CNTVOFF },
407  { "cnthp_cval", MISCREG_CNTHP_CVAL },
408  { "cpumerrsr", MISCREG_CPUMERRSR },
409  { "l2merrsr", MISCREG_L2MERRSR },
410 
411  // AArch64 registers (Op0=2)
412  { "mdccint_el1", MISCREG_MDCCINT_EL1 },
413  { "osdtrrx_el1", MISCREG_OSDTRRX_EL1 },
414  { "mdscr_el1", MISCREG_MDSCR_EL1 },
415  { "osdtrtx_el1", MISCREG_OSDTRTX_EL1 },
416  { "oseccr_el1", MISCREG_OSECCR_EL1 },
417  { "dbgbvr0_el1", MISCREG_DBGBVR0_EL1 },
418  { "dbgbvr1_el1", MISCREG_DBGBVR1_EL1 },
419  { "dbgbvr2_el1", MISCREG_DBGBVR2_EL1 },
420  { "dbgbvr3_el1", MISCREG_DBGBVR3_EL1 },
421  { "dbgbvr4_el1", MISCREG_DBGBVR4_EL1 },
422  { "dbgbvr5_el1", MISCREG_DBGBVR5_EL1 },
423  { "dbgbvr6_el1", MISCREG_DBGBVR6_EL1 },
424  { "dbgbvr7_el1", MISCREG_DBGBVR7_EL1 },
425  { "dbgbvr8_el1", MISCREG_DBGBVR8_EL1 },
426  { "dbgbvr9_el1", MISCREG_DBGBVR9_EL1 },
427  { "dbgbvr10_el1", MISCREG_DBGBVR10_EL1 },
428  { "dbgbvr11_el1", MISCREG_DBGBVR11_EL1 },
429  { "dbgbvr12_el1", MISCREG_DBGBVR12_EL1 },
430  { "dbgbvr13_el1", MISCREG_DBGBVR13_EL1 },
431  { "dbgbvr14_el1", MISCREG_DBGBVR14_EL1 },
432  { "dbgbvr15_el1", MISCREG_DBGBVR15_EL1 },
433  { "dbgbcr0_el1", MISCREG_DBGBCR0_EL1 },
434  { "dbgbcr1_el1", MISCREG_DBGBCR1_EL1 },
435  { "dbgbcr2_el1", MISCREG_DBGBCR2_EL1 },
436  { "dbgbcr3_el1", MISCREG_DBGBCR3_EL1 },
437  { "dbgbcr4_el1", MISCREG_DBGBCR4_EL1 },
438  { "dbgbcr5_el1", MISCREG_DBGBCR5_EL1 },
439  { "dbgbcr6_el1", MISCREG_DBGBCR6_EL1 },
440  { "dbgbcr7_el1", MISCREG_DBGBCR7_EL1 },
441  { "dbgbcr8_el1", MISCREG_DBGBCR8_EL1 },
442  { "dbgbcr9_el1", MISCREG_DBGBCR9_EL1 },
443  { "dbgbcr10_el1", MISCREG_DBGBCR10_EL1 },
444  { "dbgbcr11_el1", MISCREG_DBGBCR11_EL1 },
445  { "dbgbcr12_el1", MISCREG_DBGBCR12_EL1 },
446  { "dbgbcr13_el1", MISCREG_DBGBCR13_EL1 },
447  { "dbgbcr14_el1", MISCREG_DBGBCR14_EL1 },
448  { "dbgbcr15_el1", MISCREG_DBGBCR15_EL1 },
449  { "dbgwvr0_el1", MISCREG_DBGWVR0_EL1 },
450  { "dbgwvr1_el1", MISCREG_DBGWVR1_EL1 },
451  { "dbgwvr2_el1", MISCREG_DBGWVR2_EL1 },
452  { "dbgwvr3_el1", MISCREG_DBGWVR3_EL1 },
453  { "dbgwvr4_el1", MISCREG_DBGWVR4_EL1 },
454  { "dbgwvr5_el1", MISCREG_DBGWVR5_EL1 },
455  { "dbgwvr6_el1", MISCREG_DBGWVR6_EL1 },
456  { "dbgwvr7_el1", MISCREG_DBGWVR7_EL1 },
457  { "dbgwvr8_el1", MISCREG_DBGWVR8_EL1 },
458  { "dbgwvr9_el1", MISCREG_DBGWVR9_EL1 },
459  { "dbgwvr10_el1", MISCREG_DBGWVR10_EL1 },
460  { "dbgwvr11_el1", MISCREG_DBGWVR11_EL1 },
461  { "dbgwvr12_el1", MISCREG_DBGWVR12_EL1 },
462  { "dbgwvr13_el1", MISCREG_DBGWVR13_EL1 },
463  { "dbgwvr14_el1", MISCREG_DBGWVR14_EL1 },
464  { "dbgwvr15_el1", MISCREG_DBGWVR15_EL1 },
465  { "dbgwcr0_el1", MISCREG_DBGWCR0_EL1 },
466  { "dbgwcr1_el1", MISCREG_DBGWCR1_EL1 },
467  { "dbgwcr2_el1", MISCREG_DBGWCR2_EL1 },
468  { "dbgwcr3_el1", MISCREG_DBGWCR3_EL1 },
469  { "dbgwcr4_el1", MISCREG_DBGWCR4_EL1 },
470  { "dbgwcr5_el1", MISCREG_DBGWCR5_EL1 },
471  { "dbgwcr6_el1", MISCREG_DBGWCR6_EL1 },
472  { "dbgwcr7_el1", MISCREG_DBGWCR7_EL1 },
473  { "dbgwcr8_el1", MISCREG_DBGWCR8_EL1 },
474  { "dbgwcr9_el1", MISCREG_DBGWCR9_EL1 },
475  { "dbgwcr10_el1", MISCREG_DBGWCR10_EL1 },
476  { "dbgwcr11_el1", MISCREG_DBGWCR11_EL1 },
477  { "dbgwcr12_el1", MISCREG_DBGWCR12_EL1 },
478  { "dbgwcr13_el1", MISCREG_DBGWCR13_EL1 },
479  { "dbgwcr14_el1", MISCREG_DBGWCR14_EL1 },
480  { "dbgwcr15_el1", MISCREG_DBGWCR15_EL1 },
481  { "mdccsr_el0", MISCREG_MDCCSR_EL0 },
482  { "mddtr_el0", MISCREG_MDDTR_EL0 },
483  { "mddtrtx_el0", MISCREG_MDDTRTX_EL0 },
484  { "mddtrrx_el0", MISCREG_MDDTRRX_EL0 },
485  { "dbgvcr32_el2", MISCREG_DBGVCR32_EL2 },
486  { "mdrar_el1", MISCREG_MDRAR_EL1 },
487  { "oslar_el1", MISCREG_OSLAR_EL1 },
488  { "oslsr_el1", MISCREG_OSLSR_EL1 },
489  { "osdlr_el1", MISCREG_OSDLR_EL1 },
490  { "dbgprcr_el1", MISCREG_DBGPRCR_EL1 },
491  { "dbgclaimset_el1", MISCREG_DBGCLAIMSET_EL1 },
492  { "dbgclaimclr_el1", MISCREG_DBGCLAIMCLR_EL1 },
493  { "dbgauthstatus_el1", MISCREG_DBGAUTHSTATUS_EL1 },
494  { "teecr32_el1", MISCREG_TEECR32_EL1 },
495  { "teehbr32_el1", MISCREG_TEEHBR32_EL1 },
496 
497  // AArch64 registers (Op0=1,3)
498  { "midr_el1", MISCREG_MIDR_EL1 },
499  { "mpidr_el1", MISCREG_MPIDR_EL1 },
500  { "revidr_el1", MISCREG_REVIDR_EL1 },
501  { "id_pfr0_el1", MISCREG_ID_PFR0_EL1 },
502  { "id_pfr1_el1", MISCREG_ID_PFR1_EL1 },
503  { "id_dfr0_el1", MISCREG_ID_DFR0_EL1 },
504  { "id_afr0_el1", MISCREG_ID_AFR0_EL1 },
505  { "id_mmfr0_el1", MISCREG_ID_MMFR0_EL1 },
506  { "id_mmfr1_el1", MISCREG_ID_MMFR1_EL1 },
507  { "id_mmfr2_el1", MISCREG_ID_MMFR2_EL1 },
508  { "id_mmfr3_el1", MISCREG_ID_MMFR3_EL1 },
509  { "id_mmfr4_el1", MISCREG_ID_MMFR4_EL1 },
510  { "id_isar0_el1", MISCREG_ID_ISAR0_EL1 },
511  { "id_isar1_el1", MISCREG_ID_ISAR1_EL1 },
512  { "id_isar2_el1", MISCREG_ID_ISAR2_EL1 },
513  { "id_isar3_el1", MISCREG_ID_ISAR3_EL1 },
514  { "id_isar4_el1", MISCREG_ID_ISAR4_EL1 },
515  { "id_isar5_el1", MISCREG_ID_ISAR5_EL1 },
516  { "id_isar6_el1", MISCREG_ID_ISAR6_EL1 },
517  { "mvfr0_el1", MISCREG_MVFR0_EL1 },
518  { "mvfr1_el1", MISCREG_MVFR1_EL1 },
519  { "mvfr2_el1", MISCREG_MVFR2_EL1 },
520  { "id_aa64pfr0_el1", MISCREG_ID_AA64PFR0_EL1 },
521  { "id_aa64pfr1_el1", MISCREG_ID_AA64PFR1_EL1 },
522  { "id_aa64dfr0_el1", MISCREG_ID_AA64DFR0_EL1 },
523  { "id_aa64dfr1_el1", MISCREG_ID_AA64DFR1_EL1 },
524  { "id_aa64afr0_el1", MISCREG_ID_AA64AFR0_EL1 },
525  { "id_aa64afr1_el1", MISCREG_ID_AA64AFR1_EL1 },
526  { "id_aa64isar0_el1", MISCREG_ID_AA64ISAR0_EL1 },
527  { "id_aa64isar1_el1", MISCREG_ID_AA64ISAR1_EL1 },
528  { "id_aa64mmfr0_el1", MISCREG_ID_AA64MMFR0_EL1 },
529  { "id_aa64mmfr1_el1", MISCREG_ID_AA64MMFR1_EL1 },
530  { "id_aa64mmfr2_el1", MISCREG_ID_AA64MMFR2_EL1 },
531  { "ccsidr_el1", MISCREG_CCSIDR_EL1 },
532  { "clidr_el1", MISCREG_CLIDR_EL1 },
533  { "aidr_el1", MISCREG_AIDR_EL1 },
534  { "csselr_el1", MISCREG_CSSELR_EL1 },
535  { "ctr_el0", MISCREG_CTR_EL0 },
536  { "dczid_el0", MISCREG_DCZID_EL0 },
537  { "vpidr_el2", MISCREG_VPIDR_EL2 },
538  { "vmpidr_el2", MISCREG_VMPIDR_EL2 },
539  { "sctlr_el1", MISCREG_SCTLR_EL1 },
540  { "actlr_el1", MISCREG_ACTLR_EL1 },
541  { "cpacr_el1", MISCREG_CPACR_EL1 },
542  { "sctlr_el2", MISCREG_SCTLR_EL2 },
543  { "actlr_el2", MISCREG_ACTLR_EL2 },
544  { "hcr_el2", MISCREG_HCR_EL2 },
545  { "mdcr_el2", MISCREG_MDCR_EL2 },
546  { "cptr_el2", MISCREG_CPTR_EL2 },
547  { "hstr_el2", MISCREG_HSTR_EL2 },
548  { "hacr_el2", MISCREG_HACR_EL2 },
549  { "sctlr_el3", MISCREG_SCTLR_EL3 },
550  { "actlr_el3", MISCREG_ACTLR_EL3 },
551  { "scr_el3", MISCREG_SCR_EL3 },
552  { "sder32_el3", MISCREG_SDER32_EL3 },
553  { "cptr_el3", MISCREG_CPTR_EL3 },
554  { "mdcr_el3", MISCREG_MDCR_EL3 },
555  { "ttbr0_el1", MISCREG_TTBR0_EL1 },
556  { "ttbr1_el1", MISCREG_TTBR1_EL1 },
557  { "tcr_el1", MISCREG_TCR_EL1 },
558  { "ttbr0_el2", MISCREG_TTBR0_EL2 },
559  { "tcr_el2", MISCREG_TCR_EL2 },
560  { "vttbr_el2", MISCREG_VTTBR_EL2 },
561  { "vtcr_el2", MISCREG_VTCR_EL2 },
562  { "ttbr0_el3", MISCREG_TTBR0_EL3 },
563  { "tcr_el3", MISCREG_TCR_EL3 },
564  { "dacr32_el2", MISCREG_DACR32_EL2 },
565  { "spsr_el1", MISCREG_SPSR_EL1 },
566  { "elr_el1", MISCREG_ELR_EL1 },
567  { "sp_el0", MISCREG_SP_EL0 },
568  { "spsel", MISCREG_SPSEL },
569  { "currentel", MISCREG_CURRENTEL },
570  { "nzcv", MISCREG_NZCV },
571  { "daif", MISCREG_DAIF },
572  { "fpcr", MISCREG_FPCR },
573  { "fpsr", MISCREG_FPSR },
574  { "dspsr_el0", MISCREG_DSPSR_EL0 },
575  { "dlr_el0", MISCREG_DLR_EL0 },
576  { "spsr_el2", MISCREG_SPSR_EL2 },
577  { "elr_el2", MISCREG_ELR_EL2 },
578  { "sp_el1", MISCREG_SP_EL1 },
579  { "spsr_irq", MISCREG_SPSR_IRQ_AA64 },
580  { "spsr_abt", MISCREG_SPSR_ABT_AA64 },
581  { "spsr_und", MISCREG_SPSR_UND_AA64 },
582  { "spsr_fiq", MISCREG_SPSR_FIQ_AA64 },
583  { "spsr_el3", MISCREG_SPSR_EL3 },
584  { "elr_el3", MISCREG_ELR_EL3 },
585  { "sp_el2", MISCREG_SP_EL2 },
586  { "afsr0_el1", MISCREG_AFSR0_EL1 },
587  { "afsr1_el1", MISCREG_AFSR1_EL1 },
588  { "esr_el1", MISCREG_ESR_EL1 },
589  { "ifsr32_el2", MISCREG_IFSR32_EL2 },
590  { "afsr0_el2", MISCREG_AFSR0_EL2 },
591  { "afsr1_el2", MISCREG_AFSR1_EL2 },
592  { "esr_el2", MISCREG_ESR_EL2 },
593  { "fpexc32_el2", MISCREG_FPEXC32_EL2 },
594  { "afsr0_el3", MISCREG_AFSR0_EL3 },
595  { "afsr1_el3", MISCREG_AFSR1_EL3 },
596  { "esr_el3", MISCREG_ESR_EL3 },
597  { "far_el1", MISCREG_FAR_EL1 },
598  { "far_el2", MISCREG_FAR_EL2 },
599  { "hpfar_el2", MISCREG_HPFAR_EL2 },
600  { "far_el3", MISCREG_FAR_EL3 },
601  { "ic_ialluis", MISCREG_IC_IALLUIS },
602  { "par_el1", MISCREG_PAR_EL1 },
603  { "ic_iallu", MISCREG_IC_IALLU },
604  { "dc_ivac_xt", MISCREG_DC_IVAC_Xt },
605  { "dc_isw_xt", MISCREG_DC_ISW_Xt },
606  { "at_s1e1r_xt", MISCREG_AT_S1E1R_Xt },
607  { "at_s1e1w_xt", MISCREG_AT_S1E1W_Xt },
608  { "at_s1e0r_xt", MISCREG_AT_S1E0R_Xt },
609  { "at_s1e0w_xt", MISCREG_AT_S1E0W_Xt },
610  { "dc_csw_xt", MISCREG_DC_CSW_Xt },
611  { "dc_cisw_xt", MISCREG_DC_CISW_Xt },
612  { "dc_zva_xt", MISCREG_DC_ZVA_Xt },
613  { "ic_ivau_xt", MISCREG_IC_IVAU_Xt },
614  { "dc_cvac_xt", MISCREG_DC_CVAC_Xt },
615  { "dc_cvau_xt", MISCREG_DC_CVAU_Xt },
616  { "dc_civac_xt", MISCREG_DC_CIVAC_Xt },
617  { "at_s1e2r_xt", MISCREG_AT_S1E2R_Xt },
618  { "at_s1e2w_xt", MISCREG_AT_S1E2W_Xt },
619  { "at_s12e1r_xt", MISCREG_AT_S12E1R_Xt },
620  { "at_s12e1w_xt", MISCREG_AT_S12E1W_Xt },
621  { "at_s12e0r_xt", MISCREG_AT_S12E0R_Xt },
622  { "at_s12e0w_xt", MISCREG_AT_S12E0W_Xt },
623  { "at_s1e3r_xt", MISCREG_AT_S1E3R_Xt },
624  { "at_s1e3w_xt", MISCREG_AT_S1E3W_Xt },
625  { "tlbi_vmalle1is", MISCREG_TLBI_VMALLE1IS },
626  { "tlbi_vae1is_xt", MISCREG_TLBI_VAE1IS_Xt },
627  { "tlbi_aside1is_xt", MISCREG_TLBI_ASIDE1IS_Xt },
628  { "tlbi_vaae1is_xt", MISCREG_TLBI_VAAE1IS_Xt },
629  { "tlbi_vale1is_xt", MISCREG_TLBI_VALE1IS_Xt },
630  { "tlbi_vaale1is_xt", MISCREG_TLBI_VAALE1IS_Xt },
631  { "tlbi_vmalle1", MISCREG_TLBI_VMALLE1 },
632  { "tlbi_vae1_xt", MISCREG_TLBI_VAE1_Xt },
633  { "tlbi_aside1_xt", MISCREG_TLBI_ASIDE1_Xt },
634  { "tlbi_vaae1_xt", MISCREG_TLBI_VAAE1_Xt },
635  { "tlbi_vale1_xt", MISCREG_TLBI_VALE1_Xt },
636  { "tlbi_vaale1_xt", MISCREG_TLBI_VAALE1_Xt },
637  { "tlbi_ipas2e1is_xt", MISCREG_TLBI_IPAS2E1IS_Xt },
638  { "tlbi_ipas2le1is_xt", MISCREG_TLBI_IPAS2LE1IS_Xt },
639  { "tlbi_alle2is", MISCREG_TLBI_ALLE2IS },
640  { "tlbi_vae2is_xt", MISCREG_TLBI_VAE2IS_Xt },
641  { "tlbi_alle1is", MISCREG_TLBI_ALLE1IS },
642  { "tlbi_vale2is_xt", MISCREG_TLBI_VALE2IS_Xt },
643  { "tlbi_vmalls12e1is", MISCREG_TLBI_VMALLS12E1IS },
644  { "tlbi_ipas2e1_xt", MISCREG_TLBI_IPAS2E1_Xt },
645  { "tlbi_ipas2le1_xt", MISCREG_TLBI_IPAS2LE1_Xt },
646  { "tlbi_alle2", MISCREG_TLBI_ALLE2 },
647  { "tlbi_vae2_xt", MISCREG_TLBI_VAE2_Xt },
648  { "tlbi_alle1", MISCREG_TLBI_ALLE1 },
649  { "tlbi_vale2_xt", MISCREG_TLBI_VALE2_Xt },
650  { "tlbi_vmalls12e1", MISCREG_TLBI_VMALLS12E1 },
651  { "tlbi_alle3is", MISCREG_TLBI_ALLE3IS },
652  { "tlbi_vae3is_xt", MISCREG_TLBI_VAE3IS_Xt },
653  { "tlbi_vale3is_xt", MISCREG_TLBI_VALE3IS_Xt },
654  { "tlbi_alle3", MISCREG_TLBI_ALLE3 },
655  { "tlbi_vae3_xt", MISCREG_TLBI_VAE3_Xt },
656  { "tlbi_vale3_xt", MISCREG_TLBI_VALE3_Xt },
657  { "pmintenset_el1", MISCREG_PMINTENSET_EL1 },
658  { "pmintenclr_el1", MISCREG_PMINTENCLR_EL1 },
659  { "pmcr_el0", MISCREG_PMCR_EL0 },
660  { "pmcntenset_el0", MISCREG_PMCNTENSET_EL0 },
661  { "pmcntenclr_el0", MISCREG_PMCNTENCLR_EL0 },
662  { "pmovsclr_el0", MISCREG_PMOVSCLR_EL0 },
663  { "pmswinc_el0", MISCREG_PMSWINC_EL0 },
664  { "pmselr_el0", MISCREG_PMSELR_EL0 },
665  { "pmceid0_el0", MISCREG_PMCEID0_EL0 },
666  { "pmceid1_el0", MISCREG_PMCEID1_EL0 },
667  { "pmccntr_el0", MISCREG_PMCCNTR_EL0 },
668  { "pmxevtyper_el0", MISCREG_PMXEVTYPER_EL0 },
669  { "pmccfiltr_el0", MISCREG_PMCCFILTR_EL0 },
670  { "pmxevcntr_el0", MISCREG_PMXEVCNTR_EL0 },
671  { "pmuserenr_el0", MISCREG_PMUSERENR_EL0 },
672  { "pmovsset_el0", MISCREG_PMOVSSET_EL0 },
673  { "mair_el1", MISCREG_MAIR_EL1 },
674  { "amair_el1", MISCREG_AMAIR_EL1 },
675  { "mair_el2", MISCREG_MAIR_EL2 },
676  { "amair_el2", MISCREG_AMAIR_EL2 },
677  { "mair_el3", MISCREG_MAIR_EL3 },
678  { "amair_el3", MISCREG_AMAIR_EL3 },
679  { "l2ctlr_el1", MISCREG_L2CTLR_EL1 },
680  { "l2ectlr_el1", MISCREG_L2ECTLR_EL1 },
681  { "vbar_el1", MISCREG_VBAR_EL1 },
682  { "rvbar_el1", MISCREG_RVBAR_EL1 },
683  { "isr_el1", MISCREG_ISR_EL1 },
684  { "vbar_el2", MISCREG_VBAR_EL2 },
685  { "rvbar_el2", MISCREG_RVBAR_EL2 },
686  { "vbar_el3", MISCREG_VBAR_EL3 },
687  { "rvbar_el3", MISCREG_RVBAR_EL3 },
688  { "rmr_el3", MISCREG_RMR_EL3 },
689  { "contextidr_el1", MISCREG_CONTEXTIDR_EL1 },
690  { "contextidr_el2", MISCREG_CONTEXTIDR_EL2 },
691  { "tpidr_el1", MISCREG_TPIDR_EL1 },
692  { "tpidr_el0", MISCREG_TPIDR_EL0 },
693  { "tpidrro_el0", MISCREG_TPIDRRO_EL0 },
694  { "tpidr_el2", MISCREG_TPIDR_EL2 },
695  { "tpidr_el3", MISCREG_TPIDR_EL3 },
696  { "cntkctl_el1", MISCREG_CNTKCTL_EL1 },
697  { "cntfrq_el0", MISCREG_CNTFRQ_EL0 },
698  { "cntpct_el0", MISCREG_CNTPCT_EL0 },
699  { "cntvct_el0", MISCREG_CNTVCT_EL0 },
700  { "cntp_tval_el0", MISCREG_CNTP_TVAL_EL0 },
701  { "cntp_ctl_el0", MISCREG_CNTP_CTL_EL0 },
702  { "cntp_cval_el0", MISCREG_CNTP_CVAL_EL0 },
703  { "cntv_tval_el0", MISCREG_CNTV_TVAL_EL0 },
704  { "cntv_ctl_el0", MISCREG_CNTV_CTL_EL0 },
705  { "cntv_cval_el0", MISCREG_CNTV_CVAL_EL0 },
706  { "pmevcntr0_el0", MISCREG_PMEVCNTR0_EL0 },
707  { "pmevcntr1_el0", MISCREG_PMEVCNTR1_EL0 },
708  { "pmevcntr2_el0", MISCREG_PMEVCNTR2_EL0 },
709  { "pmevcntr3_el0", MISCREG_PMEVCNTR3_EL0 },
710  { "pmevcntr4_el0", MISCREG_PMEVCNTR4_EL0 },
711  { "pmevcntr5_el0", MISCREG_PMEVCNTR5_EL0 },
712  { "pmevtyper0_el0", MISCREG_PMEVTYPER0_EL0 },
713  { "pmevtyper1_el0", MISCREG_PMEVTYPER1_EL0 },
714  { "pmevtyper2_el0", MISCREG_PMEVTYPER2_EL0 },
715  { "pmevtyper3_el0", MISCREG_PMEVTYPER3_EL0 },
716  { "pmevtyper4_el0", MISCREG_PMEVTYPER4_EL0 },
717  { "pmevtyper5_el0", MISCREG_PMEVTYPER5_EL0 },
718  { "cntvoff_el2", MISCREG_CNTVOFF_EL2 },
719  { "cnthctl_el2", MISCREG_CNTHCTL_EL2 },
720  { "cnthp_tval_el2", MISCREG_CNTHP_TVAL_EL2 },
721  { "cnthp_ctl_el2", MISCREG_CNTHP_CTL_EL2 },
722  { "cnthp_cval_el2", MISCREG_CNTHP_CVAL_EL2 },
723  { "cntps_tval_el1", MISCREG_CNTPS_TVAL_EL1 },
724  { "cntps_ctl_el1", MISCREG_CNTPS_CTL_EL1 },
725  { "cntps_cval_el1", MISCREG_CNTPS_CVAL_EL1 },
726  { "il1data0_el1", MISCREG_IL1DATA0_EL1 },
727  { "il1data1_el1", MISCREG_IL1DATA1_EL1 },
728  { "il1data2_el1", MISCREG_IL1DATA2_EL1 },
729  { "il1data3_el1", MISCREG_IL1DATA3_EL1 },
730  { "dl1data0_el1", MISCREG_DL1DATA0_EL1 },
731  { "dl1data1_el1", MISCREG_DL1DATA1_EL1 },
732  { "dl1data2_el1", MISCREG_DL1DATA2_EL1 },
733  { "dl1data3_el1", MISCREG_DL1DATA3_EL1 },
734  { "dl1data4_el1", MISCREG_DL1DATA4_EL1 },
735  { "l2actlr_el1", MISCREG_L2ACTLR_EL1 },
736  { "cpuactlr_el1", MISCREG_CPUACTLR_EL1 },
737  { "cpuectlr_el1", MISCREG_CPUECTLR_EL1 },
738  { "cpumerrsr_el1", MISCREG_CPUMERRSR_EL1 },
739  { "l2merrsr_el1", MISCREG_L2MERRSR_EL1 },
740  { "cbar_el1", MISCREG_CBAR_EL1 },
741 };
742 
743 void
744 TarmacParserRecord::TarmacParserRecordEvent::process()
745 {
746  std::ostream &outs = Trace::output();
747 
748  std::list<ParserRegEntry>::iterator it = destRegRecords.begin(),
749  end = destRegRecords.end();
750 
751  std::vector<uint64_t> values;
752 
753  for (; it != end; ++it) {
754  values.clear();
755  switch (it->type) {
756  case REG_R:
757  case REG_X:
758  values.push_back(thread->getReg(RegId(IntRegClass, it->index)));
759  break;
760  case REG_S:
761  if (instRecord.isetstate == ISET_A64) {
763  thread->getReg(RegId(VecRegClass, it->index), &vc);
764  auto vv = vc.as<uint32_t>();
765  values.push_back(vv[0]);
766  } else {
767  const VecElem elem = thread->getReg(
768  RegId(VecElemClass, it->index));
769  values.push_back(elem);
770  }
771  break;
772  case REG_D:
773  if (instRecord.isetstate == ISET_A64) {
775  thread->getReg(RegId(VecRegClass, it->index), &vc);
776  auto vv = vc.as<uint64_t>();
777  values.push_back(vv[0]);
778  } else {
779  const VecElem w0 = thread->getReg(
780  RegId(VecElemClass, it->index));
781  const VecElem w1 = thread->getReg(
782  RegId(VecElemClass, it->index + 1));
783 
784  values.push_back((uint64_t)(w1) << 32 | w0);
785  }
786  break;
787  case REG_P:
788  {
790  thread->getReg(RegId(VecPredRegClass, it->index), &pc);
791  auto pv = pc.as<uint8_t>();
792  uint64_t p = 0;
793  for (int i = maxVectorLength * 8; i > 0; ) {
794  p = (p << 1) | pv[--i];
795  }
796  values.push_back(p);
797  }
798  break;
799  case REG_Q:
800  if (instRecord.isetstate == ISET_A64) {
802  thread->getReg(RegId(VecRegClass, it->index), &vc);
803  auto vv = vc.as<uint64_t>();
804  values.push_back(vv[0]);
805  values.push_back(vv[1]);
806  } else {
807  const VecElem w0 = thread->getReg(
808  RegId(VecElemClass, it->index));
809  const VecElem w1 = thread->getReg(
810  RegId(VecElemClass, it->index + 1));
811  const VecElem w2 = thread->getReg(
812  RegId(VecElemClass, it->index + 2));
813  const VecElem w3 = thread->getReg(
814  RegId(VecElemClass, it->index + 3));
815 
816  values.push_back((uint64_t)(w1) << 32 | w0);
817  values.push_back((uint64_t)(w3) << 32 | w2);
818  }
819  break;
820  case REG_Z:
821  {
822  int8_t i = maxVectorLength;
824  thread->getReg(RegId(VecRegClass, it->index), &vc);
825  auto vv = vc.as<uint64_t>();
826  while (i > 0) {
827  values.push_back(vv[--i]);
828  }
829  }
830  break;
831  case REG_MISC:
832  if (it->index == MISCREG_CPSR) {
833  // Read condition codes from aliased integer regs
834  CPSR cpsr = thread->readMiscRegNoEffect(it->index);
835  cpsr.nz = thread->getReg(cc_reg::Nz);
836  cpsr.c = thread->getReg(cc_reg::C);
837  cpsr.v = thread->getReg(cc_reg::V);
838  cpsr.ge = thread->getReg(cc_reg::Ge);
839  values.push_back(cpsr);
840  } else if (it->index == MISCREG_NZCV) {
841  CPSR cpsr = 0;
842  cpsr.nz = thread->getReg(cc_reg::Nz);
843  cpsr.c = thread->getReg(cc_reg::C);
844  cpsr.v = thread->getReg(cc_reg::V);
845  values.push_back(cpsr);
846  } else if (it->index == MISCREG_FPCR) {
847  // Read FPSCR and extract FPCR value
848  FPSCR fpscr = thread->readMiscRegNoEffect(MISCREG_FPSCR);
849  const uint32_t ones = (uint32_t)(-1);
850  FPSCR fpcrMask = 0;
851  fpcrMask.ioe = ones;
852  fpcrMask.dze = ones;
853  fpcrMask.ofe = ones;
854  fpcrMask.ufe = ones;
855  fpcrMask.ixe = ones;
856  fpcrMask.ide = ones;
857  fpcrMask.len = ones;
858  fpcrMask.stride = ones;
859  fpcrMask.rMode = ones;
860  fpcrMask.fz = ones;
861  fpcrMask.dn = ones;
862  fpcrMask.ahp = ones;
863  values.push_back(fpscr & fpcrMask);
864  } else if (it->index == MISCREG_FPSR) {
865  // Read FPSCR and extract FPSR value
866  FPSCR fpscr = thread->readMiscRegNoEffect(MISCREG_FPSCR);
867  const uint32_t ones = (uint32_t)(-1);
868  FPSCR fpsrMask = 0;
869  fpsrMask.ioc = ones;
870  fpsrMask.dzc = ones;
871  fpsrMask.ofc = ones;
872  fpsrMask.ufc = ones;
873  fpsrMask.ixc = ones;
874  fpsrMask.idc = ones;
875  fpsrMask.qc = ones;
876  fpsrMask.v = ones;
877  fpsrMask.c = ones;
878  fpsrMask.z = ones;
879  fpsrMask.n = ones;
880  values.push_back(fpscr & fpsrMask);
881  } else {
882  values.push_back(thread->readMiscRegNoEffect(it->index));
883  }
884  break;
885  default:
886  panic("Unknown TARMAC trace record type!");
887  }
888 
889  bool same = true;
890  if (values.size() != it->values.size()) same = false;
891 
892  uint32_t size = values.size();
893  if (size > it->values.size())
894  size = it->values.size();
895 
896  if (same) {
897  for (int i = 0; i < size; ++i) {
898  if (values[i] != it->values[i]) {
899  same = false;
900  break;
901  }
902  }
903  }
904 
905  if (!same) {
906  if (!mismatch) {
907  TarmacParserRecord::printMismatchHeader(inst, *pc);
908  mismatch = true;
909  }
910  outs << "diff> [" << it->repr << "] gem5: 0x" << std::hex;
911  for (auto v : values)
912  outs << std::setw(16) << std::setfill('0') << v;
913 
914  outs << ", TARMAC: 0x" << std::hex;
915  for (auto v : it->values)
916  outs << std::setw(16) << std::setfill('0') << v;
917  outs << std::endl;
918  }
919  }
920  destRegRecords.clear();
921 
922  if (mismatchOnPcOrOpcode && (parent.exitOnDiff ||
923  parent.exitOnInsnDiff))
924  exitSimLoop("a mismatch with the TARMAC trace has been detected "
925  "on PC or opcode", 1);
926  if (mismatch && parent.exitOnDiff)
927  exitSimLoop("a mismatch with the TARMAC trace has been detected "
928  "on data value", 1);
929 }
930 
931 const char *
932 TarmacParserRecord::TarmacParserRecordEvent::description() const
933 {
934  return "TARMAC parser record event";
935 }
936 
937 
938 void
939 TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst,
940  const PCStateBase &pc)
941 {
942  std::ostream &outs = Trace::output();
943  outs << "\nMismatch between gem5 and TARMAC trace @ " << std::dec
944  << curTick() << " ticks\n"
945  << "[seq_num: " << std::dec << instRecord.seq_num
946  << ", opcode: 0x" << std::hex << (staticInst->getEMI() & 0xffffffff)
947  << ", PC: 0x" << pc.instAddr()
948  << ", disasm: " << staticInst->disassemble(pc.instAddr()) << "]"
949  << std::endl;
950 }
951 
952 TarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread,
953  const StaticInstPtr _staticInst,
954  const PCStateBase &_pc,
955  TarmacParser& _parent,
956  const StaticInstPtr _macroStaticInst)
957  : TarmacBaseRecord(_when, _thread, _staticInst,
958  _pc, _macroStaticInst),
959  parsingStarted(false), mismatch(false),
960  mismatchOnPcOrOpcode(false), parent(_parent)
961 {
962  memReq = std::make_shared<Request>();
963  if (maxVectorLength == 0) {
964  maxVectorLength = ArmStaticInst::getCurSveVecLen<uint64_t>(_thread);
965  }
966 }
967 
968 void
970 {
971  std::ostream &outs = Trace::output();
972 
973  uint64_t written_data = 0;
974  unsigned mem_flags = 3 | ArmISA::MMU::AllowUnaligned;
975 
976  ISetState isetstate;
977 
979 
981  // A microop faulted and it was not the last microop -> advance
982  // TARMAC trace to next instruction
983  advanceTrace();
984  }
985 
986  parent.macroopInProgress = false;
987 
988  auto arm_inst = static_cast<const ArmStaticInst*>(
989  staticInst.get()
990  );
991 
992  while (advanceTrace()) {
993  switch (currRecordType) {
994 
995  case TARMAC_INST:
996  parsingStarted = true;
997  if (pc->instAddr() != instRecord.addr) {
998  if (!mismatch)
1000  outs << "diff> [PC] gem5: 0x" << std::hex << pc->instAddr()
1001  << ", TARMAC: 0x" << instRecord.addr << std::endl;
1002  mismatch = true;
1003  mismatchOnPcOrOpcode = true;
1004  }
1005 
1006  if (arm_inst->encoding() != instRecord.opcode) {
1007  if (!mismatch)
1009  outs << "diff> [opcode] gem5: 0x" << std::hex
1010  << arm_inst->encoding()
1011  << ", TARMAC: 0x" << instRecord.opcode << std::endl;
1012  mismatch = true;
1013  mismatchOnPcOrOpcode = true;
1014  }
1015 
1016  // Set the Instruction set state.
1017  isetstate = pcToISetState(*pc);
1018 
1019  if (instRecord.isetstate != isetstate &&
1020  isetstate != ISET_UNSUPPORTED) {
1021  if (!mismatch)
1023  outs << "diff> [iset_state] gem5: "
1024  << iSetStateToStr(isetstate)
1025  << ", TARMAC: "
1027  mismatch = true;
1028  }
1029 
1030  // TODO(Giacomo): add support for predicate and mode checking
1031  break;
1032 
1033  case TARMAC_REG:
1034  destRegRecords.push_back(regRecord);
1035  break;
1036 
1037  case TARMAC_MEM:
1038  if (!readMemNoEffect(memRecord.addr, (uint8_t*) &written_data,
1039  memRecord.size, mem_flags))
1040  break;
1041  if (written_data != memRecord.data) {
1042  if (!mismatch)
1044  outs << "diff> [mem(0x" << std::hex << memRecord.addr
1045  << ")] gem5: 0x" << written_data
1046  << ", TARMAC: 0x" << memRecord.data
1047  << std::endl;
1048  }
1049  break;
1050 
1051  case TARMAC_UNSUPPORTED:
1052  break;
1053 
1054  default:
1055  panic("Unknown TARMAC trace record type!");
1056  }
1057  }
1058  // We are done with the current instruction, i.e. all the corresponding
1059  // entries in the TARMAC trace have been parsed
1060  if (destRegRecords.size()) {
1064  mainEventQueue[0]->schedule(event, curTick());
1065  } else if (mismatchOnPcOrOpcode && (parent.exitOnDiff ||
1067  exitSimLoop("a mismatch with the TARMAC trace has been detected "
1068  "on PC or opcode", 1);
1069  }
1070  } else {
1071  parent.macroopInProgress = true;
1072  }
1073 }
1074 
1075 bool
1077 {
1078  std::ifstream& trace = parent.trace;
1079  trace >> std::hex; // All integer values are in hex base
1080 
1081  if (buf[0] != 'I') {
1082  trace >> buf;
1083  if (trace.eof())
1084  return false;
1085  trace >> buf >> buf;
1086  if (parent.cpuId) {
1087  assert((buf[0] == 'c') && (buf[1] == 'p') && (buf[2] == 'u'));
1088  trace >> buf;
1089  }
1090  }
1091 
1092  if (trace.eof())
1093  return false;
1094 
1095  if (buf[0] == 'I') {
1096  // Instruction trace record
1097  if (parsingStarted)
1098  return false;
1100  instRecord.taken = (buf[1] == 'T');
1101  trace >> buf;
1102  instRecord.seq_num = atoi(&buf[1]);
1103  trace >> instRecord.addr;
1104  char c = trace.peek();
1105  if (c == ':') {
1106  // Skip phys. address and _S/_NS suffix
1107  trace >> c >> buf;
1108  }
1109  trace >> instRecord.opcode;
1110  trace >> buf;
1111  switch (buf[0]) {
1112  case 'A':
1114  break;
1115  case 'T':
1117  break;
1118  case 'O':
1120  break;
1121  default:
1122  warn("Invalid TARMAC trace record (seq_num: %lld)",
1126  break;
1127  }
1128  trace.ignore(MaxLineLength, '\n');
1129  buf[0] = 0;
1130  } else if (buf[0] == 'R') {
1131  // Register trace record
1133  regRecord.values.clear();
1134  trace >> buf;
1135  strcpy(regRecord.repr, buf);
1136  if (std::tolower(buf[0]) == 'r' && isdigit(buf[1])) {
1137  // R register
1138  regRecord.type = REG_R;
1139  int base_index = atoi(&buf[1]);
1140  char* pch = strchr(buf, '_');
1141  if (pch == NULL) {
1142  regRecord.index = int_reg::usr(base_index);
1143  } else {
1144  ++pch;
1145  if (strncmp(pch, "usr", 3) == 0)
1146  regRecord.index = int_reg::usr(base_index);
1147  else if (strncmp(pch, "fiq", 3) == 0)
1148  regRecord.index = int_reg::fiq(base_index);
1149  else if (strncmp(pch, "irq", 3) == 0)
1150  regRecord.index = int_reg::irq(base_index);
1151  else if (strncmp(pch, "svc", 3) == 0)
1152  regRecord.index = int_reg::svc(base_index);
1153  else if (strncmp(pch, "mon", 3) == 0)
1154  regRecord.index = int_reg::mon(base_index);
1155  else if (strncmp(pch, "abt", 3) == 0)
1156  regRecord.index = int_reg::abt(base_index);
1157  else if (strncmp(pch, "und", 3) == 0)
1158  regRecord.index = int_reg::und(base_index);
1159  else if (strncmp(pch, "hyp", 3) == 0)
1160  regRecord.index = int_reg::hyp(base_index);
1161  }
1162  } else if (std::tolower(buf[0]) == 'x' && isdigit(buf[1])) {
1163  // X register (A64)
1164  regRecord.type = REG_X;
1165  regRecord.index = atoi(&buf[1]);
1166  } else if (std::tolower(buf[0]) == 's' && isdigit(buf[1])) {
1167  // S register
1168  regRecord.type = REG_S;
1169  regRecord.index = atoi(&buf[1]);
1170  } else if (std::tolower(buf[0]) == 'd' && isdigit(buf[1])) {
1171  // D register
1172  regRecord.type = REG_D;
1173  regRecord.index = atoi(&buf[1]);
1174  } else if (std::tolower(buf[0]) == 'q' && isdigit(buf[1])) {
1175  // Q register
1176  regRecord.type = REG_Q;
1177  regRecord.index = atoi(&buf[1]);
1178  } else if (std::tolower(buf[0]) == 'z' && isdigit(buf[1])) {
1179  // Z (SVE vector) register
1180  regRecord.type = REG_Z;
1181  regRecord.index = atoi(&buf[1]);
1182  } else if (std::tolower(buf[0]) == 'p' && isdigit(buf[1])) {
1183  // P (SVE predicate) register
1184  regRecord.type = REG_P;
1185  regRecord.index = atoi(&buf[1]);
1186  } else if (strncmp(buf, "SP_EL", 5) == 0) {
1187  // A64 stack pointer
1188  regRecord.type = REG_X;
1189  regRecord.index = int_reg::Sp0 + atoi(&buf[5]);
1190  } else if (miscRegMap.count(buf)) {
1191  // Misc. register
1194  } else {
1195  // Try match with upper case name (misc. register)
1196  std::string reg_name = buf;
1197  std::transform(reg_name.begin(), reg_name.end(), reg_name.begin(),
1198  ::tolower);
1199  if (miscRegMap.count(reg_name.c_str())) {
1201  regRecord.index = miscRegMap[reg_name.c_str()];
1202  } else {
1203  warn("Unknown register in TARMAC trace (%s).\n", buf);
1205  trace.ignore(MaxLineLength, '\n');
1206  buf[0] = 0;
1207  return true;
1208  }
1209  }
1210  if (regRecord.type == REG_Q) {
1211  trace.ignore();
1212  trace.get(buf, 17);
1213  uint64_t hi = strtoull(buf, NULL, 16);
1214  trace.get(buf, 17);
1215  uint64_t lo = strtoull(buf, NULL, 16);
1216  regRecord.values.push_back(lo);
1217  regRecord.values.push_back(hi);
1218  } else if (regRecord.type == REG_Z) {
1220  for (uint8_t i = 0; i < maxVectorLength; ++i) {
1221  uint64_t v;
1222  trace >> v;
1223  char c;
1224  trace >> c;
1225  assert(c == '_');
1226 
1227  uint64_t lsw = 0;
1228  trace >> lsw;
1229  v = (v << 32) | lsw;
1230  if (i < maxVectorLength - 1) trace >> c;
1231  regRecord.values[i] = v;
1232  }
1233  } else {
1234  // REG_P values are also parsed here
1235  uint64_t v;
1236  trace >> v;
1237  char c = trace.peek();
1238  if ((c == ':') || (c == '_')) {
1239  // 64-bit value with : or _ in the middle
1240  uint64_t lsw = 0;
1241  trace >> c >> lsw;
1242  v = (v << 32) | lsw;
1243  }
1244  regRecord.values.push_back(v);
1245  }
1246  trace.ignore(MaxLineLength, '\n');
1247  buf[0] = 0;
1248  } else if (buf[0] == 'M' && (parent.memWrCheck && buf[1] == 'W')) {
1250  memRecord.size = atoi(&buf[2]);
1251  trace >> memRecord.addr;
1252  char c = trace.peek();
1253  if (c == ':') {
1254  // Skip phys. address and _S/_NS suffix
1255  trace >> c >> buf;
1256  }
1257  uint64_t data = 0;
1258  trace >> data;
1259  c = trace.peek();
1260  if (c == '_') {
1261  // 64-bit value with _ in the middle
1262  uint64_t lsw = 0;
1263  trace >> c >> lsw;
1264  data = (data << 32) | lsw;
1265  }
1266  memRecord.data = data;
1267  trace.ignore(MaxLineLength, '\n');
1268  buf[0] = 0;
1269  } else {
1271  trace.ignore(MaxLineLength, '\n');
1272  buf[0] = 0;
1273  }
1274 
1275  return true;
1276 }
1277 
1278 bool
1280  unsigned flags)
1281 {
1282  const RequestPtr &req = memReq;
1283  auto mmu = static_cast<MMU*>(thread->getMMUPtr());
1284 
1285  req->setVirt(addr, size, flags, thread->pcState().instAddr(),
1287 
1288  // Translate to physical address
1289  Fault fault = mmu->translateAtomic(req, thread, BaseMMU::Read);
1290 
1291  // Ignore read if the address falls into the ignored range
1293  return false;
1294 
1295  // Now do the access
1296  if (fault == NoFault &&
1297  !req->getFlags().isSet(Request::NO_ACCESS)) {
1298  if (req->isLLSC() || req->isLocalAccess())
1299  // LLSCs and local accesses are ignored
1300  return false;
1301  // the translating proxy will perform the virtual to physical
1302  // translation again
1304  SETranslatingPortProxy(thread)).readBlob(addr, data, size);
1305  } else {
1306  return false;
1307  }
1308 
1309  if (fault != NoFault) {
1310  return false;
1311  }
1312 
1313  return true;
1314 }
1315 
1316 void
1318 {
1320  Addr pc;
1321  int saved_offset;
1322 
1323  trace >> std::hex; // All integer values are in hex base
1324 
1325  while (true) {
1326  saved_offset = trace.tellg();
1327  trace >> buf >> buf >> buf;
1328  if (cpuId)
1329  trace >> buf;
1330  if (buf[0] == 'I') {
1331  trace >> buf >> pc;
1332  if (pc == startPc) {
1333  // Set file pointer to the beginning of this line
1334  trace.seekg(saved_offset, std::ios::beg);
1335  return;
1336  } else {
1338  }
1339  } else {
1341  }
1342  if (trace.eof())
1343  panic("End of TARMAC trace reached before start PC\n");
1344  }
1345 }
1346 
1347 const char*
1349 {
1350  switch (isetstate) {
1351  case ISET_ARM:
1352  return "ARM (A32)";
1353  case ISET_THUMB:
1354  return "Thumb (A32)";
1355  case ISET_A64:
1356  return "A64";
1357  default:
1358  return "UNSUPPORTED";
1359  }
1360 }
1361 
1362 } // namespace Trace
1363 } // namespace gem5
gem5::ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: misc.hh:576
gem5::ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition: misc.hh:617
gem5::ArmISA::MISCREG_DCCMVAU
@ MISCREG_DCCMVAU
Definition: misc.hh:317
gem5::ArmISA::MISCREG_PMSWINC
@ MISCREG_PMSWINC
Definition: misc.hh:356
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::ArmISA::MISCREG_CSSELR_NS
@ MISCREG_CSSELR_NS
Definition: misc.hh:232
gem5::ArmISA::MISCREG_DL1DATA1
@ MISCREG_DL1DATA1
Definition: misc.hh:441
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:650
gem5::ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition: misc.hh:166
gem5::ArmISA::MISCREG_HAMAIR0
@ MISCREG_HAMAIR0
Definition: misc.hh:390
gem5::ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition: misc.hh:246
gem5::ArmISA::MISCREG_IC_IALLUIS
@ MISCREG_IC_IALLUIS
Definition: misc.hh:655
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::MISCREG_IL1DATA3_EL1
@ MISCREG_IL1DATA3_EL1
Definition: misc.hh:806
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition: misc.hh:220
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:589
gem5::ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: misc.hh:484
gem5::ArmISA::MISCREG_PMCCFILTR
@ MISCREG_PMCCFILTR
Definition: misc.hh:362
gem5::ArmISA::MISCREG_DBGWVR8_EL1
@ MISCREG_DBGWVR8_EL1
Definition: misc.hh:499
gem5::Trace::TarmacParserRecord::mismatch
bool mismatch
True if a mismatch has been detected for this instruction.
Definition: tarmac_parser.hh:193
gem5::ArmISA::MISCREG_PMCEID1
@ MISCREG_PMCEID1
Definition: misc.hh:359
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: misc.hh:326
gem5::ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition: misc.hh:449
gem5::ArmISA::MISCREG_DL1DATA3_EL1
@ MISCREG_DL1DATA3_EL1
Definition: misc.hh:810
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: misc.hh:352
gem5::ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition: misc.hh:428
gem5::SETranslatingPortProxy
Definition: se_translating_port_proxy.hh:49
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:56
gem5::ArmISA::MISCREG_MDDTRRX_EL0
@ MISCREG_MDDTRRX_EL0
Definition: misc.hh:526
gem5::Trace::TarmacParserRecord::buf
static char buf[MaxLineLength]
Buffer used for trace file parsing.
Definition: tarmac_parser.hh:177
gem5::ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition: misc.hh:96
gem5::ArmISA::MISCREG_DCCMVAC
@ MISCREG_DCCMVAC
Definition: misc.hh:313
gem5::Trace::TarmacParser::memWrCheck
bool memWrCheck
If true, memory write accesses are checked.
Definition: tarmac_parser.hh:288
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_DBGPRCR_EL1
@ MISCREG_DBGPRCR_EL1
Definition: misc.hh:532
gem5::ArmISA::MISCREG_DBGBXVR9
@ MISCREG_DBGBXVR9
Definition: misc.hh:181
gem5::ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition: misc.hh:729
gem5::ArmISA::MISCREG_AMAIR0_NS
@ MISCREG_AMAIR0_NS
Definition: misc.hh:383
gem5::ArmISA::MISCREG_DBGWVR5
@ MISCREG_DBGWVR5
Definition: misc.hh:144
gem5::ArmISA::MISCREG_VBAR_EL3
@ MISCREG_VBAR_EL3
Definition: misc.hh:743
gem5::ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: misc.hh:675
gem5::ArmISA::MISCREG_PMCCFILTR_EL0
@ MISCREG_PMCCFILTR_EL0
Definition: misc.hh:723
gem5::ArmISA::MISCREG_PMXEVTYPER_EL0
@ MISCREG_PMXEVTYPER_EL0
Definition: misc.hh:722
gem5::ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition: misc.hh:132
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::ArmISA::MISCREG_TTBCR_S
@ MISCREG_TTBCR_S
Definition: misc.hh:263
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:186
gem5::ArmISA::MISCREG_PMOVSCLR_EL0
@ MISCREG_PMOVSCLR_EL0
Definition: misc.hh:716
gem5::ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: misc.hh:334
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: misc.hh:253
gem5::ArmISA::MISCREG_PMOVSR
@ MISCREG_PMOVSR
Definition: misc.hh:355
gem5::ArmISA::MISCREG_DBGWVR15
@ MISCREG_DBGWVR15
Definition: misc.hh:154
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: misc.hh:597
gem5::ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition: misc.hh:368
gem5::ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition: misc.hh:705
gem5::ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition: misc.hh:610
gem5::ArmISA::MISCREG_DBGWVR1_EL1
@ MISCREG_DBGWVR1_EL1
Definition: misc.hh:492
warn
#define warn(...)
Definition: logging.hh:246
gem5::ArmISA::MISCREG_DC_CISW_Xt
@ MISCREG_DC_CISW_Xt
Definition: misc.hh:665
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: misc.hh:226
gem5::ArmISA::MISCREG_CONTEXTIDR_S
@ MISCREG_CONTEXTIDR_S
Definition: misc.hh:402
gem5::ArmISA::MISCREG_DBGDTRRXext
@ MISCREG_DBGDTRRXext
Definition: misc.hh:103
gem5::ArmISA::MISCREG_DC_CIVAC_Xt
@ MISCREG_DC_CIVAC_Xt
Definition: misc.hh:670
gem5::ArmISA::MISCREG_DBGWVR1
@ MISCREG_DBGWVR1
Definition: misc.hh:140
gem5::ArmISA::MISCREG_TPIDRURO_NS
@ MISCREG_TPIDRURO_NS
Definition: misc.hh:407
gem5::ArmISA::MISCREG_PMCNTENCLR
@ MISCREG_PMCNTENCLR
Definition: misc.hh:354
gem5::ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: misc.hh:682
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: misc.hh:592
gem5::ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: misc.hh:521
gem5::ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition: misc.hh:347
gem5::ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition: misc.hh:678
gem5::ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: misc.hh:298
gem5::ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition: misc.hh:802
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::ArmISA::MISCREG_CONTEXTIDR_NS
@ MISCREG_CONTEXTIDR_NS
Definition: misc.hh:401
gem5::ArmISA::MISCREG_HACR_EL2
@ MISCREG_HACR_EL2
Definition: misc.hh:591
gem5::ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition: misc.hh:771
gem5::ArmISA::MISCREG_DBGBVR15
@ MISCREG_DBGBVR15
Definition: misc.hh:122
gem5::ArmISA::MISCREG_IL1DATA0
@ MISCREG_IL1DATA0
Definition: misc.hh:436
gem5::ArmISA::MISCREG_IFSR32_EL2
@ MISCREG_IFSR32_EL2
Definition: misc.hh:642
gem5::Trace::TarmacBaseRecord::TARMAC_INST
@ TARMAC_INST
Definition: tarmac_base.hh:70
gem5::ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: misc.hh:510
gem5::ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition: misc.hh:619
gem5::ArmISA::MISCREG_ID_MMFR3_EL1
@ MISCREG_ID_MMFR3_EL1
Definition: misc.hh:550
gem5::ArmISA::MISCREG_DBGBXVR10
@ MISCREG_DBGBXVR10
Definition: misc.hh:182
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: misc.hh:702
gem5::ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition: misc.hh:416
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: misc.hh:676
gem5::ArmISA::MISCREG_CPUACTLR_EL1
@ MISCREG_CPUACTLR_EL1
Definition: misc.hh:813
gem5::ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition: misc.hh:170
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:65
gem5::ArmISA::MISCREG_VPIDR_EL2
@ MISCREG_VPIDR_EL2
Definition: misc.hh:578
gem5::ArmISA::MISCREG_AIDR_EL1
@ MISCREG_AIDR_EL1
Definition: misc.hh:574
gem5::ArmISA::MISCREG_CP15DMB
@ MISCREG_CP15DMB
Definition: misc.hh:316
gem5::ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition: misc.hh:165
gem5::ArmISA::MISCREG_DBGBXVR11
@ MISCREG_DBGBXVR11
Definition: misc.hh:183
gem5::ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition: misc.hh:210
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: misc.hh:414
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: misc.hh:478
gem5::ArmISA::MISCREG_PMINTENCLR_EL1
@ MISCREG_PMINTENCLR_EL1
Definition: misc.hh:712
gem5::Trace::TarmacParserRecord::destRegRecords
static std::list< ParserRegEntry > destRegRecords
List of records of destination registers.
Definition: tarmac_parser.hh:180
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:760
gem5::Trace::TarmacBaseRecord::REG_S
@ REG_S
Definition: tarmac_base.hh:81
gem5::ArmISA::MISCREG_ID_ISAR1_EL1
@ MISCREG_ID_ISAR1_EL1
Definition: misc.hh:553
gem5::ArmISA::MISCREG_DBGWVR9
@ MISCREG_DBGWVR9
Definition: misc.hh:148
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition: misc.hh:308
gem5::ArmISA::MISCREG_DC_CVAC_Xt
@ MISCREG_DC_CVAC_Xt
Definition: misc.hh:668
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:605
gem5::ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: misc.hh:490
gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition: misc.hh:773
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:757
gem5::ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: misc.hh:329
gem5::Trace::TarmacParserRecord::maxVectorLength
static int8_t maxVectorLength
Max.
Definition: tarmac_parser.hh:205
gem5::ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: misc.hh:691
gem5::ArmISA::MISCREG_DBGBXVR1
@ MISCREG_DBGBXVR1
Definition: misc.hh:173
gem5::mainEventQueue
std::vector< EventQueue * > mainEventQueue
Array for main event queues.
Definition: eventq.cc:57
gem5::ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition: misc.hh:237
gem5::ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition: misc.hh:234
gem5::ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition: misc.hh:163
gem5::ArmISA::MISCREG_HSTR_EL2
@ MISCREG_HSTR_EL2
Definition: misc.hh:590
gem5::ArmISA::MISCREG_PMEVCNTR5_EL0
@ MISCREG_PMEVCNTR5_EL0
Definition: misc.hh:796
gem5::ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition: misc.hh:128
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:588
gem5::ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: misc.hh:476
gem5::ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: misc.hh:688
gem5::Trace::TarmacBaseRecord::TARMAC_MEM
@ TARMAC_MEM
Definition: tarmac_base.hh:72
gem5::ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition: misc.hh:164
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: misc.hh:339
gem5::ArmISA::MISCREG_CNTHCTL
@ MISCREG_CNTHCTL
Definition: misc.hh:430
gem5::ArmISA::MISCREG_TEEHBR32_EL1
@ MISCREG_TEEHBR32_EL1
Definition: misc.hh:537
gem5::ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition: misc.hh:311
gem5::ArmISA::MISCREG_DBGWVR10
@ MISCREG_DBGWVR10
Definition: misc.hh:149
gem5::ArmISA::MISCREG_DCCSW
@ MISCREG_DCCSW
Definition: misc.hh:314
gem5::ArmISA::MISCREG_PMSELR_EL0
@ MISCREG_PMSELR_EL0
Definition: misc.hh:718
gem5::ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition: misc.hh:345
gem5::ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition: misc.hh:348
gem5::ArmISA::MISCREG_IC_IVAU_Xt
@ MISCREG_IC_IVAU_Xt
Definition: misc.hh:667
gem5::ArmISA::MISCREG_CNTP_CVAL_S
@ MISCREG_CNTP_CVAL_S
Definition: misc.hh:422
gem5::ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition: misc.hh:620
gem5::ArmISA::MISCREG_DL1DATA3
@ MISCREG_DL1DATA3
Definition: misc.hh:443
gem5::ArmISA::MISCREG_CNTKCTL
@ MISCREG_CNTKCTL
Definition: misc.hh:429
gem5::ArmISA::MISCREG_ACTLR_EL3
@ MISCREG_ACTLR_EL3
Definition: misc.hh:593
gem5::ArmISA::MISCREG_ACTLR_NS
@ MISCREG_ACTLR_NS
Definition: misc.hh:240
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:594
gem5::ArmISA::MISCREG_AMAIR1_NS
@ MISCREG_AMAIR1_NS
Definition: misc.hh:386
gem5::AddrRange::contains
bool contains(const Addr &a) const
Determine if the range contains an address.
Definition: addr_range.hh:471
gem5::Request::NO_ACCESS
@ NO_ACCESS
The request should not cause a memory access.
Definition: request.hh:146
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: misc.hh:519
gem5::ArmISA::MISCREG_DC_CSW_Xt
@ MISCREG_DC_CSW_Xt
Definition: misc.hh:664
gem5::ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition: misc.hh:123
gem5::ArmISA::MISCREG_HAMAIR1
@ MISCREG_HAMAIR1
Definition: misc.hh:391
gem5::ArmISA::MISCREG_BPIMVA
@ MISCREG_BPIMVA
Definition: misc.hh:302
gem5::ArmISA::MISCREG_SDER32_EL3
@ MISCREG_SDER32_EL3
Definition: misc.hh:595
gem5::ArmISA::MISCREG_ID_ISAR5_EL1
@ MISCREG_ID_ISAR5_EL1
Definition: misc.hh:557
gem5::ArmISA::MISCREG_DBGWVR14_EL1
@ MISCREG_DBGWVR14_EL1
Definition: misc.hh:505
gem5::ArmISA::MISCREG_ICIMVAU
@ MISCREG_ICIMVAU
Definition: misc.hh:299
gem5::Trace::TarmacParserRecord::dump
void dump() override
Definition: tarmac_parser.cc:969
gem5::ArmISA::MISCREG_DBGWVR3_EL1
@ MISCREG_DBGWVR3_EL1
Definition: misc.hh:494
gem5::ArmISA::MISCREG_TPIDRURW_S
@ MISCREG_TPIDRURW_S
Definition: misc.hh:405
gem5::Trace::TarmacBaseRecord
Definition: tarmac_base.hh:64
gem5::ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition: misc.hh:346
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: misc.hh:692
gem5::ArmISA::MISCREG_DBGVCR
@ MISCREG_DBGVCR
Definition: misc.hh:102
gem5::ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: misc.hh:621
gem5::ArmISA::MISCREG_MAIR1_NS
@ MISCREG_MAIR1_NS
Definition: misc.hh:380
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: misc.hh:600
cur_tick.hh
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:741
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: misc.hh:697
gem5::ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: misc.hh:703
gem5::Trace::InstRecord::data
union gem5::Trace::InstRecord::@336 data
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition: misc.hh:644
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: misc.hh:338
gem5::ArmISA::MISCREG_TPIDRPRW_NS
@ MISCREG_TPIDRPRW_NS
Definition: misc.hh:410
gem5::ArmISA::MISCREG_ID_MMFR0_EL1
@ MISCREG_ID_MMFR0_EL1
Definition: misc.hh:547
gem5::ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: misc.hh:202
gem5::ArmISA::MISCREG_MDRAR_EL1
@ MISCREG_MDRAR_EL1
Definition: misc.hh:528
translating_port_proxy.hh
gem5::ArmISA::MISCREG_DCISW
@ MISCREG_DCISW
Definition: misc.hh:304
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: misc.hh:247
gem5::ArmISA::MISCREG_SPSR_FIQ_AA64
@ MISCREG_SPSR_FIQ_AA64
Definition: misc.hh:632
gem5::ArmISA::MISCREG_DBGBVR7
@ MISCREG_DBGBVR7
Definition: misc.hh:114
gem5::ArmISA::MISCREG_MAIR0_NS
@ MISCREG_MAIR0_NS
Definition: misc.hh:374
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:645
gem5::ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: misc.hh:663
gem5::ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: misc.hh:516
gem5::ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: misc.hh:696
gem5::ArmISA::MISCREG_HACTLR
@ MISCREG_HACTLR
Definition: misc.hh:248
gem5::ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: misc.hh:517
gem5::ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: misc.hh:322
gem5::Trace::TarmacBaseRecord::InstEntry::opcode
ArmISA::MachInst opcode
Definition: tarmac_base.hh:94
gem5::ArmISA::MISCREG_DBGWVR13_EL1
@ MISCREG_DBGWVR13_EL1
Definition: misc.hh:504
gem5::ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition: misc.hh:530
gem5::ArmISA::MISCREG_L2MERRSR
@ MISCREG_L2MERRSR
Definition: misc.hh:451
gem5::ArmISA::MISCREG_DBGDTRRXint
@ MISCREG_DBGDTRRXint
Definition: misc.hh:100
gem5::ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: misc.hh:483
gem5::ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition: misc.hh:342
gem5::ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: misc.hh:711
gem5::ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: misc.hh:683
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: misc.hh:209
gem5::ArmISA::MISCREG_TPIDR_EL3
@ MISCREG_TPIDR_EL3
Definition: misc.hh:752
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:746
gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: misc.hh:567
gem5::ArmISA::MISCREG_DBGBVR1_EL1
@ MISCREG_DBGBVR1_EL1
Definition: misc.hh:460
gem5::Trace::InstRecord::thread
ThreadContext * thread
Definition: insttracer.hh:68
gem5::ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: misc.hh:330
gem5::ArmISA::MISCREG_IL1DATA0_EL1
@ MISCREG_IL1DATA0_EL1
Definition: misc.hh:803
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: misc.hh:611
gem5::ArmISA::MISCREG_ID_ISAR2_EL1
@ MISCREG_ID_ISAR2_EL1
Definition: misc.hh:554
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: misc.hh:291
gem5::ArmISA::MISCREG_DBGBVR2
@ MISCREG_DBGBVR2
Definition: misc.hh:109
gem5::ArmISA::MISCREG_DFSR_S
@ MISCREG_DFSR_S
Definition: misc.hh:271
gem5::ArmISA::MISCREG_ID_ISAR3_EL1
@ MISCREG_ID_ISAR3_EL1
Definition: misc.hh:555
gem5::ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition: misc.hh:159
gem5::ArmISA::MISCREG_AMAIR_EL3
@ MISCREG_AMAIR_EL3
Definition: misc.hh:734
gem5::ArmISA::MISCREG_TTBR0_NS
@ MISCREG_TTBR0_NS
Definition: misc.hh:256
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: misc.hh:224
gem5::ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: misc.hh:488
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:570
gem5::Trace::TarmacParser::trace
std::ifstream trace
TARMAC trace file.
Definition: tarmac_parser.hh:268
gem5::ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition: misc.hh:351
gem5::ArmISA::MISCREG_ID_ISAR4_EL1
@ MISCREG_ID_ISAR4_EL1
Definition: misc.hh:556
gem5::ArmISA::MISCREG_CNTP_TVAL_NS
@ MISCREG_CNTP_TVAL_NS
Definition: misc.hh:424
gem5::ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: misc.hh:487
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: misc.hh:219
gem5::ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition: misc.hh:168
gem5::ArmISA::MISCREG_MAIR_EL3
@ MISCREG_MAIR_EL3
Definition: misc.hh:733
gem5::Trace::TarmacBaseRecord::REG_Z
@ REG_Z
Definition: tarmac_base.hh:81
std::vector< uint64_t >
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: misc.hh:188
gem5::ArmISA::MISCREG_DBGWVR11_EL1
@ MISCREG_DBGWVR11_EL1
Definition: misc.hh:502
gem5::ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: misc.hh:367
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition: misc.hh:727
gem5::ArmISA::MISCREG_PMUSERENR
@ MISCREG_PMUSERENR
Definition: misc.hh:364
gem5::ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition: misc.hh:319
gem5::ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition: misc.hh:371
gem5::ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: misc.hh:689
gem5::Trace::TarmacBaseRecord::ISET_A64
@ ISET_A64
Definition: tarmac_base.hh:77
gem5::ArmISA::MMU::AllowUnaligned
@ AllowUnaligned
Definition: mmu.hh:109
gem5::ArmISA::MISCREG_PRRR_S
@ MISCREG_PRRR_S
Definition: misc.hh:372
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: misc.hh:222
gem5::ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition: misc.hh:310
gem5::ArmISA::MISCREG_CNTP_CTL_NS
@ MISCREG_CNTP_CTL_NS
Definition: misc.hh:418
gem5::ArmISA::MISCREG_DBGBVR6
@ MISCREG_DBGBVR6
Definition: misc.hh:113
gem5::RefCountingPtr::get
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:227
gem5::ArmISA::MISCREG_PMSWINC_EL0
@ MISCREG_PMSWINC_EL0
Definition: misc.hh:717
gem5::ArmISA::MISCREG_DFSR_NS
@ MISCREG_DFSR_NS
Definition: misc.hh:270
gem5::ArmISA::MISCREG_DL1DATA0_EL1
@ MISCREG_DL1DATA0_EL1
Definition: misc.hh:807
gem5::ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: misc.hh:680
gem5::ArmISA::MISCREG_PMCCNTR_EL0
@ MISCREG_PMCCNTR_EL0
Definition: misc.hh:721
gem5::ArmISA::MISCREG_BPIALLIS
@ MISCREG_BPIALLIS
Definition: misc.hh:294
gem5::ArmISA::MISCREG_DL1DATA2
@ MISCREG_DL1DATA2
Definition: misc.hh:442
gem5::ArmISA::MISCREG_ADFSR_NS
@ MISCREG_ADFSR_NS
Definition: misc.hh:276
gem5::ArmISA::MISCREG_DL1DATA2_EL1
@ MISCREG_DL1DATA2_EL1
Definition: misc.hh:809
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: misc.hh:565
gem5::ArmISA::MISCREG_L2ACTLR_EL1
@ MISCREG_L2ACTLR_EL1
Definition: misc.hh:812
gem5::ArmISA::MISCREG_DBGBXVR15
@ MISCREG_DBGBXVR15
Definition: misc.hh:187
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition: misc.hh:656
gem5::ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition: misc.hh:707
faults.hh
gem5::ArmISA::MISCREG_ACTLR_S
@ MISCREG_ACTLR_S
Definition: misc.hh:241
gem5::ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition: misc.hh:756
gem5::ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition: misc.hh:755
gem5::ArmISA::MISCREG_MAIR1_S
@ MISCREG_MAIR1_S
Definition: misc.hh:381
sim_exit.hh
gem5::ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: misc.hh:512
gem5::ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition: misc.hh:162
gem5::ArmISA::MISCREG_TPIDRRO_EL0
@ MISCREG_TPIDRRO_EL0
Definition: misc.hh:750
gem5::ArmISA::MISCREG_DBGBVR15_EL1
@ MISCREG_DBGBVR15_EL1
Definition: misc.hh:474
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: misc.hh:704
gem5::ArmISA::MISCREG_DBGBVR3
@ MISCREG_DBGBVR3
Definition: misc.hh:110
gem5::ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: misc.hh:200
gem5::Trace::TarmacParser::cpuId
bool cpuId
If true, the trace format includes the CPU id.
Definition: tarmac_parser.hh:294
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: misc.hh:217
gem5::Trace::TarmacBaseRecord::InstEntry::isetstate
ISetState isetstate
Definition: tarmac_base.hh:96
gem5::ArmISA::MISCREG_OSDLR_EL1
@ MISCREG_OSDLR_EL1
Definition: misc.hh:531
gem5::ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition: misc.hh:138
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: misc.hh:545
gem5::exitSimLoop
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
Definition: sim_events.cc:88
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: misc.hh:203
gem5::ArmISA::MISCREG_L2CTLR_EL1
@ MISCREG_L2CTLR_EL1
Definition: misc.hh:735
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: misc.hh:607
gem5::ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition: misc.hh:129
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::ArmISA::MISCREG_DBGBXVR4
@ MISCREG_DBGBXVR4
Definition: misc.hh:176
gem5::ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: misc.hh:701
gem5::RefCountingPtr< StaticInst >
packet.hh
gem5::ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: misc.hh:513
gem5::ArmISA::MISCREG_DBGCLAIMCLR_EL1
@ MISCREG_DBGCLAIMCLR_EL1
Definition: misc.hh:534
gem5::ArmISA::MISCREG_ID_PFR1_EL1
@ MISCREG_ID_PFR1_EL1
Definition: misc.hh:544
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: misc.hh:252
gem5::ArmISA::MISCREG_DBGWVR9_EL1
@ MISCREG_DBGWVR9_EL1
Definition: misc.hh:500
gem5::Trace::TarmacParser::ignoredAddrRange
AddrRange ignoredAddrRange
Ignored addresses (ignored if empty).
Definition: tarmac_parser.hh:291
gem5::ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition: misc.hh:158
gem5::TranslatingPortProxy
This proxy attempts to translate virtual addresses using the TLBs.
Definition: translating_port_proxy.hh:60
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: misc.hh:221
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:769
gem5::ArmISA::MISCREG_HTCR
@ MISCREG_HTCR
Definition: misc.hh:264
gem5::ArmISA::MISCREG_DBGBXVR3
@ MISCREG_DBGBXVR3
Definition: misc.hh:175
gem5::Trace::TarmacParser::macroopInProgress
bool macroopInProgress
True if a macroop is currently in progress.
Definition: tarmac_parser.hh:300
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: misc.hh:104
gem5::ArmISA::MISCREG_CPUMERRSR_EL1
@ MISCREG_CPUMERRSR_EL1
Definition: misc.hh:815
gem5::Trace::TarmacParserRecord::iSetStateToStr
const char * iSetStateToStr(ISetState isetstate) const
Returns the string representation of an instruction set state.
Definition: tarmac_parser.cc:1348
gem5::ArmISA::irq
Bitfield< 1 > irq
Definition: misc_types.hh:331
gem5::ArmISA::MISCREG_OSECCR_EL1
@ MISCREG_OSECCR_EL1
Definition: misc.hh:458
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition: misc.hh:731
gem5::ArmISA::MISCREG_DBGDSAR
@ MISCREG_DBGDSAR
Definition: misc.hh:192
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: misc.hh:218
gem5::ArmISA::cc_reg::Nz
constexpr RegId Nz(CCRegClass, _NzIdx)
gem5::Trace::TarmacBaseRecord::ISET_ARM
@ ISET_ARM
Definition: tarmac_base.hh:77
gem5::ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition: misc.hh:459
gem5::ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: misc.hh:333
mmu.hh
gem5::ArmISA::MISCREG_VTCR
@ MISCREG_VTCR
Definition: misc.hh:265
gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent
Event triggered to check the value of the destination registers.
Definition: tarmac_parser.hh:76
gem5::ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition: misc.hh:238
gem5::ArmISA::MISCREG_DBGWVR12
@ MISCREG_DBGWVR12
Definition: misc.hh:151
gem5::ArmISA::MISCREG_DBGAUTHSTATUS_EL1
@ MISCREG_DBGAUTHSTATUS_EL1
Definition: misc.hh:535
gem5::ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: misc.hh:522
gem5::VegaISA::c
Bitfield< 2 > c
Definition: pagetable.hh:63
gem5::Trace::TarmacParserRecord::instRecord
static ParserInstEntry instRecord
Buffer for instruction trace records.
Definition: tarmac_parser.hh:165
gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2
@ MISCREG_CNTHP_TVAL_EL2
Definition: misc.hh:777
gem5::ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition: misc.hh:250
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:774
gem5::ArmISA::MISCREG_ID_PFR0_EL1
@ MISCREG_ID_PFR0_EL1
Definition: misc.hh:543
gem5::Trace::TarmacParserRecord::mismatchOnPcOrOpcode
bool mismatchOnPcOrOpcode
True if a mismatch has been detected for this instruction on PC or opcode.
Definition: tarmac_parser.hh:199
gem5::ArmISA::MISCREG_PAR_S
@ MISCREG_PAR_S
Definition: misc.hh:297
gem5::ArmISA::MISCREG_CPUMERRSR
@ MISCREG_CPUMERRSR
Definition: misc.hh:450
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: misc.hh:434
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:615
gem5::Trace::TarmacBaseRecord::RegEntry::values
std::vector< uint64_t > values
Definition: tarmac_base.hh:117
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: misc.hh:332
gem5::ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition: misc.hh:340
gem5::ArmISA::MISCREG_DBGCLAIMSET_EL1
@ MISCREG_DBGCLAIMSET_EL1
Definition: misc.hh:533
gem5::ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition: misc.hh:124
gem5::ArmISA::MISCREG_FCSEIDR
@ MISCREG_FCSEIDR
Definition: misc.hh:399
gem5::ArmISA::MISCREG_DBGBVR14_EL1
@ MISCREG_DBGBVR14_EL1
Definition: misc.hh:473
gem5::ArmISA::MISCREG_DBGDCCINT
@ MISCREG_DBGDCCINT
Definition: misc.hh:98
gem5::ArmISA::MISCREG_DBGDRAR
@ MISCREG_DBGDRAR
Definition: misc.hh:171
gem5::Trace::TarmacBaseRecord::TARMAC_REG
@ TARMAC_REG
Definition: tarmac_base.hh:71
gem5::ArmISA::MISCREG_PMEVCNTR1_EL0
@ MISCREG_PMEVCNTR1_EL0
Definition: misc.hh:792
gem5::ArmISA::MISCREG_L2ECTLR_EL1
@ MISCREG_L2ECTLR_EL1
Definition: misc.hh:736
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:123
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: misc.hh:155
gem5::ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition: misc.hh:739
gem5::Trace::TarmacBaseRecord::ISetState
ISetState
ARM instruction set state.
Definition: tarmac_base.hh:77
gem5::ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition: misc.hh:131
gem5::ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition: misc.hh:133
gem5::Trace::TarmacParserRecord::memRecord
static ParserMemEntry memRecord
Buffer for memory access trace records (stores only).
Definition: tarmac_parser.hh:171
gem5::ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition: misc.hh:169
gem5::ArmISA::MISCREG_DBGBVR5_EL1
@ MISCREG_DBGBVR5_EL1
Definition: misc.hh:464
gem5::ArmISA::MISCREG_HMAIR1
@ MISCREG_HMAIR1
Definition: misc.hh:389
gem5::ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition: misc.hh:307
gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: misc.hh:563
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: misc.hh:509
gem5::ArmISA::MISCREG_TPIDRURW_NS
@ MISCREG_TPIDRURW_NS
Definition: misc.hh:404
gem5::Trace::TarmacParserRecord::ParserRegEntry::repr
char repr[16]
Definition: tarmac_parser.hh:121
gem5::ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition: misc.hh:126
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:580
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:823
gem5::Trace::TarmacBaseRecord::REG_Q
@ REG_Q
Definition: tarmac_base.hh:81
gem5::Trace::TarmacBaseRecord::ISET_THUMB
@ ISET_THUMB
Definition: tarmac_base.hh:77
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: misc.hh:223
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::Trace::TarmacParserRecord::parent
TarmacParser & parent
Definition: tarmac_parser.hh:208
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::ArmISA::MISCREG_CP15ISB
@ MISCREG_CP15ISB
Definition: misc.hh:300
gem5::ArmISA::MISCREG_MDDTRTX_EL0
@ MISCREG_MDDTRTX_EL0
Definition: misc.hh:525
gem5::ArmISA::MISCREG_ID_MMFR2_EL1
@ MISCREG_ID_MMFR2_EL1
Definition: misc.hh:549
gem5::ArmISA::MISCREG_PMCNTENSET
@ MISCREG_PMCNTENSET
Definition: misc.hh:353
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:251
gem5::VecRegContainer::as
VecElem * as()
View interposers.
Definition: vec_reg.hh:189
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: misc.hh:596
gem5::ArmISA::cc_reg::V
constexpr RegId V(CCRegClass, _VIdx)
gem5::ArmISA::MISCREG_CBAR_EL1
@ MISCREG_CBAR_EL1
Definition: misc.hh:817
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: misc.hh:225
gem5::ArmISA::MISCREG_MDCCINT_EL1
@ MISCREG_MDCCINT_EL1
Definition: misc.hh:454
gem5::ArmISA::MISCREG_DBGAUTHSTATUS
@ MISCREG_DBGAUTHSTATUS
Definition: misc.hh:195
gem5::ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition: misc.hh:137
gem5::ArmISA::MISCREG_DBGWVR13
@ MISCREG_DBGWVR13
Definition: misc.hh:152
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: misc.hh:395
gem5::ArmISA::MISCREG_DBGBVR4_EL1
@ MISCREG_DBGBVR4_EL1
Definition: misc.hh:463
gem5::ArmISA::MISCREG_HACR
@ MISCREG_HACR
Definition: misc.hh:254
gem5::ArmISA::MISCREG_DL1DATA1_EL1
@ MISCREG_DL1DATA1_EL1
Definition: misc.hh:808
gem5::ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: misc.hh:726
gem5::ArmISA::MISCREG_DBGWVR2_EL1
@ MISCREG_DBGWVR2_EL1
Definition: misc.hh:493
gem5::ArmISA::MISCREG_OSDTRRX_EL1
@ MISCREG_OSDTRRX_EL1
Definition: misc.hh:455
gem5::ArmISA::MISCREG_BPIALL
@ MISCREG_BPIALL
Definition: misc.hh:301
gem5::ArmISA::MISCREG_DL1DATA4_EL1
@ MISCREG_DL1DATA4_EL1
Definition: misc.hh:811
gem5::ArmISA::MISCREG_CPUECTLR_EL1
@ MISCREG_CPUECTLR_EL1
Definition: misc.hh:814
gem5::ArmISA::MISCREG_DBGWVR6
@ MISCREG_DBGWVR6
Definition: misc.hh:145
gem5::Trace::TarmacParserRecord::MaxLineLength
static const int MaxLineLength
Definition: tarmac_parser.hh:127
gem5::ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition: misc.hh:160
gem5::ArmISA::MISCREG_PMSELR
@ MISCREG_PMSELR
Definition: misc.hh:357
gem5::ArmISA::MISCREG_REVIDR_EL1
@ MISCREG_REVIDR_EL1
Definition: misc.hh:542
gem5::ArmISA::MISCREG_SPSR_IRQ_AA64
@ MISCREG_SPSR_IRQ_AA64
Definition: misc.hh:629
gem5::ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition: misc.hh:415
gem5::Trace::InstRecord::staticInst
StaticInstPtr staticInst
Definition: insttracer.hh:71
gem5::ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition: misc.hh:732
gem5::ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition: misc.hh:540
gem5::ArmISA::MISCREG_DBGBXVR7
@ MISCREG_DBGBXVR7
Definition: misc.hh:179
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: misc.hh:661
gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2
@ MISCREG_CNTHP_CVAL_EL2
Definition: misc.hh:776
gem5::Trace::TarmacBaseRecord::REG_MISC
@ REG_MISC
Definition: tarmac_base.hh:81
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:585
gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: misc.hh:566
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmISA::MISCREG_PMEVTYPER2_EL0
@ MISCREG_PMEVTYPER2_EL0
Definition: misc.hh:799
gem5::ArmISA::MISCREG_DBGBVR10_EL1
@ MISCREG_DBGBVR10_EL1
Definition: misc.hh:469
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: misc.hh:228
gem5::ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: misc.hh:511
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::ArmISA::MISCREG_HTTBR
@ MISCREG_HTTBR
Definition: misc.hh:448
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::MISCREG_CSSELR_S
@ MISCREG_CSSELR_S
Definition: misc.hh:233
gem5::ArmISA::MISCREG_CNTHP_TVAL
@ MISCREG_CNTHP_TVAL
Definition: misc.hh:433
gem5::ArmISA::MISCREG_DBGWVR0_EL1
@ MISCREG_DBGWVR0_EL1
Definition: misc.hh:491
gem5::ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: misc.hh:293
gem5::Trace::TarmacParserRecord::regRecord
static ParserRegEntry regRecord
Buffer for register trace records.
Definition: tarmac_parser.hh:168
gem5::ArmISA::MISCREG_CNTPS_CVAL_EL1
@ MISCREG_CNTPS_CVAL_EL1
Definition: misc.hh:772
gem5::ArmISA::MISCREG_PMXEVCNTR_EL0
@ MISCREG_PMXEVCNTR_EL0
Definition: misc.hh:724
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: misc.hh:235
port_proxy.hh
gem5::ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition: misc.hh:344
gem5::ArmISA::MISCREG_DBGCLAIMSET
@ MISCREG_DBGCLAIMSET
Definition: misc.hh:193
gem5::ArmISA::MISCREG_HMAIR0
@ MISCREG_HMAIR0
Definition: misc.hh:388
gem5::Trace::TarmacBaseRecord::REG_P
@ REG_P
Definition: tarmac_base.hh:81
gem5::ArmISA::MISCREG_ADFSR_S
@ MISCREG_ADFSR_S
Definition: misc.hh:277
gem5::ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: misc.hh:508
gem5::ArmISA::MISCREG_DCCIMVAC
@ MISCREG_DCCIMVAC
Definition: misc.hh:318
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:583
gem5::Trace::TarmacBaseRecord::REG_D
@ REG_D
Definition: tarmac_base.hh:81
gem5::ArmISA::MISCREG_DBGBXVR8
@ MISCREG_DBGBXVR8
Definition: misc.hh:180
gem5::ArmISA::MISCREG_DBGVCR32_EL2
@ MISCREG_DBGVCR32_EL2
Definition: misc.hh:527
gem5::Trace::TarmacParser::exitOnDiff
bool exitOnDiff
If true, the simulation is stopped as the first mismatch is detected.
Definition: tarmac_parser.hh:279
gem5::ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition: misc.hh:320
gem5::ArmISA::MISCREG_MVFR1_EL1
@ MISCREG_MVFR1_EL1
Definition: misc.hh:560
gem5::ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition: misc.hh:134
gem5::ArmISA::MISCREG_ID_ISAR0_EL1
@ MISCREG_ID_ISAR0_EL1
Definition: misc.hh:552
gem5::ArmISA::MISCREG_DBGBVR8
@ MISCREG_DBGBVR8
Definition: misc.hh:115
gem5::ArmISA::MMU::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) override
Definition: mmu.hh:245
gem5::ArmISA::MISCREG_PMINTENSET
@ MISCREG_PMINTENSET
Definition: misc.hh:365
gem5::ArmISA::MISCREG_TEEHBR
@ MISCREG_TEEHBR
Definition: misc.hh:201
gem5::ArmISA::MISCREG_ACTLR_EL2
@ MISCREG_ACTLR_EL2
Definition: misc.hh:586
gem5::ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: misc.hh:618
gem5::ArmISA::MISCREG_DFAR_NS
@ MISCREG_DFAR_NS
Definition: misc.hh:285
tarmac_parser.hh
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: misc.hh:541
gem5::ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: misc.hh:681
gem5::ArmISA::MISCREG_DBGWVR11
@ MISCREG_DBGWVR11
Definition: misc.hh:150
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:626
gem5::ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: misc.hh:666
gem5::ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: misc.hh:628
gem5::ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: misc.hh:662
gem5::ArmISA::MISCREG_DACR_NS
@ MISCREG_DACR_NS
Definition: misc.hh:267
gem5::ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition: misc.hh:397
gem5::ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition: misc.hh:742
gem5::ArmISA::MISCREG_HADFSR
@ MISCREG_HADFSR
Definition: misc.hh:281
gem5::ArmISA::MISCREG_DBGWVR14
@ MISCREG_DBGWVR14
Definition: misc.hh:153
gem5::ArmISA::MISCREG_ID_ISAR6_EL1
@ MISCREG_ID_ISAR6_EL1
Definition: misc.hh:558
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: misc.hh:215
gem5::ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition: misc.hh:206
gem5::Trace::TarmacBaseRecord::REG_R
@ REG_R
Definition: tarmac_base.hh:81
gem5::Trace::TarmacParserRecord::ParserInstEntry::seq_num
uint64_t seq_num
Definition: tarmac_parser.hh:115
gem5::ArmISA::MISCREG_DBGDEVID1
@ MISCREG_DBGDEVID1
Definition: misc.hh:197
flags
uint8_t flags
Definition: helpers.cc:66
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: misc.hh:479
static_inst.hh
gem5::ArmISA::MISCREG_IFSR_NS
@ MISCREG_IFSR_NS
Definition: misc.hh:273
gem5::Trace::TarmacBaseRecord::REG_X
@ REG_X
Definition: tarmac_base.hh:81
gem5::ArmISA::MISCREG_PMCNTENSET_EL0
@ MISCREG_PMCNTENSET_EL0
Definition: misc.hh:714
gem5::Trace::output
std::ostream & output()
Get the ostream from the current global logger.
Definition: trace.cc:79
gem5::ArmISA::MISCREG_DBGBXVR14
@ MISCREG_DBGBXVR14
Definition: misc.hh:186
gem5::ArmISA::MISCREG_DBGBVR2_EL1
@ MISCREG_DBGBVR2_EL1
Definition: misc.hh:461
gem5::ArmISA::MISCREG_CNTHP_CTL_EL2
@ MISCREG_CNTHP_CTL_EL2
Definition: misc.hh:775
gem5::ArmISA::MISCREG_DL1DATA0
@ MISCREG_DL1DATA0
Definition: misc.hh:440
gem5::ArmISA::MISCREG_DBGPRCR
@ MISCREG_DBGPRCR
Definition: misc.hh:191
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: misc.hh:213
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:564
gem5::ArmISA::MISCREG_CNTV_CVAL
@ MISCREG_CNTV_CVAL
Definition: misc.hh:427
gem5::ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition: misc.hh:761
gem5::X86ISA::usr
Bitfield< 16 > usr
Definition: misc.hh:802
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: misc.hh:290
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:571
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:613
gem5::ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition: misc.hh:744
gem5::ArmISA::MISCREG_CSSELR_EL1
@ MISCREG_CSSELR_EL1
Definition: misc.hh:575
gem5::ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition: misc.hh:394
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: misc.hh:208
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition: misc.hh:135
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: misc.hh:335
gem5::ArmISA::MISCREG_PAR_NS
@ MISCREG_PAR_NS
Definition: misc.hh:296
gem5::ArmISA::MISCREG_DBGDEVID2
@ MISCREG_DBGDEVID2
Definition: misc.hh:196
gem5::ArmISA::MISCREG_DBGBVR13
@ MISCREG_DBGBVR13
Definition: misc.hh:120
gem5::ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition: misc.hh:377
gem5::ArmISA::cc_reg::C
constexpr RegId C(CCRegClass, _CIdx)
gem5::ArmISA::MISCREG_PMEVCNTR4_EL0
@ MISCREG_PMEVCNTR4_EL0
Definition: misc.hh:795
gem5::ArmISA::MISCREG_CNTHP_CVAL
@ MISCREG_CNTHP_CVAL
Definition: misc.hh:432
gem5::ArmISA::MISCREG_DBGOSDLR
@ MISCREG_DBGOSDLR
Definition: misc.hh:190
gem5::ArmISA::MISCREG_DBGBXVR5
@ MISCREG_DBGBXVR5
Definition: misc.hh:177
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:475
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:188
gem5::ArmISA::MISCREG_PMCEID1_EL0
@ MISCREG_PMCEID1_EL0
Definition: misc.hh:720
gem5::ArmISA::MISCREG_IL1DATA1
@ MISCREG_IL1DATA1
Definition: misc.hh:437
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: misc.hh:759
gem5::ArmISA::MISCREG_MVFR2_EL1
@ MISCREG_MVFR2_EL1
Definition: misc.hh:561
gem5::ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition: misc.hh:643
gem5::ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: misc.hh:673
gem5::ArmISA::MISCREG_RMR_EL3
@ MISCREG_RMR_EL3
Definition: misc.hh:745
gem5::ArmISA::MISCREG_MAIR0_S
@ MISCREG_MAIR0_S
Definition: misc.hh:375
gem5::ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition: misc.hh:289
gem5::Trace::TarmacParserRecord::memReq
RequestPtr memReq
Request for memory write checks.
Definition: tarmac_parser.hh:202
gem5::ArmISA::MISCREG_HTPIDR
@ MISCREG_HTPIDR
Definition: misc.hh:412
gem5::ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition: misc.hh:635
gem5::Trace::TarmacBaseRecord::ISET_UNSUPPORTED
@ ISET_UNSUPPORTED
Definition: tarmac_base.hh:78
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:569
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: misc.hh:672
gem5::ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition: misc.hh:156
gem5::ArmISA::MISCREG_TTBR0_S
@ MISCREG_TTBR0_S
Definition: misc.hh:257
gem5::ArmISA::MISCREG_TPIDR_EL2
@ MISCREG_TPIDR_EL2
Definition: misc.hh:751
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: misc.hh:699
gem5::ArmISA::MISCREG_DBGWVR12_EL1
@ MISCREG_DBGWVR12_EL1
Definition: misc.hh:503
gem5::ArmISA::MISCREG_IC_IALLU
@ MISCREG_IC_IALLU
Definition: misc.hh:657
gem5::ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: misc.hh:482
gem5::ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: misc.hh:480
full_system.hh
gem5::Trace::InstRecord::pc
std::unique_ptr< PCStateBase > pc
Definition: insttracer.hh:72
gem5::Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:279
gem5::ArmISA::MISCREG_DBGWVR4
@ MISCREG_DBGWVR4
Definition: misc.hh:143
gem5::ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: misc.hh:684
gem5::ArmISA::MISCREG_ID_AFR0_EL1
@ MISCREG_ID_AFR0_EL1
Definition: misc.hh:546
gem5::ArmISA::MISCREG_SDER
@ MISCREG_SDER
Definition: misc.hh:245
gem5::ArmISA::fiq
Bitfield< 2 > fiq
Definition: misc_types.hh:330
gem5::ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: misc.hh:485
gem5::ArmISA::MISCREG_AFSR0_EL3
@ MISCREG_AFSR0_EL3
Definition: misc.hh:647
gem5::ArmISA::MISCREG_DBGBVR14
@ MISCREG_DBGBVR14
Definition: misc.hh:121
gem5::ArmISA::MISCREG_DLR_EL0
@ MISCREG_DLR_EL0
Definition: misc.hh:625
gem5::ArmISA::MISCREG_CBAR
@ MISCREG_CBAR
Definition: misc.hh:447
gem5::ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition: misc.hh:127
gem5::ArmISA::MISCREG_DBGWVR3
@ MISCREG_DBGWVR3
Definition: misc.hh:142
gem5::ArmISA::MISCREG_PMINTENCLR
@ MISCREG_PMINTENCLR
Definition: misc.hh:366
gem5::ArmISA::MISCREG_SPSR_UND_AA64
@ MISCREG_SPSR_UND_AA64
Definition: misc.hh:631
gem5::ArmISA::cc_reg::Ge
constexpr RegId Ge(CCRegClass, _GeIdx)
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: misc.hh:324
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::ArmISA::MISCREG_IL1DATA2_EL1
@ MISCREG_IL1DATA2_EL1
Definition: misc.hh:805
gem5::ArmISA::MISCREG_MDDTR_EL0
@ MISCREG_MDDTR_EL0
Definition: misc.hh:524
gem5::ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: misc.hh:789
gem5::Trace::TarmacParserRecord::readMemNoEffect
bool readMemNoEffect(Addr addr, uint8_t *data, unsigned size, unsigned flags)
Performs a memory access to read the value written by a previous write.
Definition: tarmac_parser.cc:1279
gem5::ArmISA::MISCREG_SPSR_ABT_AA64
@ MISCREG_SPSR_ABT_AA64
Definition: misc.hh:630
gem5::ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: misc.hh:507
gem5::ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition: misc.hh:309
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: misc.hh:230
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: misc.hh:633
gem5::Trace::TarmacParser
Tarmac Parser: this tracer parses an existing Tarmac trace and it diffs it with gem5 simulation statu...
Definition: tarmac_parser.hh:216
gem5::ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition: misc.hh:161
gem5::ArmISA::MISCREG_RMR
@ MISCREG_RMR
Definition: misc.hh:396
gem5::ArmISA::MISCREG_VBAR_NS
@ MISCREG_VBAR_NS
Definition: misc.hh:393
gem5::ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: misc.hh:518
gem5::ArmISA::MISCREG_IL1DATA1_EL1
@ MISCREG_IL1DATA1_EL1
Definition: misc.hh:804
gem5::ArmISA::MISCREG_DCIMVAC
@ MISCREG_DCIMVAC
Definition: misc.hh:303
gem5::VegaISA::v
Bitfield< 0 > v
Definition: pagetable.hh:65
gem5::StaticInst::getEMI
virtual uint64_t getEMI() const
Definition: static_inst.hh:236
gem5::ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition: misc.hh:306
gem5::Trace::InstRecord::size
Addr size
The size of the memory request.
Definition: insttracer.hh:87
gem5::ArmISA::MISCREG_DBGBVR9_EL1
@ MISCREG_DBGBVR9_EL1
Definition: misc.hh:468
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: misc.hh:207
gem5::ArmISA::MISCREG_DBGWVR7_EL1
@ MISCREG_DBGWVR7_EL1
Definition: misc.hh:498
gem5::ArmISA::MISCREG_DBGOSECCR
@ MISCREG_DBGOSECCR
Definition: misc.hh:106
gem5::ArmISA::MISCREG_TEECR
@ MISCREG_TEECR
Definition: misc.hh:199
gem5::ArmISA::lo
Bitfield< 19, 16 > lo
Definition: misc_types.hh:141
gem5::ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: misc.hh:331
gem5::ArmISA::MISCREG_DBGBXVR13
@ MISCREG_DBGBXVR13
Definition: misc.hh:185
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:249
gem5::ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition: misc.hh:286
gem5::ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition: misc.hh:343
gem5::StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:60
gem5::ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition: misc.hh:321
gem5::ArmISA::MISCREG_PMXEVCNTR
@ MISCREG_PMXEVCNTR
Definition: misc.hh:363
gem5::ArmISA::MISCREG_IFSR_S
@ MISCREG_IFSR_S
Definition: misc.hh:274
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: misc.hh:262
gem5::ArmISA::MISCREG_AFSR1_EL3
@ MISCREG_AFSR1_EL3
Definition: misc.hh:648
gem5::ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition: misc.hh:312
gem5::ArmISA::MISCREG_AIFSR_NS
@ MISCREG_AIFSR_NS
Definition: misc.hh:279
gem5::Trace::TarmacBaseRecord::InstEntry::taken
bool taken
Definition: tarmac_base.hh:92
gem5::ArmISA::MISCREG_CNTHP_CTL
@ MISCREG_CNTHP_CTL
Definition: misc.hh:431
gem5::ArmISA::MISCREG_L2MERRSR_EL1
@ MISCREG_L2MERRSR_EL1
Definition: misc.hh:816
gem5::ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition: misc.hh:677
gem5::Trace::TarmacParserRecord::miscRegMap
static MiscRegMap miscRegMap
Definition: tarmac_parser.hh:184
gem5::ArmISA::MISCREG_CNTP_CVAL_EL0
@ MISCREG_CNTP_CVAL_EL0
Definition: misc.hh:758
gem5::ArmISA::MISCREG_TPIDRURO_S
@ MISCREG_TPIDRURO_S
Definition: misc.hh:408
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: misc.hh:72
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: misc.hh:687
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: misc.hh:229
gem5::ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition: misc.hh:606
gem5::ArmISA::MISCREG_L2ACTLR
@ MISCREG_L2ACTLR
Definition: misc.hh:446
gem5::ArmISA::MISCREG_DBGBVR12
@ MISCREG_DBGBVR12
Definition: misc.hh:119
gem5::ArmISA::MISCREG_DSPSR_EL0
@ MISCREG_DSPSR_EL0
Definition: misc.hh:624
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: misc.hh:327
gem5::ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition: misc.hh:349
gem5::ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: misc.hh:690
gem5::ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition: misc.hh:125
gem5::ArmISA::MISCREG_DBGWVR8
@ MISCREG_DBGWVR8
Definition: misc.hh:147
gem5::ArmISA::MISCREG_AMAIR0_S
@ MISCREG_AMAIR0_S
Definition: misc.hh:384
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: misc.hh:477
gem5::ArmISA::MISCREG_DBGBVR8_EL1
@ MISCREG_DBGBVR8_EL1
Definition: misc.hh:467
gem5::ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: misc.hh:514
gem5::ArmISA::MISCREG_PMEVCNTR3_EL0
@ MISCREG_PMEVCNTR3_EL0
Definition: misc.hh:794
gem5::Trace::TarmacBaseRecord::pcToISetState
static ISetState pcToISetState(const PCStateBase &pc)
Returns the Instruction Set State according to the current PCState.
Definition: tarmac_base.cc:103
core.hh
static_inst.hh
gem5::ArmISA::MISCREG_CNTP_CVAL_NS
@ MISCREG_CNTP_CVAL_NS
Definition: misc.hh:421
gem5::Trace::TarmacParserRecord::parsingStarted
bool parsingStarted
True if a TARMAC instruction record has already been parsed for this instruction.
Definition: tarmac_parser.hh:190
gem5::Trace::InstRecord::addr
Addr addr
The address that was accessed.
Definition: insttracer.hh:86
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: misc.hh:189
gem5::ArmISA::MISCREG_DBGWVR2
@ MISCREG_DBGWVR2
Definition: misc.hh:141
gem5::ArmISA::MISCREG_TPIDRPRW_S
@ MISCREG_TPIDRPRW_S
Definition: misc.hh:411
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::MISCREG_AIFSR_S
@ MISCREG_AIFSR_S
Definition: misc.hh:280
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:244
gem5::ArmISA::MISCREG_ID_MMFR1_EL1
@ MISCREG_ID_MMFR1_EL1
Definition: misc.hh:548
gem5::ArmISA::MISCREG_ESR_EL3
@ MISCREG_ESR_EL3
Definition: misc.hh:649
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:627
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: misc.hh:212
gem5::ArmISA::MISCREG_CP15DSB
@ MISCREG_CP15DSB
Definition: misc.hh:315
gem5::ArmISA::MISCREG_DBGWVR4_EL1
@ MISCREG_DBGWVR4_EL1
Definition: misc.hh:495
gem5::ArmISA::MISCREG_PMEVTYPER1_EL0
@ MISCREG_PMEVTYPER1_EL0
Definition: misc.hh:798
gem5::ArmISA::MISCREG_DBGBXVR0
@ MISCREG_DBGBXVR0
Definition: misc.hh:172
gem5::ArmISA::MISCREG_DBGDTRTXext
@ MISCREG_DBGDTRTXext
Definition: misc.hh:105
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:579
gem5::ArmISA::MISCREG_PMEVTYPER3_EL0
@ MISCREG_PMEVTYPER3_EL0
Definition: misc.hh:800
gem5::Trace::TarmacParser::startPc
Addr startPc
Tracing starts when the PC gets this value for the first time (ignored if 0x0).
Definition: tarmac_parser.hh:274
gem5::ArmISA::MISCREG_DBGWFAR
@ MISCREG_DBGWFAR
Definition: misc.hh:101
gem5::ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: misc.hh:791
gem5::ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition: misc.hh:708
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: misc.hh:211
gem5::ArmISA::MISCREG_NMRR_S
@ MISCREG_NMRR_S
Definition: misc.hh:378
gem5::ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: misc.hh:481
gem5::ArmISA::MISCREG_OSDTRTX_EL1
@ MISCREG_OSDTRTX_EL1
Definition: misc.hh:457
gem5::ArmISA::MISCREG_DBGWVR15_EL1
@ MISCREG_DBGWVR15_EL1
Definition: misc.hh:506
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:623
gem5::ArmISA::MISCREG_DBGBVR10
@ MISCREG_DBGBVR10
Definition: misc.hh:117
gem5::ArmISA::MISCREG_DBGBVR7_EL1
@ MISCREG_DBGBVR7_EL1
Definition: misc.hh:466
gem5::ArmISA::MISCREG_HVBAR
@ MISCREG_HVBAR
Definition: misc.hh:398
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition: misc.hh:636
se_translating_port_proxy.hh
gem5::ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition: misc.hh:361
gem5::ArmISA::MISCREG_HSR
@ MISCREG_HSR
Definition: misc.hh:283
gem5::ArmISA::MISCREG_DBGBXVR6
@ MISCREG_DBGBXVR6
Definition: misc.hh:178
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition: misc.hh:227
gem5::ArmISA::MISCREG_DBGDEVID0
@ MISCREG_DBGDEVID0
Definition: misc.hh:198
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:818
gem5::ArmISA::MISCREG_ELR_EL3
@ MISCREG_ELR_EL3
Definition: misc.hh:634
gem5::ArmISA::MISCREG_DACR_S
@ MISCREG_DACR_S
Definition: misc.hh:268
gem5::Trace::TarmacParser::advanceTraceToStartPc
void advanceTraceToStartPc()
Helper function to advance the trace up to startPc.
Definition: tarmac_parser.cc:1317
gem5::ArmISA::MISCREG_IFAR_NS
@ MISCREG_IFAR_NS
Definition: misc.hh:288
gem5::ArmISA::MISCREG_CNTP_TVAL_S
@ MISCREG_CNTP_TVAL_S
Definition: misc.hh:425
gem5::ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition: misc.hh:577
gem5::ArmISA::MISCREG_TTBR1_NS
@ MISCREG_TTBR1_NS
Definition: misc.hh:259
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:622
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::Trace::TarmacBaseRecord::InstEntry::addr
Addr addr
Definition: tarmac_base.hh:93
gem5::ArmISA::MISCREG_DC_IVAC_Xt
@ MISCREG_DC_IVAC_Xt
Definition: misc.hh:658
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:754
gem5::ArmISA::MISCREG_DBGBVR0
@ MISCREG_DBGBVR0
Definition: misc.hh:107
gem5::ArmISA::MISCREG_TPIDR_EL0
@ MISCREG_TPIDR_EL0
Definition: misc.hh:749
gem5::ArmISA::MISCREG_PMCEID0_EL0
@ MISCREG_PMCEID0_EL0
Definition: misc.hh:719
gem5::ArmISA::MISCREG_PMCEID0
@ MISCREG_PMCEID0
Definition: misc.hh:358
gem5::Trace::TarmacBaseRecord::TARMAC_UNSUPPORTED
@ TARMAC_UNSUPPORTED
Definition: tarmac_base.hh:73
gem5::ArmISA::MISCREG_DC_CVAU_Xt
@ MISCREG_DC_CVAU_Xt
Definition: misc.hh:669
gem5::Trace::TarmacBaseRecord::RegEntry::type
RegType type
Definition: tarmac_base.hh:114
std::list
STL list class.
Definition: stl.hh:51
gem5::ArmISA::MISCREG_TTBR1_S
@ MISCREG_TTBR1_S
Definition: misc.hh:260
gem5::ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition: misc.hh:157
gem5::ArmISA::MISCREG_DBGBVR6_EL1
@ MISCREG_DBGBVR6_EL1
Definition: misc.hh:465
gem5::ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: misc.hh:323
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: misc.hh:674
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:587
gem5::ArmISA::MISCREG_RAMINDEX
@ MISCREG_RAMINDEX
Definition: misc.hh:445
gem5::ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition: misc.hh:638
gem5::Trace::TarmacParser::exitOnInsnDiff
bool exitOnInsnDiff
If true, the simulation is stopped as the first mismatch is detected on PC or opcode.
Definition: tarmac_parser.hh:285
gem5::ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: misc.hh:695
gem5::ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: misc.hh:336
gem5::ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition: misc.hh:305
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: misc.hh:598
gem5::ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: misc.hh:486
gem5::ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition: misc.hh:710
gem5::ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: misc.hh:700
gem5::ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: misc.hh:337
gem5::ArmISA::MISCREG_PMEVTYPER4_EL0
@ MISCREG_PMEVTYPER4_EL0
Definition: misc.hh:801
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:652
gem5::ArmISA::MISCREG_DBGBVR4
@ MISCREG_DBGBVR4
Definition: misc.hh:111
gem5::ArmISA::MISCREG_FAR_EL3
@ MISCREG_FAR_EL3
Definition: misc.hh:654
gem5::ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: misc.hh:685
gem5::ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: misc.hh:515
gem5::ArmISA::MISCREG_DBGBVR12_EL1
@ MISCREG_DBGBVR12_EL1
Definition: misc.hh:471
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:562
gem5::ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition: misc.hh:97
gem5::ArmISA::MISCREG_DBGCLAIMCLR
@ MISCREG_DBGCLAIMCLR
Definition: misc.hh:194
gem5::ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition: misc.hh:167
gem5::Trace::TarmacBaseRecord::RegEntry::index
RegIndex index
Definition: tarmac_base.hh:115
gem5::ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition: misc.hh:653
gem5::ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: misc.hh:325
gem5::ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: misc.hh:686
gem5::ArmISA::MISCREG_FPEXC32_EL2
@ MISCREG_FPEXC32_EL2
Definition: misc.hh:646
gem5::ArmISA::MISCREG_PMCCNTR
@ MISCREG_PMCCNTR
Definition: misc.hh:360
gem5::ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition: misc.hh:426
gem5::ArmISA::MISCREG_CNTP_CTL_S
@ MISCREG_CNTP_CTL_S
Definition: misc.hh:419
gem5::ArmISA::MISCREG_PMUSERENR_EL0
@ MISCREG_PMUSERENR_EL0
Definition: misc.hh:725
gem5::Trace::TarmacParserRecord::advanceTrace
bool advanceTrace()
Advances the TARMAC trace up to the next instruction, register, or memory access record.
Definition: tarmac_parser.cc:1076
gem5::ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition: misc.hh:350
gem5::ArmISA::MISCREG_ACTLR_EL1
@ MISCREG_ACTLR_EL1
Definition: misc.hh:582
gem5::ArmISA::MISCREG_CCSIDR_EL1
@ MISCREG_CCSIDR_EL1
Definition: misc.hh:572
gem5::ArmISA::MISCREG_DBGBXVR12
@ MISCREG_DBGBXVR12
Definition: misc.hh:184
gem5::ArmISA::MISCREG_HPFAR
@ MISCREG_HPFAR
Definition: misc.hh:292
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:640
gem5::ArmISA::MISCREG_TPIDR_EL1
@ MISCREG_TPIDR_EL1
Definition: misc.hh:748
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: misc.hh:216
gem5::ArmISA::MISCREG_DBGWVR7
@ MISCREG_DBGWVR7
Definition: misc.hh:146
gem5::ArmISA::MISCREG_DACR32_EL2
@ MISCREG_DACR32_EL2
Definition: misc.hh:612
gem5::ArmISA::MMU
Definition: mmu.hh:60
gem5::ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: misc.hh:679
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:737
gem5::ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition: misc.hh:706
gem5::ArmISA::MISCREG_AMAIR1_S
@ MISCREG_AMAIR1_S
Definition: misc.hh:387
gem5::ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: misc.hh:698
gem5::ArmISA::MISCREG_PMCNTENCLR_EL0
@ MISCREG_PMCNTENCLR_EL0
Definition: misc.hh:715
gem5::ArmISA::MISCREG_IL1DATA2
@ MISCREG_IL1DATA2
Definition: misc.hh:438
gem5::ArmISA::MISCREG_DBGWVR6_EL1
@ MISCREG_DBGWVR6_EL1
Definition: misc.hh:497
gem5::ArmISA::MISCREG_DBGBVR11
@ MISCREG_DBGBVR11
Definition: misc.hh:118
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: misc.hh:242
gem5::ArmISA::MISCREG_IL1DATA3
@ MISCREG_IL1DATA3
Definition: misc.hh:439
gem5::ArmISA::MISCREG_ID_MMFR4_EL1
@ MISCREG_ID_MMFR4_EL1
Definition: misc.hh:551
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: misc.hh:456
gem5::ArmISA::MISCREG_DBGWVR10_EL1
@ MISCREG_DBGWVR10_EL1
Definition: misc.hh:501
gem5::ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: misc.hh:489
gem5::ArmISA::MISCREG_PMEVCNTR2_EL0
@ MISCREG_PMEVCNTR2_EL0
Definition: misc.hh:793
gem5::ArmISA::MISCREG_TEECR32_EL1
@ MISCREG_TEECR32_EL1
Definition: misc.hh:536
gem5::ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition: misc.hh:130
gem5::ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: misc.hh:740
thread_context.hh
gem5::Trace::TarmacParserRecord::currRecordType
static TarmacRecordType currRecordType
Type of last parsed record.
Definition: tarmac_parser.hh:174
gem5::ArmISA::MISCREG_DC_ISW_Xt
@ MISCREG_DC_ISW_Xt
Definition: misc.hh:659
gem5::Trace::InstRecord::flags
unsigned flags
The flags that were assigned to the request.
Definition: insttracer.hh:88
gem5::ArmISA::MISCREG_HAIFSR
@ MISCREG_HAIFSR
Definition: misc.hh:282
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: misc.hh:568
gem5::ArmISA::MISCREG_CLIDR_EL1
@ MISCREG_CLIDR_EL1
Definition: misc.hh:573
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: misc.hh:529
gem5::ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: misc.hh:660
gem5::ArmISA::MISCREG_DBGBVR13_EL1
@ MISCREG_DBGBVR13_EL1
Definition: misc.hh:472
gem5::ArmISA::MISCREG_DBGDTRTXint
@ MISCREG_DBGDTRTXint
Definition: misc.hh:99
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: misc.hh:214
gem5::ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition: misc.hh:136
gem5::ArmISA::MISCREG_PMCR_EL0
@ MISCREG_PMCR_EL0
Definition: misc.hh:713
gem5::ArmISA::MISCREG_MVFR0_EL1
@ MISCREG_MVFR0_EL1
Definition: misc.hh:559
gem5::ArmISA::MISCREG_PMEVTYPER0_EL0
@ MISCREG_PMEVTYPER0_EL0
Definition: misc.hh:797
gem5::ArmISA::MISCREG_DBGBVR5
@ MISCREG_DBGBVR5
Definition: misc.hh:112
gem5::ArmISA::MISCREG_DBGBVR1
@ MISCREG_DBGBVR1
Definition: misc.hh:108
gem5::ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition: misc.hh:341
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: misc.hh:328
gem5::ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: misc.hh:694
gem5::ArmISA::MISCREG_DBGBXVR2
@ MISCREG_DBGBXVR2
Definition: misc.hh:174
gem5::ArmISA::MISCREG_DBGWVR0
@ MISCREG_DBGWVR0
Definition: misc.hh:139
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:602
gem5::ArmISA::MISCREG_DL1DATA4
@ MISCREG_DL1DATA4
Definition: misc.hh:444
gem5::ArmISA::MISCREG_DBGBVR3_EL1
@ MISCREG_DBGBVR3_EL1
Definition: misc.hh:462
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::MISCREG_L2ECTLR
@ MISCREG_L2ECTLR
Definition: misc.hh:369
gem5::ArmISA::MISCREG_DBGBVR9
@ MISCREG_DBGBVR9
Definition: misc.hh:116
gem5::ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: misc.hh:693
gem5::ArmISA::MISCREG_DBGBVR11_EL1
@ MISCREG_DBGBVR11_EL1
Definition: misc.hh:470
gem5::ArmISA::MISCREG_MDCCSR_EL0
@ MISCREG_MDCCSR_EL0
Definition: misc.hh:523
gem5::ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition: misc.hh:709
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: misc.hh:762
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: misc.hh:671
gem5::ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: misc.hh:520
gem5::Trace::TarmacParserRecord::printMismatchHeader
static void printMismatchHeader(const StaticInstPtr inst, const PCStateBase &pc)
Print a mismatch header containing the instruction fields as reported by gem5.
Definition: tarmac_parser.cc:939
gem5::ArmISA::MISCREG_DBGWVR5_EL1
@ MISCREG_DBGWVR5_EL1
Definition: misc.hh:496

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