gem5
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mem
translating_port_proxy.hh
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/*
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* Copyright (c) 2011 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_TRANSLATING_PORT_PROXY_HH__
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#define __MEM_TRANSLATING_PORT_PROXY_HH__
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#include <functional>
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#include "
arch/generic/mmu.hh
"
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#include "
mem/port_proxy.hh
"
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namespace
gem5
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{
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class
ThreadContext;
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class
TranslatingPortProxy
:
public
PortProxy
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{
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protected
:
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ThreadContext
*
_tc
;
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Request::Flags
flags
;
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virtual
bool
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fixupRange
(
const
TranslationGen::Range
&range,
BaseMMU::Mode
mode
)
const
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{
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return
false
;
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}
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bool
tryOnBlob
(
BaseMMU::Mode
mode
,
TranslationGenPtr
gen,
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std::function<
void
(
const
TranslationGen::Range
&)> func)
const
;
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public
:
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TranslatingPortProxy
(
ThreadContext
*tc,
Request::Flags
_flags=0);
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bool
tryReadBlob
(
Addr
addr
,
void
*
p
, uint64_t size)
const override
;
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bool
tryWriteBlob
(
Addr
addr
,
const
void
*
p
, uint64_t size)
const override
;
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bool
tryMemsetBlob
(
Addr
address, uint8_t
v
, uint64_t size)
const override
;
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};
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}
// namespace gem5
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#endif
//__MEM_TRANSLATING_PORT_PROXY_HH__
gem5::BaseMMU::Mode
Mode
Definition
mmu.hh:56
gem5::Flags< FlagsType >
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition
port_proxy.hh:87
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
guest_abi.test.cc:41
gem5::TranslatingPortProxy
This proxy attempts to translate virtual addresses using the TLBs.
Definition
translating_port_proxy.hh:61
gem5::TranslatingPortProxy::_tc
ThreadContext * _tc
Definition
translating_port_proxy.hh:63
gem5::TranslatingPortProxy::TranslatingPortProxy
TranslatingPortProxy(ThreadContext *tc, Request::Flags _flags=0)
Definition
translating_port_proxy.cc:57
gem5::TranslatingPortProxy::tryReadBlob
bool tryReadBlob(Addr addr, void *p, uint64_t size) const override
Version of tryReadblob that translates virt->phys and deals with page boundries.
Definition
translating_port_proxy.cc:89
gem5::TranslatingPortProxy::tryMemsetBlob
bool tryMemsetBlob(Addr address, uint8_t v, uint64_t size) const override
Fill size bytes starting at addr with byte value val.
Definition
translating_port_proxy.cc:114
gem5::TranslatingPortProxy::fixupRange
virtual bool fixupRange(const TranslationGen::Range &range, BaseMMU::Mode mode) const
Definition
translating_port_proxy.hh:67
gem5::TranslatingPortProxy::tryWriteBlob
bool tryWriteBlob(Addr addr, const void *p, uint64_t size) const override
Version of tryWriteBlob that translates virt->phys and deals with page boundries.
Definition
translating_port_proxy.cc:101
gem5::TranslatingPortProxy::flags
Request::Flags flags
Definition
translating_port_proxy.hh:64
gem5::TranslatingPortProxy::tryOnBlob
bool tryOnBlob(BaseMMU::Mode mode, TranslationGenPtr gen, std::function< void(const TranslationGen::Range &)> func) const
Definition
translating_port_proxy.cc:63
mmu.hh
gem5::ArmISA::v
Bitfield< 28 > v
Definition
misc_types.hh:54
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition
misc_types.hh:74
gem5::MipsISA::p
Bitfield< 0 > p
Definition
pra_constants.hh:326
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition
types.hh:84
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition
types.hh:147
gem5::TranslationGenPtr
std::unique_ptr< TranslationGen > TranslationGenPtr
Definition
translation_gen.hh:131
port_proxy.hh
PortProxy Object Declaration.
gem5::TranslationGen::Range
This structure represents a single, contiguous translation, or carries information about whatever fau...
Definition
translation_gen.hh:70
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