gem5  v22.0.0.2
vec_pred_reg.test.cc
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37 
38 #include <gtest/gtest.h>
39 
41 #include "base/str.hh"
42 
43 using namespace gem5;
44 
46 {
47  constexpr size_t size = 4;
49 
50  vec.reset();
51 
52  for (auto idx = 0; idx < size; idx++) {
53  ASSERT_FALSE(vec[idx]);
54  }
55 }
56 
58 {
59  constexpr size_t size = 4;
61 
62  vec.set();
63 
64  for (auto idx = 0; idx < size; idx++) {
65  ASSERT_TRUE(vec[idx]);
66  }
67 }
68 
69 template <bool T>
70 class TwoDifferentVecPredRegsBase : public testing::Test
71 {
72  protected:
73  static constexpr ssize_t size = 4;
76 
77  void
78  SetUp() override
79  {
80  // Initializing with:
81  // 0,1,0,1
82  for (auto idx = 0; idx < size; idx++) {
83  pred1[idx] = (idx % 2);
84  }
85 
86  // Initializing with:
87  // 1,0,1,0
88  for (auto idx = 0; idx < size; idx++) {
89  pred2[idx] = !(idx % 2);
90  }
91  }
92 };
93 
96 
97 // Testing operator=
99 {
100  pred2 = pred1;
101 
102  for (auto idx = 0; idx < size; idx++) {
103  ASSERT_EQ(pred2[idx], idx % 2);
104  }
105 }
106 
107 // Testing operator==
109 {
110  // Equality check
111  ASSERT_TRUE(pred1 == pred1);
112  ASSERT_TRUE(pred2 == pred2);
113  ASSERT_FALSE(pred1 == pred2);
114 }
115 
116 // Testing operator!=
118 {
119  // Inequality check
120  ASSERT_FALSE(pred1 != pred1);
121  ASSERT_FALSE(pred2 != pred2);
122  ASSERT_TRUE(pred1 != pred2);
123 }
124 
125 // Testing operator<<
127 {
128  {
129  std::ostringstream stream;
130  stream << pred1;
131  ASSERT_EQ(stream.str(), "[0 1 0 1]");
132  }
133 
134  {
135  std::ostringstream stream;
136  stream << pred2;
137  ASSERT_EQ(stream.str(), "[1 0 1 0]");
138  }
139 }
140 
141 // Testing ParseParam
143 {
144  ParseParam<decltype(pred1)> parser;
145  parser.parse("1111", pred1);
146  parser.parse("0000", pred2);
147 
148  for (auto idx = 0; idx < size; idx++) {
149  ASSERT_EQ(pred1[idx], 1);
150  ASSERT_EQ(pred2[idx], 0);
151  }
152 }
153 
154 // Testing ShowParam
156 {
157  ShowParam<decltype(pred1)> parser;
158 
159  {
160  std::stringstream ss;
161  parser.show(ss, pred1);
162  ASSERT_EQ(ss.str(), "0101");
163  }
164 
165  {
166  std::stringstream ss;
167  parser.show(ss, pred2);
168  ASSERT_EQ(ss.str(), "1010");
169  }
170 }
171 
172 // Testing VecPredReg view as uint8_t
173 // pred1 is 0101
174 // -> pred1_view[0] = false
175 // -> pred1_view[1] = true
176 // -> pred1_view[2] = false
177 // -> pred1_view[3] = true
178 // pred2 is 1010
179 // -> pred2_view[0] = true
180 // -> pred2_view[1] = false
181 // -> pred2_view[2] = true
182 // -> pred2_view[3] = false
184 {
185  auto pred1_view = pred1.as<uint8_t>();
186  auto pred2_view = pred2.as<uint8_t>();
187 
188  for (auto idx = 0; idx < size; idx++) {
189  ASSERT_EQ(pred1_view[idx], idx % 2);
190  ASSERT_EQ(pred2_view[idx], !(idx % 2));
191  }
192 }
193 
194 // Testing VecPredReg view as uint16_t
195 // pred1 is 0101
196 // -> pred1_view[0] = false
197 // -> pred1_view[1] = false
198 // pred2 is 1010
199 // -> pred2_view[0] = true
200 // -> pred2_view[1] = true
202 {
203  auto pred1_view = pred1.as<uint16_t>();
204  auto pred2_view = pred2.as<uint16_t>();
205 
206  for (auto idx = 0; idx < size / sizeof(uint16_t); idx++) {
207  ASSERT_FALSE(pred1_view[idx]);
208  ASSERT_TRUE(pred2_view[idx]);
209  }
210 }
211 
212 // Testing VecPredReg view as uint32_t
213 // pred1 is 0101
214 // -> pred1_view[0] = false
215 // pred2 is 1010
216 // -> pred2_view[0] = true
218 {
219  auto pred1_view = pred1.as<uint32_t>();
220  auto pred2_view = pred2.as<uint32_t>();
221 
222  ASSERT_FALSE(pred1_view[0]);
223  ASSERT_TRUE(pred2_view[0]);
224 }
225 
226 // Testing VecPredReg view as uint8_t
227 // pred1 is 0101
228 // -> pred1_view[0] = false
229 // -> pred1_view[1] = true
230 // -> pred1_view[2] = false
231 // -> pred1_view[3] = true
232 // pred2 is 1010
233 // -> pred2_view[0] = true
234 // -> pred2_view[1] = false
235 // -> pred2_view[2] = true
236 // -> pred2_view[3] = false
238 {
239  auto pred1_view = pred1.as<uint8_t>();
240  auto pred2_view = pred2.as<uint8_t>();
241 
242  for (auto idx = 0; idx < size; idx++) {
243  ASSERT_EQ(pred1_view[idx], idx % 2);
244  ASSERT_EQ(pred2_view[idx], !(idx % 2));
245  }
246 }
247 
248 // Testing VecPredReg view as uint16_t
249 // pred1 is 0101
250 // -> pred1_view[0] = false
251 // -> pred1_view[1] = true
252 // -> pred1_view[2] = false
253 // -> pred1_view[3] = true
254 // pred2 is 1010
255 // -> pred2_view[0] = true
256 // -> pred2_view[1] = false
257 // -> pred2_view[2] = true
258 // -> pred2_view[3] = false
260 {
261  auto pred1_view = pred1.as<uint16_t>();
262  auto pred2_view = pred2.as<uint16_t>();
263 
264  for (auto idx = 0; idx < size; idx++) {
265  ASSERT_EQ(pred1_view[idx], idx % 2);
266  ASSERT_EQ(pred2_view[idx], !(idx % 2));
267  }
268 }
269 
270 // Testing VecPredReg view as uint32_t
271 // pred1 is 0101
272 // -> pred1_view[0] = false
273 // -> pred1_view[1] = true
274 // -> pred1_view[2] = false
275 // -> pred1_view[3] = true
276 // pred2 is 1010
277 // -> pred2_view[0] = true
278 // -> pred2_view[1] = false
279 // -> pred2_view[2] = true
280 // -> pred2_view[3] = false
282 {
283  auto pred1_view = pred1.as<uint32_t>();
284  auto pred2_view = pred2.as<uint32_t>();
285 
286  for (auto idx = 0; idx < size; idx++) {
287  ASSERT_EQ(pred1_view[idx], idx % 2);
288  ASSERT_EQ(pred2_view[idx], !(idx % 2));
289  }
290 }
gem5::VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:54
gem5::ArmISA::set
Bitfield< 12, 11 > set
Definition: misc_types.hh:703
gem5::ShowParam::show
static void show(std::ostream &os, const T &value)
Definition: serialize_handlers.hh:127
gem5::ShowParam
Definition: serialize_handlers.hh:125
TwoDifferentVecPredRegsBase::pred2
VecPredRegContainer< size, T > pred2
Definition: vec_pred_reg.test.cc:75
str.hh
TEST_F
TEST_F(TwoDifferentVecPredRegs, Assignment)
Definition: vec_pred_reg.test.cc:98
gem5::VecPredRegT
Predicate register view.
Definition: vec_pred_reg.hh:73
gem5::statistics::reset
void reset()
Definition: statistics.cc:310
ss
std::stringstream ss
Definition: trace.test.cc:45
vec_pred_reg.hh
TwoDifferentVecPredRegsBase::SetUp
void SetUp() override
Definition: vec_pred_reg.test.cc:78
TwoDifferentVecPredRegsBase::pred1
VecPredRegContainer< size, T > pred1
Definition: vec_pred_reg.test.cc:74
gem5::PowerISA::vec
Bitfield< 25 > vec
Definition: misc.hh:108
TwoDifferentVecPredRegsBase
Definition: vec_pred_reg.test.cc:70
gem5::ParseParam
Definition: serialize_handlers.hh:78
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
TEST
TEST(VecPredReg, reset)
Definition: vec_pred_reg.test.cc:45

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