gem5  v21.1.0.2
vgic.cc
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37 
38 #include "dev/arm/vgic.hh"
39 
40 #include "arch/arm/interrupts.hh"
41 #include "base/trace.hh"
42 #include "cpu/base.hh"
43 #include "debug/Checkpoint.hh"
44 #include "debug/VGIC.hh"
45 #include "dev/arm/base_gic.hh"
46 #include "mem/packet.hh"
47 #include "mem/packet_access.hh"
48 
49 namespace gem5
50 {
51 
53  : PioDevice(p), gicvIIDR(p.gicv_iidr), platform(p.platform),
54  gic(p.gic), vcpuAddr(p.vcpu_addr), hvAddr(p.hv_addr),
55  pioDelay(p.pio_delay), maintInt(p.maint_int)
56 {
57  for (int x = 0; x < VGIC_CPU_MAX; x++) {
59  [this, x]{ processPostVIntEvent(x); },
60  "Post VInterrupt to CPU");
61  maintIntPosted[x] = false;
62  vIntPosted[x] = false;
63  }
64  assert(sys->threads.numRunning() <= VGIC_CPU_MAX);
65 }
66 
68 {
69  for (int x = 0; x < VGIC_CPU_MAX; x++)
70  delete postVIntEvent[x];
71 }
72 
73 Tick
75 {
76  Addr addr = pkt->getAddr();
77 
78  if (addr >= vcpuAddr && addr < vcpuAddr + GICV_SIZE)
79  return readVCpu(pkt);
80  else if (addr >= hvAddr && addr < hvAddr + GICH_REG_SIZE)
81  return readCtrl(pkt);
82  else
83  panic("Read to unknown address %#x\n", pkt->getAddr());
84 }
85 
86 Tick
88 {
89  Addr addr = pkt->getAddr();
90 
91  if (addr >= vcpuAddr && addr < vcpuAddr + GICV_SIZE)
92  return writeVCpu(pkt);
93  else if (addr >= hvAddr && addr < hvAddr + GICH_REG_SIZE)
94  return writeCtrl(pkt);
95  else
96  panic("Write to unknown address %#x\n", pkt->getAddr());
97 }
98 
99 Tick
101 {
102  Addr daddr = pkt->getAddr() - vcpuAddr;
103 
104  ContextID ctx_id = pkt->req->contextId();
105  assert(ctx_id < VGIC_CPU_MAX);
106  struct vcpuIntData *vid = &vcpuData[ctx_id];
107 
108  DPRINTF(VGIC, "VGIC VCPU read register %#x\n", daddr);
109 
110  switch (daddr) {
111  case GICV_CTLR:
112  pkt->setLE<uint32_t>(vid->vctrl);
113  break;
114  case GICV_IAR: {
115  int i = findHighestPendingLR(vid);
116  if (i < 0 || !vid->vctrl.En) {
117  pkt->setLE<uint32_t>(1023); // "No int" marker
118  } else {
119  ListReg *lr = &vid->LR[i];
120 
121  pkt->setLE<uint32_t>(lr->VirtualID |
122  (((int)lr->CpuID) << 10));
123  // We don't support auto-EOI of HW interrupts via real GIC!
124  // Fortunately, KVM doesn't use this. How about Xen...? Ulp!
125  if (lr->HW)
126  panic("VGIC does not support 'HW' List Register feature (LR %#x)!\n",
127  *lr);
128  lr->State = LR_ACTIVE;
129  DPRINTF(VGIC, "Consumed interrupt %d (cpu%d) from LR%d (EOI%d)\n",
130  lr->VirtualID, lr->CpuID, i, lr->EOI);
131  }
132  } break;
133  case GICV_IIDR:
134  pkt->setLE<uint32_t>(gicvIIDR);
135  break;
136  default:
137  panic("VGIC VCPU read of bad address %#x\n", daddr);
138  }
139 
140  updateIntState(ctx_id);
141 
142  pkt->makeAtomicResponse();
143  return pioDelay;
144 }
145 
146 Tick
148 {
149  Addr daddr = pkt->getAddr() - hvAddr;
150 
151  ContextID ctx_id = pkt->req->contextId();
152 
153  DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr);
154 
155  /* Munge the address: 0-0xfff is the usual space banked by requestor CPU.
156  * Anything > that is 0x200-sized slices of 'per CPU' regs.
157  */
158  if (daddr & ~0x1ff) {
159  ctx_id = (daddr >> 9);
160  if (ctx_id > 8)
161  panic("VGIC: Weird unbanked hv ctrl address %#x!\n", daddr);
162  daddr &= ~0x1ff;
163  }
164  assert(ctx_id < VGIC_CPU_MAX);
165  struct vcpuIntData *vid = &vcpuData[ctx_id];
166 
167  switch (daddr) {
168  case GICH_HCR:
169  pkt->setLE<uint32_t>(vid->hcr);
170  break;
171 
172  case GICH_VTR:
173  pkt->setLE<uint32_t>(0x44000000 | (NUM_LR - 1));
174  break;
175 
176  case GICH_VMCR:
177  pkt->setLE<uint32_t>(
178  ((uint32_t)vid->VMPriMask << 27) |
179  ((uint32_t)vid->VMBP << 21) |
180  ((uint32_t)vid->VMABP << 18) |
181  ((uint32_t)vid->VEM << 9) |
182  ((uint32_t)vid->VMCBPR << 4) |
183  ((uint32_t)vid->VMFiqEn << 3) |
184  ((uint32_t)vid->VMAckCtl << 2) |
185  ((uint32_t)vid->VMGrp1En << 1) |
186  ((uint32_t)vid->VMGrp0En << 0)
187  );
188  break;
189 
190  case GICH_MISR:
191  pkt->setLE<uint32_t>(getMISR(vid));
192  break;
193 
194  case GICH_EISR0:
195  pkt->setLE<uint32_t>(vid->eisr & 0xffffffff);
196  break;
197 
198  case GICH_EISR1:
199  pkt->setLE<uint32_t>(vid->eisr >> 32);
200  break;
201 
202  case GICH_ELSR0: {
203  uint32_t bm = 0;
204  for (int i = 0; i < ((NUM_LR < 32) ? NUM_LR : 32); i++) {
205  if (!vid->LR[i].State)
206  bm |= 1 << i;
207  }
208  pkt->setLE<uint32_t>(bm);
209  } break;
210 
211  case GICH_ELSR1: {
212  uint32_t bm = 0;
213  for (int i = 32; i < NUM_LR; i++) {
214  if (!vid->LR[i].State)
215  bm |= 1 << (i-32);
216  }
217  pkt->setLE<uint32_t>(bm);
218  } break;
219 
220  case GICH_APR0:
221  warn_once("VGIC GICH_APR read!\n");
222  pkt->setLE<uint32_t>(0);
223  break;
224 
225  case GICH_LR0:
226  case GICH_LR1:
227  case GICH_LR2:
228  case GICH_LR3:
229  pkt->setLE<uint32_t>(vid->LR[(daddr - GICH_LR0) >> 2]);
230  break;
231 
232  default:
233  panic("VGIC HVCtrl read of bad address %#x\n", daddr);
234  }
235 
236  pkt->makeAtomicResponse();
237  return pioDelay;
238 }
239 
240 Tick
242 {
243  Addr daddr = pkt->getAddr() - vcpuAddr;
244 
245  ContextID ctx_id = pkt->req->contextId();
246  assert(ctx_id < VGIC_CPU_MAX);
247  struct vcpuIntData *vid = &vcpuData[ctx_id];
248 
249  DPRINTF(VGIC, "VGIC VCPU write register %#x <= %#x\n",
250  daddr, pkt->getLE<uint32_t>());
251 
252  switch (daddr) {
253  case GICV_CTLR:
254  vid->vctrl = pkt->getLE<uint32_t>();
255  break;
256  case GICV_PMR:
257  vid->VMPriMask = pkt->getLE<uint32_t>();
258  break;
259  case GICV_EOIR: {
260  // We don't handle the split EOI-then-DIR mode. Linux (guest)
261  // doesn't need it though.
262  assert(!vid->vctrl.EOImode);
263  uint32_t w = pkt->getLE<uint32_t>();
264  unsigned int virq = w & 0x3ff;
265  unsigned int vcpu = (w >> 10) & 7;
266  int i = findLRForVIRQ(vid, virq, vcpu);
267  if (i < 0) {
268  DPRINTF(VGIC, "EOIR: No LR for irq %d(cpu%d)\n", virq, vcpu);
269  } else {
270  DPRINTF(VGIC, "EOIR: Found LR%d for irq %d(cpu%d)\n", i, virq, vcpu);
271  ListReg *lr = &vid->LR[i];
272  lr->State = 0;
273  // Maintenance interrupt -- via eisr -- is flagged when
274  // LRs have EOI=1 and State=INVALID!
275  }
276  } break;
277  default:
278  panic("VGIC VCPU write %#x to unk address %#x\n",
279  pkt->getLE<uint32_t>(), daddr);
280  }
281 
282  // This updates the EISRs and flags IRQs:
283  updateIntState(ctx_id);
284 
285  pkt->makeAtomicResponse();
286  return pioDelay;
287 }
288 
289 Tick
291 {
292  Addr daddr = pkt->getAddr() - hvAddr;
293 
294  ContextID ctx_id = pkt->req->contextId();
295 
296  DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n",
297  daddr, pkt->getLE<uint32_t>());
298 
299  /* Munge the address: 0-0xfff is the usual space banked by requestor CPU.
300  * Anything > that is 0x200-sized slices of 'per CPU' regs.
301  */
302  if (daddr & ~0x1ff) {
303  ctx_id = (daddr >> 9);
304  if (ctx_id > 8)
305  panic("VGIC: Weird unbanked hv ctrl address %#x!\n", daddr);
306  daddr &= ~0x1ff;
307  }
308  assert(ctx_id < VGIC_CPU_MAX);
309  struct vcpuIntData *vid = &vcpuData[ctx_id];
310 
311  switch (daddr) {
312  case GICH_HCR:
313  vid->hcr = pkt->getLE<uint32_t>();
314  // update int state
315  break;
316 
317  case GICH_VMCR: {
318  uint32_t d = pkt->getLE<uint32_t>();
319  vid->VMPriMask = d >> 27;
320  vid->VMBP = (d >> 21) & 7;
321  vid->VMABP = (d >> 18) & 7;
322  vid->VEM = (d >> 9) & 1;
323  vid->VMCBPR = (d >> 4) & 1;
324  vid->VMFiqEn = (d >> 3) & 1;
325  vid->VMAckCtl = (d >> 2) & 1;
326  vid->VMGrp1En = (d >> 1) & 1;
327  vid->VMGrp0En = d & 1;
328  } break;
329 
330  case GICH_APR0:
331  warn_once("VGIC GICH_APR0 written, ignored\n");
332  break;
333 
334  case GICH_LR0:
335  case GICH_LR1:
336  case GICH_LR2:
337  case GICH_LR3:
338  vid->LR[(daddr - GICH_LR0) >> 2] = pkt->getLE<uint32_t>();
339  // update int state
340  break;
341 
342  default:
343  panic("VGIC HVCtrl write to bad address %#x\n", daddr);
344  }
345 
346  updateIntState(ctx_id);
347 
348  pkt->makeAtomicResponse();
349  return pioDelay;
350 }
351 
352 
353 uint32_t
354 VGic::getMISR(struct vcpuIntData *vid)
355 {
356  return (!!vid->hcr.VGrp1DIE && !vid->VMGrp1En ? 0x80 : 0) |
357  (!!vid->hcr.VGrp1EIE && vid->VMGrp1En ? 0x40 : 0) |
358  (!!vid->hcr.VGrp0DIE && !vid->VMGrp0En ? 0x20 : 0) |
359  (!!vid->hcr.VGrp0EIE && vid->VMGrp0En ? 0x10 : 0) |
360  (!!vid->hcr.NPIE && !lrPending(vid) ? 0x08 : 0) |
361  (!!vid->hcr.LRENPIE && vid->hcr.EOICount ? 0x04 : 0) |
362  (!!vid->hcr.UIE && lrValid(vid) <= 1 ? 0x02 : 0) |
363  (vid->eisr ? 0x01 : 0);
364 }
365 
366 void
367 VGic::postVInt(uint32_t cpu, Tick when)
368 {
369  DPRINTF(VGIC, "Posting VIRQ to %d\n", cpu);
370  if (!(postVIntEvent[cpu]->scheduled()))
371  eventq->schedule(postVIntEvent[cpu], when);
372 }
373 
374 void
375 VGic::unPostVInt(uint32_t cpu)
376 {
377  DPRINTF(VGIC, "Unposting VIRQ to %d\n", cpu);
378  auto tc = platform->system->threads[cpu];
379  tc->getCpuPtr()->clearInterrupt(tc->threadId(), ArmISA::INT_VIRT_IRQ, 0);
380 }
381 
382 void
384 {
385  auto tc = platform->system->threads[cpu];
386  tc->getCpuPtr()->postInterrupt(tc->threadId(), ArmISA::INT_VIRT_IRQ, 0);
387 }
388 
389 
390 void
391 VGic::postMaintInt(uint32_t cpu)
392 {
393  DPRINTF(VGIC, "Posting maintenance PPI to GIC/cpu%d\n", cpu);
394  // Linux DT configures this as Level.
395  gic->sendPPInt(maintInt, cpu);
396 }
397 
398 void
399 VGic::unPostMaintInt(uint32_t cpu)
400 {
401  DPRINTF(VGIC, "Unposting maintenance PPI to GIC/cpu%d\n", cpu);
402  gic->clearPPInt(maintInt, cpu);
403 }
404 
405 /* Update state (in general); something concerned with ctx_id has changed.
406  * This may raise a maintenance interrupt.
407  */
408 void
410 {
411  // @todo This should update APRs!
412 
413  // Build EISR contents:
414  // (Cached so that regs can read them without messing about again)
415  struct vcpuIntData *tvid = &vcpuData[ctx_id];
416 
417  tvid->eisr = 0;
418  for (int i = 0; i < NUM_LR; i++) {
419  if (!tvid->LR[i].State && tvid->LR[i].EOI) {
420  tvid->eisr |= 1 << i;
421  }
422  }
423 
424  assert(sys->threads.numRunning() <= VGIC_CPU_MAX);
425  for (int i = 0; i < sys->threads.numRunning(); i++) {
426  struct vcpuIntData *vid = &vcpuData[i];
427  // Are any LRs active that weren't before?
428  if (!vIntPosted[i]) {
429  if (lrPending(vid) && vid->vctrl.En) {
430  vIntPosted[i] = true;
431  postVInt(i, curTick() + 1);
432  }
433  } else if (!lrPending(vid)) {
434  vIntPosted[i] = false;
435  unPostVInt(i);
436  }
437 
438  // Any maintenance ints to send?
439  if (!maintIntPosted[i]) {
440  if (vid->hcr.En && getMISR(vid)) {
441  maintIntPosted[i] = true;
442  postMaintInt(i);
443  }
444  } else {
445  if (!vid->hcr.En || !getMISR(vid)) {
446  unPostMaintInt(i);
447  maintIntPosted[i] = false;
448  }
449  }
450  }
451 }
452 
455 {
456  AddrRangeList ranges;
457  ranges.push_back(RangeSize(hvAddr, GICH_REG_SIZE));
458  ranges.push_back(RangeSize(vcpuAddr, GICV_SIZE));
459  return ranges;
460 }
461 
462 void
464 {
465  Tick interrupt_time[VGIC_CPU_MAX];
466  for (uint32_t cpu = 0; cpu < VGIC_CPU_MAX; cpu++) {
467  interrupt_time[cpu] = 0;
468  if (postVIntEvent[cpu]->scheduled()) {
469  interrupt_time[cpu] = postVIntEvent[cpu]->when();
470  }
471  }
472 
473  DPRINTF(Checkpoint, "Serializing VGIC\n");
474 
475  SERIALIZE_ARRAY(interrupt_time, VGIC_CPU_MAX);
482 
483  for (uint32_t cpu = 0; cpu < VGIC_CPU_MAX; cpu++)
484  vcpuData[cpu].serializeSection(cp, csprintf("vcpuData%d", cpu));
485 }
486 
487 void
489 {
490  uint32_t vctrl_val = vctrl;
491  SERIALIZE_SCALAR(vctrl_val);
492  uint32_t hcr_val = hcr;
493  SERIALIZE_SCALAR(hcr_val);
494  uint64_t eisr_val = eisr;
495  SERIALIZE_SCALAR(eisr_val);
496  uint8_t VMGrp0En_val = VMGrp0En;
497  SERIALIZE_SCALAR(VMGrp0En_val);
498  uint8_t VMGrp1En_val = VMGrp1En;
499  SERIALIZE_SCALAR(VMGrp1En_val);
500  uint8_t VMAckCtl_val = VMAckCtl;
501  SERIALIZE_SCALAR(VMAckCtl_val);
502  uint8_t VMFiqEn_val = VMFiqEn;
503  SERIALIZE_SCALAR(VMFiqEn_val);
504  uint8_t VMCBPR_val = VMCBPR;
505  SERIALIZE_SCALAR(VMCBPR_val);
506  uint8_t VEM_val = VEM;
507  SERIALIZE_SCALAR(VEM_val);
508  uint8_t VMABP_val = VMABP;
509  SERIALIZE_SCALAR(VMABP_val);
510  uint8_t VMBP_val = VMBP;
511  SERIALIZE_SCALAR(VMBP_val);
512  uint8_t VMPriMask_val = VMPriMask;
513  SERIALIZE_SCALAR(VMPriMask_val);
514 
515  for (int i = 0; i < NUM_LR; i++) {
516  ScopedCheckpointSection sec_lr(cp, csprintf("LR%d", i));
517  paramOut(cp, "lr", LR[i]);
518  }
519 }
520 
522 {
523  DPRINTF(Checkpoint, "Unserializing Arm GIC\n");
524 
525  Tick interrupt_time[VGIC_CPU_MAX];
526  UNSERIALIZE_ARRAY(interrupt_time, VGIC_CPU_MAX);
527  for (uint32_t cpu = 0; cpu < VGIC_CPU_MAX; cpu++) {
528  if (interrupt_time[cpu])
529  schedule(postVIntEvent[cpu], interrupt_time[cpu]);
530 
531  vcpuData[cpu].unserializeSection(cp, csprintf("vcpuData%d", cpu));
532  }
539 }
540 
541 void
543 {
544  paramIn(cp, "vctrl_val", vctrl);
545  paramIn(cp, "hcr_val", hcr);
546  paramIn(cp, "eisr_val", eisr);
547  paramIn(cp, "VMGrp0En_val", VMGrp0En);
548  paramIn(cp, "VMGrp1En_val", VMGrp1En);
549  paramIn(cp, "VMAckCtl_val", VMAckCtl);
550  paramIn(cp, "VMFiqEn_val", VMFiqEn);
551  paramIn(cp, "VMCBPR_val", VMCBPR);
552  paramIn(cp, "VEM_val", VEM);
553  paramIn(cp, "VMABP_val", VMABP);
554  paramIn(cp, "VMPriMask_val", VMPriMask);
555 
556  for (int i = 0; i < NUM_LR; i++) {
557  ScopedCheckpointSection sec_lr(cp, csprintf("LR%d", i));
558  paramIn(cp, "lr", LR[i]);
559  }
560 }
561 
562 } // namespace gem5
gem5::VGic::unPostVInt
void unPostVInt(uint32_t cpu)
Definition: vgic.cc:375
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::VGic::readVCpu
Tick readVCpu(PacketPtr pkt)
Definition: vgic.cc:100
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:206
gem5::Event::when
Tick when() const
Get the time that the event is scheduled.
Definition: eventq.hh:508
gem5::VGic::postVInt
void postVInt(uint32_t cpu, Tick when)
Definition: vgic.cc:367
gem5::VGic::GICH_LR3
static const int GICH_LR3
Definition: vgic.hh:86
gem5::VGic::platform
Platform * platform
Definition: vgic.hh:115
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
gem5::PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:102
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::VGic::GICH_LR2
static const int GICH_LR2
Definition: vgic.hh:85
gem5::VGic::GICH_HCR
static const int GICH_HCR
Definition: vgic.hh:74
gem5::RangeSize
AddrRange RangeSize(Addr start, Addr size)
Definition: addr_range.hh:661
warn_once
#define warn_once(...)
Definition: logging.hh:249
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::VGic::maintIntPosted
bool maintIntPosted[VGIC_CPU_MAX]
Definition: vgic.hh:112
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::VGic::processPostVIntEvent
void processPostVIntEvent(uint32_t cpu)
Post interrupt to CPU.
Definition: vgic.cc:383
base_gic.hh
gem5::Serializable::serializeSection
void serializeSection(CheckpointOut &cp, const char *name) const
Serialize an object into a new section.
Definition: serialize.cc:74
vgic.hh
gem5::ArmISA::INT_VIRT_IRQ
@ INT_VIRT_IRQ
Definition: interrupts.hh:65
gem5::VGic::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: vgic.cc:463
gem5::VGic::updateIntState
void updateIntState(ContextID ctx_id)
Definition: vgic.cc:409
gem5::VGic::LR_ACTIVE
static const uint32_t LR_ACTIVE
Definition: vgic.hh:105
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::VGic::getMISR
uint32_t getMISR(struct vcpuIntData *vid)
Definition: vgic.cc:354
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::VGic::GICH_VTR
static const int GICH_VTR
Definition: vgic.hh:75
gem5::VGic::VGic
VGic(const Params &p)
Definition: vgic.cc:52
gem5::VGic::lrValid
unsigned int lrValid(struct vcpuIntData *vid)
Definition: vgic.hh:227
packet.hh
gem5::scmi::Platform::clearInterrupt
void clearInterrupt(const Doorbell *doorbell) override
Definition: scmi_platform.cc:281
gem5::ArmISA::gic
Bitfield< 27, 24 > gic
Definition: misc_types.hh:174
gem5::VGic::GICH_LR1
static const int GICH_LR1
Definition: vgic.hh:84
gem5::VGic::VGIC_CPU_MAX
static const int VGIC_CPU_MAX
Definition: vgic.hh:68
gem5::VGic::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: vgic.cc:521
gem5::VGic::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: vgic.cc:454
interrupts.hh
gem5::VGic::GICV_EOIR
static const int GICV_EOIR
Definition: vgic.hh:93
gem5::VGic::NUM_LR
static const int NUM_LR
Definition: vgic.hh:69
gem5::BaseGic::clearPPInt
virtual void clearPPInt(uint32_t num, uint32_t cpu)=0
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::VGic::GICH_LR0
static const int GICH_LR0
Definition: vgic.hh:83
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:63
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PioDevice::sys
System * sys
Definition: io_device.hh:105
gem5::EventManager::eventq
EventQueue * eventq
A pointer to this object's event queue.
Definition: eventq.hh:991
gem5::VGic::GICH_EISR1
static const int GICH_EISR1
Definition: vgic.hh:79
gem5::VGic::GICH_EISR0
static const int GICH_EISR0
Definition: vgic.hh:78
gem5::VGic::GICH_ELSR0
static const int GICH_ELSR0
Definition: vgic.hh:80
gem5::VGic::GICV_PMR
static const int GICV_PMR
Definition: vgic.hh:90
gem5::VGic::gic
BaseGic * gic
Definition: vgic.hh:116
gem5::VGic::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: vgic.cc:87
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:157
gem5::VGic::findLRForVIRQ
int findLRForVIRQ(struct vcpuIntData *vid, int virq, int vcpu)
Definition: vgic.hh:251
gem5::VGic::GICH_VMCR
static const int GICH_VMCR
Definition: vgic.hh:76
gem5::VGic::vcpuAddr
Addr vcpuAddr
Definition: vgic.hh:118
gem5::VGic::gicvIIDR
const uint32_t gicvIIDR
Definition: vgic.hh:106
gem5::VGic::GICV_IAR
static const int GICV_IAR
Definition: vgic.hh:92
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::VGic::writeVCpu
Tick writeVCpu(PacketPtr pkt)
Definition: vgic.cc:241
gem5::VGic::pioDelay
Tick pioDelay
Definition: vgic.hh:120
gem5::VGic::GICH_MISR
static const int GICH_MISR
Definition: vgic.hh:77
gem5::VGic::GICH_ELSR1
static const int GICH_ELSR1
Definition: vgic.hh:81
gem5::VGic::hvAddr
Addr hvAddr
Definition: vgic.hh:119
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
packet_access.hh
gem5::VGic::unPostMaintInt
void unPostMaintInt(uint32_t cpu)
Definition: vgic.cc:399
gem5::VGic::GICV_SIZE
static const int GICV_SIZE
Definition: vgic.hh:88
gem5::VGic::readCtrl
Tick readCtrl(PacketPtr pkt)
Definition: vgic.cc:147
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::VGic::maintInt
int maintInt
Definition: vgic.hh:121
gem5::RiscvISA::x
Bitfield< 3 > x
Definition: pagetable.hh:73
gem5::VGic::lrPending
unsigned int lrPending(struct vcpuIntData *vid)
Definition: vgic.hh:218
gem5::VGic::~VGic
~VGic()
Definition: vgic.cc:67
gem5::paramOut
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
base.hh
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::VGic::GICH_REG_SIZE
static const int GICH_REG_SIZE
Definition: vgic.hh:72
gem5::paramIn
void paramIn(CheckpointIn &cp, const std::string &name, ExtMachInst &machInst)
Definition: types.cc:72
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::VGic::findHighestPendingLR
int findHighestPendingLR(struct vcpuIntData *vid)
Returns LR index or -1 if none pending.
Definition: vgic.hh:238
gem5::VGic::writeCtrl
Tick writeCtrl(PacketPtr pkt)
Definition: vgic.cc:290
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::EventQueue::schedule
void schedule(Event *event, Tick when, bool global=false)
Schedule the given event on this queue.
Definition: eventq.hh:764
gem5::VGic::vIntPosted
bool vIntPosted[VGIC_CPU_MAX]
Definition: vgic.hh:113
gem5::VGic::GICV_IIDR
static const int GICV_IIDR
Definition: vgic.hh:101
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
trace.hh
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
gem5::VGic::GICV_CTLR
static const int GICV_CTLR
Definition: vgic.hh:89
std::list< AddrRange >
gem5::VGic::vcpuData
EndBitUnion(VCTLR) struct vcpuIntData struct std::array< vcpuIntData, VGIC_CPU_MAX > vcpuData
Definition: vgic.hh:189
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::BaseGic::sendPPInt
virtual void sendPPInt(uint32_t num, uint32_t cpu)=0
Interface call for private peripheral interrupts.
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::VGic::GICH_APR0
static const int GICH_APR0
Definition: vgic.hh:82
gem5::System::Threads::numRunning
int numRunning() const
Definition: system.cc:157
gem5::VGic::Params
VGicParams Params
Definition: vgic.hh:192
gem5::VGic::postMaintInt
void postMaintInt(uint32_t cpu)
Definition: vgic.cc:391
gem5::VGic::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: vgic.cc:74
gem5::VGic::postVIntEvent
EventFunctionWrapper * postVIntEvent[VGIC_CPU_MAX]
Definition: vgic.hh:111
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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