gem5  v21.1.0.2
watchdog_sp805.hh
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37 
38 #ifndef __DEV_ARM_WATCHDOG_SP805_HH__
39 #define __DEV_ARM_WATCHDOG_SP805_HH__
40 
41 #include "dev/arm/amba_device.hh"
42 
43 namespace gem5
44 {
45 
46 struct Sp805Params;
47 
55 class Sp805 : public AmbaIntDevice
56 {
57  public:
58  Sp805(const Sp805Params &params);
59 
60  void serialize(CheckpointOut &cp) const override;
61  void unserialize(CheckpointIn &cp) override;
62 
63  protected:
64  Tick read(PacketPtr pkt) override;
65  Tick write(PacketPtr pkt) override;
66 
67  private:
68  enum Offset : Addr
69  {
70  WDOGLOAD = 0x000,
71  WDOGVALUE = 0x004,
72  WDOGCONTROL = 0x008,
73  WDOGINTCLR = 0x00c,
74  WDOGRIS = 0x010,
75  WDOGMIS = 0x014,
76  // 0x018 - 0xbfc -> Reserved
77  WDOGLOCK = 0xc00,
78  // 0xc04 - 0xefc -> Reserved
79  WDOGITCR = 0xf00,
80  WDOGITOP = 0xf04,
81  // 0xf08 - 0xfdc -> Reserved
82  // 0xfe0 - 0xfff -> CoreSight / Peripheral ID (AMBA ID)
83  };
84 
86  uint32_t timeoutInterval;
87 
90 
92  uint32_t persistedValue;
93 
95  bool enabled;
96 
99 
102 
105 
108 
110  uint32_t value(void) const;
111 
113  void timeoutExpired(void);
114 
116  void restartCounter(void);
117 
119  void stopCounter(void);
120 
125  void sendInt(void);
126 
128  void clearInt(void);
129 
131  static constexpr uint32_t WDOGLOCK_MAGIC = 0x1acce551;
132 };
133 
134 } // namespace gem5
135 
136 #endif // __DEV_ARM_WATCHDOG_SP805_HH__
gem5::Sp805::WDOGLOCK_MAGIC
static constexpr uint32_t WDOGLOCK_MAGIC
If written into WdogLock, registers are unlocked for writes.
Definition: watchdog_sp805.hh:131
gem5::Sp805::restartCounter
void restartCounter(void)
Restarts the counter to the current timeout interval.
Definition: watchdog_sp805.cc:196
gem5::Sp805::integrationTestEnabled
bool integrationTestEnabled
Indicates if integration test harness is enabled.
Definition: watchdog_sp805.hh:104
gem5::Sp805::WDOGITOP
@ WDOGITOP
Definition: watchdog_sp805.hh:80
amba_device.hh
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Sp805::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: watchdog_sp805.cc:62
gem5::Sp805::resetEnabled
bool resetEnabled
Indicates if reset behaviour is enabled when counter reaches 0.
Definition: watchdog_sp805.hh:98
gem5::Sp805::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: watchdog_sp805.cc:113
gem5::Sp805::WDOGLOAD
@ WDOGLOAD
Definition: watchdog_sp805.hh:70
gem5::Sp805::Offset
Offset
Definition: watchdog_sp805.hh:68
gem5::Sp805::stopCounter
void stopCounter(void)
Stops the counter when watchdog becomes disabled.
Definition: watchdog_sp805.cc:203
gem5::Sp805::value
uint32_t value(void) const
Returns the current counter value.
Definition: watchdog_sp805.cc:180
gem5::Sp805::WDOGMIS
@ WDOGMIS
Definition: watchdog_sp805.hh:75
gem5::Sp805::enabled
bool enabled
Indicates if watchdog (counter and interrupt) is enabled.
Definition: watchdog_sp805.hh:95
gem5::Sp805::WDOGLOCK
@ WDOGLOCK
Definition: watchdog_sp805.hh:77
gem5::Sp805::writeAccessEnabled
bool writeAccessEnabled
Indicates if write access to registers is enabled.
Definition: watchdog_sp805.hh:101
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Sp805::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: watchdog_sp805.cc:247
gem5::Sp805::WDOGVALUE
@ WDOGVALUE
Definition: watchdog_sp805.hh:71
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Sp805::persistedValue
uint32_t persistedValue
Value as persisted when the watchdog is stopped.
Definition: watchdog_sp805.hh:92
gem5::AmbaIntDevice
Definition: amba_device.hh:88
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::Sp805::timeoutStartTick
Tick timeoutStartTick
Timeout start tick to keep track of the counter value.
Definition: watchdog_sp805.hh:89
gem5::Sp805::clearInt
void clearInt(void)
Clears any active interrupts.
Definition: watchdog_sp805.cc:224
gem5::Sp805::timeoutExpired
void timeoutExpired(void)
Triggered when value reaches 0.
Definition: watchdog_sp805.cc:188
gem5::Sp805::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: watchdog_sp805.cc:230
gem5::Sp805::WDOGCONTROL
@ WDOGCONTROL
Definition: watchdog_sp805.hh:72
gem5::Sp805::timeoutEvent
EventFunctionWrapper timeoutEvent
Timeout event, triggered when the counter value reaches 0.
Definition: watchdog_sp805.hh:107
gem5::Sp805::WDOGITCR
@ WDOGITCR
Definition: watchdog_sp805.hh:79
gem5::Sp805::timeoutInterval
uint32_t timeoutInterval
Timeout interval (in cycles) as specified in WdogLoad.
Definition: watchdog_sp805.hh:86
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Sp805::WDOGINTCLR
@ WDOGINTCLR
Definition: watchdog_sp805.hh:73
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Sp805::sendInt
void sendInt(void)
Raises an interrupt.
Definition: watchdog_sp805.cc:211
gem5::Sp805::Sp805
Sp805(const Sp805Params &params)
Definition: watchdog_sp805.cc:48
gem5::Sp805::WDOGRIS
@ WDOGRIS
Definition: watchdog_sp805.hh:74
gem5::Sp805
Definition: watchdog_sp805.hh:55

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