gem5  v21.1.0.2
watchdog_sp805.cc
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37 
39 
40 #include "base/logging.hh"
41 #include "debug/Sp805.hh"
42 #include "mem/packet_access.hh"
43 #include "params/Sp805.hh"
44 
45 namespace gem5
46 {
47 
48 Sp805::Sp805(const Sp805Params &params)
49  : AmbaIntDevice(params, 0x1000),
50  timeoutInterval(0xffffffff),
51  timeoutStartTick(MaxTick),
52  persistedValue(timeoutInterval),
53  enabled(false),
54  resetEnabled(false),
55  writeAccessEnabled(true),
56  integrationTestEnabled(false),
57  timeoutEvent([this] { timeoutExpired(); }, name())
58 {
59 }
60 
61 Tick
63 {
64  const Addr addr = pkt->getAddr() - pioAddr;
65  const size_t size = pkt->getSize();
66  panic_if(size != 4, "Sp805::read: Invalid size %i\n", size);
67 
68  uint64_t resp = 0;
69  switch (addr) {
70  case WDOGLOAD:
71  resp = timeoutInterval;
72  break;
73  case WDOGVALUE:
74  resp = value();
75  break;
76  case WDOGCONTROL:
77  resp = enabled | (resetEnabled << 1);
78  break;
79  case WDOGINTCLR:
80  warn("Sp805::read: WO reg (0x%x) [WDOGINTCLR]\n", addr);
81  break;
82  case WDOGRIS:
83  resp = interrupt->active();
84  break;
85  case WDOGMIS:
86  resp = interrupt->active() && enabled;
87  break;
88  case WDOGLOCK:
89  resp = writeAccessEnabled;
90  break;
91  case WDOGITCR:
93  break;
94  case WDOGITOP:
95  warn("Sp805::read: WO reg (0x%x) [WDOGITOP]\n", addr);
96  break;
97  default:
98  if (readId(pkt, ambaId, pioAddr))
99  resp = pkt->getUintX(ByteOrder::little);
100  else
101  warn("Sp805::read: Unexpected address (0x%x:%i), assuming RAZ\n",
102  addr, size);
103  }
104 
105  DPRINTF(Sp805, "Sp805::read: 0x%x<-0x%x(%i)\n", resp, addr, size);
106 
107  pkt->setUintX(resp, ByteOrder::little);
108  pkt->makeResponse();
109  return pioDelay;
110 }
111 
112 Tick
114 {
115  const Addr addr = pkt->getAddr() - pioAddr;
116  const size_t size = pkt->getSize();
117  panic_if(size != 4, "Sp805::write: Invalid size %i\n", size);
118 
119  uint64_t data = pkt->getUintX(ByteOrder::little);
120  switch (addr) {
121  case WDOGLOAD:
122  if (writeAccessEnabled) {
123  // When WdogLoad is written 0x0, immediately trigger an interrupt
124  if (!timeoutInterval)
125  sendInt();
126  else
128  if (enabled)
129  restartCounter();
130  }
131  break;
132  case WDOGVALUE:
133  warn("Sp805::write: RO reg (0x%x) [WDOGVALUE]\n", addr);
134  break;
135  case WDOGCONTROL:
136  if (writeAccessEnabled) {
137  bool was_enabled = enabled;
138  enabled = bits(data, 0);
139  resetEnabled = bits(data, 1);
140  // If watchdog becomes enabled, restart the counter
141  if (!was_enabled && enabled)
142  restartCounter();
143  // If watchdog becomes disabled, stop the counter
144  else if (timeoutEvent.scheduled() && !enabled)
145  stopCounter();
146  }
147  break;
148  case WDOGINTCLR:
149  if (writeAccessEnabled) {
150  // Clear the interrupt and restart the counter if enabled
151  clearInt();
152  if (enabled)
153  restartCounter();
154  }
155  break;
156  case WDOGRIS:
157  warn("Sp805::write: RO reg (0x%x) [WDOGRIS]\n", addr);
158  break;
159  case WDOGMIS:
160  warn("Sp805::write: RO reg (0x%x) [WDOGMIS]\n", addr);
161  break;
162  case WDOGLOCK:
164  break;
165  case WDOGITCR ... WDOGITOP:
166  warn("Sp805::write: No support for integration test harness\n");
167  break;
168  default:
169  warn("Sp805::write: Unexpected address (0x%x:%i), assuming WI\n",
170  addr, size);
171  }
172 
173  DPRINTF(Sp805, "Sp805::write: 0x%x->0x%x(%i)\n", data, addr, size);
174 
175  pkt->makeResponse();
176  return pioDelay;
177 }
178 
179 uint32_t
181 {
184  : persistedValue;
185 }
186 
187 void
189 {
191  sendInt();
192  restartCounter();
193 }
194 
195 void
197 {
200 }
201 
202 void
204 {
205  persistedValue = value();
208 }
209 
210 void
212 {
213  // If the previously sent interrupt has not been served,
214  // assert system reset if enabled
215  if (interrupt->active() && enabled) {
216  if (resetEnabled)
217  warn("Watchdog timed out, system reset asserted\n");
218  } else {
219  interrupt->raise();
220  }
221 }
222 
223 void
225 {
226  interrupt->clear();
227 }
228 
229 void
231 {
239 
240  bool ev_scheduled = timeoutEvent.scheduled();
241  SERIALIZE_SCALAR(ev_scheduled);
242  if (ev_scheduled)
244 }
245 
246 void
248 {
256 
257  bool ev_scheduled;
258  UNSERIALIZE_SCALAR(ev_scheduled);
259  if (ev_scheduled) {
260  Tick when;
261  UNSERIALIZE_SCALAR(when);
262  reschedule(timeoutEvent, when, true);
263  }
264 }
265 
266 } // namespace gem5
gem5::AmbaPioDevice::ambaId
uint64_t ambaId
Definition: amba_device.hh:81
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Event::when
Tick when() const
Get the time that the event is scheduled.
Definition: eventq.hh:508
gem5::BasicPioDevice::pioAddr
Addr pioAddr
Address that the device listens to.
Definition: io_device.hh:151
gem5::Sp805::WDOGLOCK_MAGIC
static constexpr uint32_t WDOGLOCK_MAGIC
If written into WdogLock, registers are unlocked for writes.
Definition: watchdog_sp805.hh:131
warn
#define warn(...)
Definition: logging.hh:245
gem5::Packet::getUintX
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition: packet.cc:334
gem5::Sp805::restartCounter
void restartCounter(void)
Restarts the counter to the current timeout interval.
Definition: watchdog_sp805.cc:196
gem5::Sp805::integrationTestEnabled
bool integrationTestEnabled
Indicates if integration test harness is enabled.
Definition: watchdog_sp805.hh:104
data
const char data[]
Definition: circlebuf.test.cc:48
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::Sp805::WDOGITOP
@ WDOGITOP
Definition: watchdog_sp805.hh:80
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Sp805::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: watchdog_sp805.cc:62
gem5::MaxTick
const Tick MaxTick
Definition: types.hh:60
gem5::Sp805::resetEnabled
bool resetEnabled
Indicates if reset behaviour is enabled when counter reaches 0.
Definition: watchdog_sp805.hh:98
gem5::Sp805::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: watchdog_sp805.cc:113
gem5::Sp805::WDOGLOAD
@ WDOGLOAD
Definition: watchdog_sp805.hh:70
gem5::Sp805::stopCounter
void stopCounter(void)
Stops the counter when watchdog becomes disabled.
Definition: watchdog_sp805.cc:203
gem5::Sp805::value
uint32_t value(void) const
Returns the current counter value.
Definition: watchdog_sp805.cc:180
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::Sp805::WDOGMIS
@ WDOGMIS
Definition: watchdog_sp805.hh:75
gem5::Sp805::enabled
bool enabled
Indicates if watchdog (counter and interrupt) is enabled.
Definition: watchdog_sp805.hh:95
gem5::Sp805::WDOGLOCK
@ WDOGLOCK
Definition: watchdog_sp805.hh:77
gem5::Sp805::writeAccessEnabled
bool writeAccessEnabled
Indicates if write access to registers is enabled.
Definition: watchdog_sp805.hh:101
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmInterruptPin::clear
virtual void clear()=0
Clear a signalled interrupt.
gem5::Sp805::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: watchdog_sp805.cc:247
gem5::Sp805::WDOGVALUE
@ WDOGVALUE
Definition: watchdog_sp805.hh:71
gem5::BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:157
gem5::EventManager::reschedule
void reschedule(Event &event, Tick when, bool always=false)
Definition: eventq.hh:1037
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Sp805::persistedValue
uint32_t persistedValue
Value as persisted when the watchdog is stopped.
Definition: watchdog_sp805.hh:92
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
packet_access.hh
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::EventManager::deschedule
void deschedule(Event &event)
Definition: eventq.hh:1028
gem5::statistics::enabled
bool enabled()
Definition: statistics.cc:280
gem5::AmbaIntDevice
Definition: amba_device.hh:88
gem5::Sp805::timeoutStartTick
Tick timeoutStartTick
Timeout start tick to keep track of the counter value.
Definition: watchdog_sp805.hh:89
gem5::AmbaIntDevice::interrupt
ArmInterruptPin *const interrupt
Definition: amba_device.hh:91
gem5::Sp805::clearInt
void clearInt(void)
Clears any active interrupts.
Definition: watchdog_sp805.cc:224
gem5::Sp805::timeoutExpired
void timeoutExpired(void)
Triggered when value reaches 0.
Definition: watchdog_sp805.cc:188
gem5::Sp805::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: watchdog_sp805.cc:230
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::Sp805::WDOGCONTROL
@ WDOGCONTROL
Definition: watchdog_sp805.hh:72
gem5::Sp805::timeoutEvent
EventFunctionWrapper timeoutEvent
Timeout event, triggered when the counter value reaches 0.
Definition: watchdog_sp805.hh:107
gem5::Sp805::WDOGITCR
@ WDOGITCR
Definition: watchdog_sp805.hh:79
gem5::Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1031
gem5::Sp805::timeoutInterval
uint32_t timeoutInterval
Timeout interval (in cycles) as specified in WdogLoad.
Definition: watchdog_sp805.hh:86
logging.hh
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ArmInterruptPin::raise
virtual void raise()=0
Signal an interrupt.
gem5::AmbaDevice::readId
bool readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr)
Definition: amba_device.cc:75
gem5::Sp805::WDOGINTCLR
@ WDOGINTCLR
Definition: watchdog_sp805.hh:73
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::ArmInterruptPin::active
bool active() const
True if interrupt pin is active, false otherwise.
Definition: base_gic.hh:220
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Sp805::sendInt
void sendInt(void)
Raises an interrupt.
Definition: watchdog_sp805.cc:211
gem5::Sp805::Sp805
Sp805(const Sp805Params &params)
Definition: watchdog_sp805.cc:48
gem5::Packet::setUintX
void setUintX(uint64_t w, ByteOrder endian)
Set the value in the word w after truncating it to the length of the packet and then byteswapping it ...
Definition: packet.cc:351
gem5::Sp805::WDOGRIS
@ WDOGRIS
Definition: watchdog_sp805.hh:74
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::Sp805
Definition: watchdog_sp805.hh:55
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
watchdog_sp805.hh

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