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mem
ruby
network
Topology.hh
Go to the documentation of this file.
1
/*
2
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3
* All rights reserved.
4
*
5
* Redistribution and use in source and binary forms, with or without
6
* modification, are permitted provided that the following conditions are
7
* met: redistributions of source code must retain the above copyright
8
* notice, this list of conditions and the following disclaimer;
9
* redistributions in binary form must reproduce the above copyright
10
* notice, this list of conditions and the following disclaimer in the
11
* documentation and/or other materials provided with the distribution;
12
* neither the name of the copyright holders nor the names of its
13
* contributors may be used to endorse or promote products derived from
14
* this software without specific prior written permission.
15
*
16
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
*/
28
29
/*
30
* The topology here is configurable; it can be a hierachical (default
31
* one) or a 2D torus or a 2D torus with half switches killed. I think
32
* all input port has a one-input-one-output switch connected just to
33
* control and bandwidth, since we don't control bandwidth on input
34
* ports. Basically, the class has a vector of nodes and edges. First
35
* 2*m_nodes elements in the node vector are input and output
36
* ports. Edges are represented in two vectors of src and dest
37
* nodes. All edges have latency.
38
*/
39
40
#ifndef __MEM_RUBY_NETWORK_TOPOLOGY_HH__
41
#define __MEM_RUBY_NETWORK_TOPOLOGY_HH__
42
43
#include <iostream>
44
#include <string>
45
#include <vector>
46
47
#include "
mem/ruby/common/TypeDefines.hh
"
48
#include "
mem/ruby/network/BasicLink.hh
"
49
#include "mem/ruby/protocol/LinkDirection.hh"
50
51
class
NetDest
;
52
class
Network
;
53
54
typedef
std::vector<std::vector<int>
>
Matrix
;
55
typedef
std::string
PortDirection
;
56
57
struct
LinkEntry
58
{
59
BasicLink
*
link
;
60
PortDirection
src_outport_dirn
;
61
PortDirection
dst_inport_dirn
;
62
};
63
64
typedef
std::map<std::pair<SwitchID, SwitchID>,
LinkEntry
>
LinkMap
;
65
66
class
Topology
67
{
68
public
:
69
Topology
(uint32_t num_routers,
const
std::vector<BasicExtLink *>
&ext_links,
70
const
std::vector<BasicIntLink *>
&int_links);
71
72
uint32_t
numSwitches
()
const
{
return
m_number_of_switches; }
73
void
createLinks(
Network
*net);
74
void
print
(std::ostream& out)
const
{ out <<
"[Topology]"
; }
75
76
private
:
77
void
addLink(
SwitchID
src,
SwitchID
dest,
BasicLink
*
link
,
78
PortDirection
src_outport_dirn
=
""
,
79
PortDirection
dest_inport_dirn =
""
);
80
void
makeLink(
Network
*net,
SwitchID
src,
SwitchID
dest,
81
const
NetDest
& routing_table_entry);
82
83
// Helper functions based on chapter 29 of Cormen et al.
84
void
extend_shortest_path(
Matrix
¤t_dist,
Matrix
&latencies,
85
Matrix
&inter_switches);
86
87
std::vector<std::vector<int>
> shortest_path(
const
Matrix
&weights,
88
Matrix
&latencies,
Matrix
&inter_switches);
89
90
bool
link_is_shortest_path_to_node(
SwitchID
src,
SwitchID
next,
91
SwitchID
final
,
const
Matrix
&weights,
const
Matrix
&
dist
);
92
93
NetDest
shortest_path_to_node(
SwitchID
src,
SwitchID
next,
94
const
Matrix
&weights,
const
Matrix
&dist);
95
96
const
uint32_t
m_nodes
;
97
const
uint32_t
m_number_of_switches
;
98
99
std::vector<BasicExtLink*>
m_ext_link_vector
;
100
std::vector<BasicIntLink*>
m_int_link_vector
;
101
102
LinkMap
m_link_map
;
103
};
104
105
inline
std::ostream&
106
operator<<
(std::ostream& out,
const
Topology
& obj)
107
{
108
obj.
print
(out);
109
out << std::flush;
110
return
out;
111
}
112
113
#endif // __MEM_RUBY_NETWORK_TOPOLOGY_HH__
Matrix
std::vector< std::vector< int > > Matrix
Definition:
Topology.hh:52
Topology::m_nodes
const uint32_t m_nodes
Definition:
Topology.hh:96
LinkEntry::link
BasicLink * link
Definition:
Topology.hh:59
BasicLink
Definition:
BasicLink.hh:45
Topology::numSwitches
uint32_t numSwitches() const
Definition:
Topology.hh:72
LinkEntry::src_outport_dirn
PortDirection src_outport_dirn
Definition:
Topology.hh:60
std::vector
STL vector class.
Definition:
stl.hh:40
TypeDefines.hh
Network
Definition:
Network.hh:76
Topology::print
void print(std::ostream &out) const
Definition:
Topology.hh:74
LinkEntry
Definition:
Topology.hh:57
SwitchID
unsigned int SwitchID
Definition:
TypeDefines.hh:35
NetDest
Definition:
NetDest.hh:39
LinkMap
std::map< std::pair< SwitchID, SwitchID >, LinkEntry > LinkMap
Definition:
Topology.hh:64
PortDirection
std::string PortDirection
Definition:
Topology.hh:55
LinkEntry::dst_inport_dirn
PortDirection dst_inport_dirn
Definition:
Topology.hh:61
Topology
Definition:
Topology.hh:66
Topology::m_number_of_switches
const uint32_t m_number_of_switches
Definition:
Topology.hh:97
Topology::m_link_map
LinkMap m_link_map
Definition:
Topology.hh:102
BasicLink.hh
Topology::m_int_link_vector
std::vector< BasicIntLink * > m_int_link_vector
Definition:
Topology.hh:100
Stats::dist
const FlagsType dist
Print the distribution.
Definition:
info.hh:57
operator<<
std::ostream & operator<<(std::ostream &out, const Topology &obj)
Definition:
Topology.hh:106
Topology::m_ext_link_vector
std::vector< BasicExtLink * > m_ext_link_vector
Definition:
Topology.hh:99
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