- c -

c : ArmISA::PMU , AtomicGeneric3Op< T > , AtomicGenericPair3Op< T > , AtomicOpCAS< T > , Coeff8 , Coeff8x8 , Compressed , Cycles , MathExpr::OpSearch
C0 : MipsISA::PTE , PowerISA::PTE , RiscvISA::PTE
c0_config : SparcISA::TLB
c0_tsb_ps0 : SparcISA::TLB
c0_tsb_ps1 : SparcISA::TLB
C1 : MipsISA::PTE , PowerISA::PTE , RiscvISA::PTE
c_reg : ConditionRegisterState
cache : AddrRangeMap< V, max_cache_size > , BaseCache::CacheCmdStats , BaseCache::CacheReqPacketQueue , BaseCache::CacheStats , BaseCache::CpuSidePort , BaseCache::MemSidePort , BasePrefetcher
cacheAsi : SparcISA::TLB
cacheBlkSize : DefaultFetch< Impl >
cacheBlocked : DefaultFetch< Impl >
cacheBlockMask : AtomicSimpleCPU::AtomicCPUDPort , LSQUnit< Impl > , Minor::LSQ , TimingSimpleCPU::DcachePort
cachedDisassembly : StaticInst
cachedLocations : SnoopFilter
cachedMsrIntersection : X86KvmCPU
cachedPC : PowerISA::PCDependentDisassembly
cachedSymtab : PowerISA::PCDependentDisassembly
cacheEntry : SparcISA::TLB
cacheLines : MemFootprintProbe
cacheLinesAll : MemFootprintProbe
cacheLineSize : PCIConfig , StochasticGen
cacheLineSizeLg2 : MemFootprintProbe
cacheLoadPorts : LSQ< Impl >
cacheMiss : BasePrefetcher::PrefetchInfo
cachePnt : IGbE::DescCache< T >
cachePort : GarnetSyntheticTraffic
cacheSnoop : QueuedPrefetcher
cacheState : SparcISA::TLB
cacheStore : SimpleCache
cacheStorePorts : LSQ< Impl >
cacheTracking : FALRU
cacheValid : SparcISA::TLB
cachingPage : UFSHostDevice::UFSSCSIDevice
calc : StackDistProbe
call : ArmSemihosting::SemiCall
callArgMem : Wavefront
callArgs : ListOperand
callback : EventFunctionWrapper
callbackDataAvail : Uart , VirtIOConsole
callbackKick : MmioVirtIO , PciVirtIO
callbacks : CallbackQueue
caller : m5::Coroutine< Arg, Ret >
callerFiber : m5::Coroutine< Arg, Ret >::CallerType
calls : ArmSemihosting
canEarlyIssue : Minor::MinorDynInst
canHandleInterrupts : DefaultCommit< Impl >
canMergeWrites : MSHR::TargetList
cantForwardFromFUIndices : Minor::FUPipeline , MinorFU
capabilityList : FuncUnit , FUPool , Minor::FUPipeline , MinorOpClassSet
capabilityPtr : PCIConfig
capacitors : ThermalModel
capacity : Minor::Queue< ElemType, ReportTraits, BubbleTraits > , SimpleCache , VirtIOBlock::Config
capacityLower : UFSHostDevice::UFSSCSIDevice
capacityUpper : UFSHostDevice::UFSSCSIDevice
caplen : pcap_pkthdr
captureCurrentFrame : VncInput
captureEnabled : VncInput
captureImage : VncInput
captureLastHash : VncInput
captureOutputDirectory : VncInput
cardbusCIS : PCIConfig
cascadeBits : X86ISA::I8259
cascadeMode : X86ISA::I8259
cause : CountedExitEvent , GlobalSimLoopExitEvent , LocalSimLoopExitEvent , MipsISA::RemoteGDB::MipsGdbRegCache
caux : ecoff_fdr
cbAuxOffset : ecoff_symhdr
cbDnOffset : ecoff_symhdr
cbExtOffset : ecoff_symhdr
cbFdOffset : ecoff_symhdr
cbFunction : MemBackdoor::Callback
cbLine : ecoff_fdr , ecoff_symhdr
cbLineOffset : ecoff_fdr , ecoff_symhdr , pdr
cbOptOffset : ecoff_symhdr
cbPdOffset : ecoff_symhdr
CBPR : Gicv3CPUInterface
CBPR_EL1NS : Gicv3CPUInterface
CBPR_EL1S : Gicv3CPUInterface
cbRfdOffset : ecoff_symhdr
cbSs : ecoff_fdr
cbSsExtOffset : ecoff_symhdr
cbSsOffset : ecoff_symhdr
cbSymOffset : ecoff_symhdr
cchip : Malta , Tsunami
ccList : UnifiedFreeList
ccMap : UnifiedRenameMap
ccRegFile : PhysRegFile
ccRegfileReads : FullO3CPU< Impl >
ccRegfileWrites : FullO3CPU< Impl >
ccRegIds : Iris::ThreadContext , PhysRegFile
ccRegIdxNameMap : FastModel::CortexA76TC
ccRegs : SimpleThread
ccsr : dp_regs
cct : Gicv3Its
cdf : Stats::ScalarPrint
cdFetches : SMMUv3
cdL1Fetches : SMMUv3
ce : CopyEngine::CopyEngineChannel
cePort : CopyEngine::CopyEngineChannel
ch_b : PixelConverter
ch_g : PixelConverter
ch_r : PixelConverter
chan : CopyEngine
chanCount : CopyEngineReg::Regs
changed : Trace::ArmNativeTrace::ThreadState
changedPC : CheckerCPU
changedROBNumEntries : DefaultCommit< Impl >
channelId : CopyEngine::CopyEngineChannel
channelOrder : Brig::BrigOperandConstantImage
channelType : Brig::BrigOperandConstantImage
char_to_logic : sc_dt::sc_logic
characteristicExtBytes : X86ISA::SMBios::BiosInformation
characteristics : X86ISA::SMBios::BiosInformation
checkEmptyROB : DefaultCommit< Impl >
checker : BaseSimpleCPU , FullO3CPU< Impl >
checkerCPU : CheckerThreadContext< TC >
checkerTC : CheckerThreadContext< TC >
checkLoads : LSQUnit< Impl >
checkR11 : Trace::X86NativeTrace
checkRcx : Trace::X86NativeTrace
checkStartEvent : RubyTester
child : CowDiskImage , SimpleInitiatorWrapper , SimpleTargetWrapper
childClearTID : Process
children : ClockDomain , ProfileNode , sc_gem5::Object
choiceCounters : BiModeBP
choiceCtrBits : BiModeBP , TournamentBP
choiceCtrs : TournamentBP
choiceHistoryMask : BiModeBP , TournamentBP
choicePredictorSize : BiModeBP , TournamentBP
choiceThreshold : BiModeBP , TournamentBP
chooserConfWidth : StatisticalCorrector
chunk : LdsChunk
chunkIdx : X86ISA::Decoder
chunkMap : LdsState
chunks : X86ISA::Decoder::InstBytes
chunkSize : ChunkGenerator , IrregularStreamBufferPrefetcher
ci : TAGEBase::BranchInfo
cidBits : Gicv3Its
cil : Gicv3Its
ckptCount : Serializable
ckptMaxCount : Serializable
ckptPrevCount : Serializable
ckptRestore : DistIface::RecvScheduler
classCode : PCIConfig
ClcdCrsrClip : Pl111
clcdCrsrClip : Pl111
ClcdCrsrConfig : Pl111
clcdCrsrConfig : Pl111
ClcdCrsrCtrl : Pl111
clcdCrsrCtrl : Pl111
ClcdCrsrIcr : Pl111
clcdCrsrIcr : Pl111
ClcdCrsrImsc : Pl111
clcdCrsrImsc : Pl111
ClcdCrsrMis : Pl111
clcdCrsrMis : Pl111
ClcdCrsrPalette0 : Pl111
clcdCrsrPalette0 : Pl111
ClcdCrsrPalette1 : Pl111
clcdCrsrPalette1 : Pl111
ClcdCrsrRis : Pl111
clcdCrsrRis : Pl111
ClcdCrsrXY : Pl111
clcdCrsrXY : Pl111
cleanupEvent : TLBCoalescer , X86ISA::GpuTLB
cleanupQueue : TLBCoalescer , X86ISA::GpuTLB
clearFetchFault : DefaultFetchDefaultDecode< Impl >
clearInterrupt : TimeBufStruct< Impl >::commitComm
clearPeriod : StoreSet
clearReq : MultiSocketSimpleSwitchAT::ConnectionInfo
client : Iris::ThreadContext
cline : ecoff_fdr
clk : fun , memory , test
clk_in : Pl050
clkdiv : Pl050
clkn : testbench
clkn2 : testbench
clkp : testbench
clkp2 : testbench
clksel : Pl111
clock : ClockDomain::ClockDomainStats , Shader , Sp804::Timer , TLBCoalescer , X86ISA::GpuTLB
clock_data : MC146818
clock_remainder : ArmISA::PMU
clockChanged : FastModel::ScxEvsCortexA76< Types >
clockDivider : DerivedClockDomain
clockDomain : Clocked , X86ISA::Interrupts
clocked_object : PowerModel , PowerModelState
clockedObject : ClockedObject::ClockedObjectStats
clockEvent : Iris::BaseCPU
clockID : PosixKvmTimer
clockPeriod : FastModel::ScxEvsCortexA76< Types >
clockRateControl : FastModel::ScxEvsCortexA76< Types >
ClrImportant : BmpWriter::InfoHeaderV1
ClrUsed : BmpWriter::InfoHeaderV1
cltn : sc_core::sc_attr_cltn , sc_gem5::Object
clusivity : BaseCache
cluster : FastModel::CortexA76
cm : ArmISA::DataAbort
cmap : Stats::SparseHistData , Stats::SparseHistStor
cmd : BaseCache::CacheStats , BaseRemoteGDB::GdbCommand::Context , MemCmd , Packet , ProbePoints::PacketInfo , SMMUCommandExecProcess , TraceCPU::FixedRetryGen::TraceElement , TraceGen::TraceElement
cmd_byte : BaseRemoteGDB::GdbCommand::Context
cmdBytes : IdeDisk
cmdBytesLeft : IdeDisk
cmdDispatcher : ItsCommand
cmdLine : ArmSemihosting
cmdList : DRAMCtrl::Rank
cmdq_base : SMMURegs
cmdq_cons : SMMURegs
cmdq_prod : SMMURegs
cmdReg : IdeDisk
cmdsts : ns_desc32 , ns_desc64
CMDUCMDARG1 : UFSHostDevice::HCIMem
CMDUCMDARG2 : UFSHostDevice::HCIMem
CMDUCMDARG3 : UFSHostDevice::HCIMem
CMDUICCMDR : UFSHostDevice::HCIMem
cmos : SouthBridge
cmpEnable : A9GlobalTimer::Timer
cmpOp : HsailISA::CmpInstBase< DestOperandType, SrcOperandType >
cmpVal : A9GlobalTimer::Timer
cmpValEvent : A9GlobalTimer::Timer
cnthpirq : FastModel::ScxEvsCortexA76< Types >
cnthvirq : FastModel::ScxEvsCortexA76< Types >
cntpnsirq : FastModel::ScxEvsCortexA76< Types >
cntpsirq : FastModel::ScxEvsCortexA76< Types >
cntvirq : FastModel::ScxEvsCortexA76< Types >
coalescedAccesses : TLBCoalescer
coalescedRxDesc : EtherDevice
coalescedRxIdle : EtherDevice
coalescedRxOk : EtherDevice
coalescedRxOrn : EtherDevice
coalescedSwi : EtherDevice
coalescedTotal : EtherDevice
coalescedTxDesc : EtherDevice
coalescedTxIdle : EtherDevice
coalescedTxOk : EtherDevice
coalesceLimit : WriteAllocator
coalescer : TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort
coalescerFIFO : TLBCoalescer
coalescerToVrfBusWidth : ComputeUnit
coalescingWindow : TLBCoalescer
cobol_main : ecoff_extsym
code : DictionaryCompressor< T >::Pattern , EmbeddedPython , GlobalSimLoopExitEvent , HUFFMTBL_ENTRY , LocalSimLoopExitEvent , MipsISA::MipsFaultBase::FaultVals
code_offs : HsaKernelInfo
code_ptr : HsaQueueEntry
code_size : HsaDriverSizes
codeFiles : ClDriver
coeff : MultiperspectivePerceptron::HistorySpec
coissue_return : Shader
cols : VirtIOConsole::Config
column : Brig::BrigDirectiveLoc
columnsPerRowBuffer : DRAMCtrl
columnsPerStripe : DRAMCtrl
comInstEventQueue : Iris::ThreadContext , O3ThreadState< Impl > , SimpleThread
command : CommandReg , CopyEngineReg::ChanRegs , CopyEngineReg::DmaDesc , dp_regs , HDLcd , PCIConfig
Command : Sinic::Device
command_map : BaseRemoteGDB
commandByte : X86ISA::I8042
commandDescBaseAddrHi : UFSHostDevice::UTPTransferReqDesc
commandDescBaseAddrLo : UFSHostDevice::UTPTransferReqDesc
commandEvent : Gicv3Its
commandExecutor : SMMUv3
commandInfo : MemCmd
commandLast : X86ISA::I8042
commandLine : LinuxX86System
CommandLineSize : BareIronMipsSystem , LinuxAlphaSystem , LinuxMipsSystem
commandPort : X86ISA::I8042
commandUPIU : UFSHostDevice::UTPTransferCMDDesc
commirq : FastModel::ScxEvsCortexA76< Types >
commit : DefaultRename< Impl >::Stalls , ElasticTrace::TraceInfo , FullO3CPU< Impl >
commit_ptr : DefaultRename< Impl >
commitEligibleSamples : DefaultCommit< Impl >
commitInfo : TimeBufStruct< Impl >
commitLimit : Minor::Execute
commitNonSpecStalls : DefaultCommit< Impl >
commitPolicy : DefaultCommit< Impl >
commitPriority : Minor::Execute
commitRenameMap : FullO3CPU< Impl >
commitSquashedInsts : DefaultCommit< Impl >
commitStatus : DefaultCommit< Impl >
committedInsts : FullO3CPU< Impl >
committedInstType : Minor::MinorStats
committedOps : FullO3CPU< Impl >
committedStores : DefaultCommit< Impl >
commitTick : ElasticTrace::TraceInfo
commitToDecodeDelay : DefaultDecode< Impl >
commitToFetchDelay : DefaultFetch< Impl >
commitToIEWDelay : DefaultCommit< Impl > , DefaultIEW< Impl > , InstructionQueue< Impl >
commitToRenameDelay : DefaultRename< Impl >
commitWidth : DefaultCommit< Impl > , DefaultRename< Impl >
commPage : ArmFreebsdProcess32 , ArmLinuxProcess32
comp : TAGEBase::FoldedHistory
compare : Brig::BrigInstCmp
compData : MultiCompressor::MultiCompData
compDelay : ElasticTrace::TraceInfo , TraceCPU::ElasticDataGen::GraphNode
compLength : TAGEBase::FoldedHistory
complete : ArmISA::Stage2LookUp , MemChecker::Transaction , MemChecker::WriteCluster
COMPLETED : ArmISA::TableWalker
completed : MemDepUnit< MemDepPred, Impl >::MemDepEntry
completedWfs : ComputeUnit
completeMax : MemChecker::WriteCluster
completionAddr : CopyEngineReg::ChanRegs
completionAddress : IGbE::TxDescCache
completionDataReg : CopyEngine::CopyEngineChannel
completionEnabled : IGbE::TxDescCache
completionEvent : DmaPort::DmaReqState
compressedSize : PerfectCompressor
Compression : BmpWriter::InfoHeaderV1
compressionLatency : PerfectCompressor
compressions : BaseCacheCompressor::BaseCacheCompressorStats
compressionSize : BaseCacheCompressor::BaseCacheCompressorStats
compressionSizeBits : BaseCacheCompressor::BaseCacheCompressorStats
compressor : BaseCache , BaseCacheCompressor::BaseCacheCompressorStats
compressors : MultiCompressor
computeIndices : TAGEBase::ThreadHistory
computeTags : TAGEBase::ThreadHistory
computeUnit : AtomicOpCAS< T > , ComputeUnit::CUExitCallback , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , ConditionRegisterState , ExecStage , FetchStage , FetchUnit , GlobalMemPipeline , LocalMemPipeline , ScheduleStage , ScoreboardCheckStage , VecRegisterState , VectorRegisterFile , Wavefront
cond : ArmISA::FpRegRegRegCondOp , HsailISA::CbrInstBase< TargetType > , TimingExprIf
condBranch : MultiperspectivePerceptron::MPPBranchInfo , TAGEBase::BranchInfo
condCode : ArmISA::BranchImmCond64 , ArmISA::DataXCondCompImmOp , ArmISA::DataXCondCompRegOp , ArmISA::DataXCondSelOp , ArmISA::FpCondCompRegOp , ArmISA::FpCondSelOp , ArmISA::PredOp
condIncorrect : BPredUnit
conditional : ArmISA::SveSelectOp
condPredicted : BPredUnit
condRegState : Wavefront
confBase : GenericPciHost
confDeviceBits : GenericPciHost
confidence : LoopPredictor::LoopEntry , SignaturePathPrefetcherV2::GlobalHistoryEntry , StridePrefetcher::StrideEntry
confidenceThreshold : LoopPredictor
config : dp_regs , PciDevice
Config : Sinic::Device
config : StreamTableEntry , VirtIO9PBase , VirtIOBlock , VirtIOConsole
configAddress : X86ISA::GpuTLB , X86ISA::TLB
configCache : SMMUv3
configCacheEnable : SMMUv3
configDelay : PciDevice
configFile : CxxConfigManager , TrafficGen
configLat : SMMUv3
configManager : CxxConfigManager::SimObjectResolver
configSem : SMMUv3
configSize : VirtIODeviceBase
configurations : FaultModel
conflictingLoads : MemDepUnit< MemDepPred, Impl >
conflictingStores : MemDepUnit< MemDepPred, Impl >
confSize : GenericPciHost
confTableReported : AbstractMemory , BackingStoreEntry
ConnectEvent : BaseRemoteGDB
connectEvent : BaseRemoteGDB
console : AlphaSystem , MipsISA::StackTrace , MipsSystem , PowerISA::StackTrace , RiscvISA::StackTrace , RiscvSystem , X86ISA::StackTrace
consoleData : AlphaBackdoor
consolePanicEvent : AlphaSystem
consoleSymtab : AlphaSystem , MipsSystem , RiscvSystem
ConstT : RefCountingPtr< T >
constUDelaySkipEvent : FreebsdArmSystem , LinuxArmSystem
consumerInst : DefaultIEW< Impl >
cont : cp::Print , StreamTableEntry
container : VecLaneT< VecElem, Const > , VecPredRegContainer< NumBits, Packed > , VecPredRegT< VecElem, NumElems, Packed, Const > , VecRegContainer< Sz > , VecRegT< VecElem, NumElems, Const >
context : SMMUTranslationProcess
contextId : CacheBlk::Lock , LockedAddr , SparcISA::TlbRange
contextIds : Process
continued : TIR
control : A9GlobalTimer::Timer , Brig::BrigDirectiveControl , Pl011 , Sp804::Timer
controlFlowDivergenceDist : ComputeUnit
controller : AbstractController::MemoryPort
controlPage : UFSHostDevice::UFSSCSIDevice
controlPort : SMMUv3
conv : HDLcd
converter : Pl111
coord : Brig::BrigOperandConstantSampler
coordType : Brig::BrigInstImage
copiesProcessed : CopyEngine
coProcID : MipsISA::CoprocessorUnusableFault
copt : ecoff_fdr
copyBuffer : CopyEngine::CopyEngineChannel
CoreCount : FastModel::ScxEvsCortexA76< Types > , FastModel::ScxEvsCortexA76x1Types , FastModel::ScxEvsCortexA76x2Types , FastModel::ScxEvsCortexA76x3Types , FastModel::ScxEvsCortexA76x4Types
cores : FastModel::CortexA76Cluster
coro : m5::Coroutine< Arg, Ret >::CallerType
coroutine : ItsProcess , SMMUProcess
count : ArmISA::ArmFault::FaultVals , AUXU , DmaCallback , fun , InstructionQueue< Impl > , ProfileNode , RefCounted , sc_gem5::ReportMsgInfo , sc_gem5::ReportSevInfo , SimPoint::BBInfo , SMMUSemaphore , SparcISA::SparcFaultBase::FaultVals , TreePLRURP
counter : Intel8254Timer , Intel8254Timer::Counter::CounterEvent , IrregularStreamBufferPrefetcher::AddressMapping , SatCounter , SignaturePathPrefetcher::PatternEntry , SignaturePathPrefetcher::PatternStrideEntry , STeMSPrefetcher::ActiveGenerationTableEntry::SequenceEntry
counterId : ArmISA::PMU::CounterState
counters : ArmISA::PMU
countInt : UFSHostDevice
countNumSeqPkts : DramGen
countPages : ComputeUnit
counts : sc_gem5::UniqueNameGen
CP0_Config : MipsISA::CoreSpecific
CP0_Config1 : MipsISA::CoreSpecific
CP0_Config1_C2 : MipsISA::CoreSpecific
CP0_Config1_CA : MipsISA::CoreSpecific
CP0_Config1_DA : MipsISA::CoreSpecific
CP0_Config1_DL : MipsISA::CoreSpecific
CP0_Config1_DS : MipsISA::CoreSpecific
CP0_Config1_EP : MipsISA::CoreSpecific
CP0_Config1_FP : MipsISA::CoreSpecific
CP0_Config1_IA : MipsISA::CoreSpecific
CP0_Config1_IL : MipsISA::CoreSpecific
CP0_Config1_IS : MipsISA::CoreSpecific
CP0_Config1_M : MipsISA::CoreSpecific
CP0_Config1_MD : MipsISA::CoreSpecific
CP0_Config1_MMU : MipsISA::CoreSpecific
CP0_Config1_PC : MipsISA::CoreSpecific
CP0_Config1_WR : MipsISA::CoreSpecific
CP0_Config2 : MipsISA::CoreSpecific
CP0_Config2_M : MipsISA::CoreSpecific
CP0_Config2_SA : MipsISA::CoreSpecific
CP0_Config2_SL : MipsISA::CoreSpecific
CP0_Config2_SS : MipsISA::CoreSpecific
CP0_Config2_SU : MipsISA::CoreSpecific
CP0_Config2_TA : MipsISA::CoreSpecific
CP0_Config2_TL : MipsISA::CoreSpecific
CP0_Config2_TS : MipsISA::CoreSpecific
CP0_Config2_TU : MipsISA::CoreSpecific
CP0_Config3 : MipsISA::CoreSpecific
CP0_Config3_DSPP : MipsISA::CoreSpecific
CP0_Config3_LPA : MipsISA::CoreSpecific
CP0_Config3_M : MipsISA::CoreSpecific
CP0_Config3_MT : MipsISA::CoreSpecific
CP0_Config3_SM : MipsISA::CoreSpecific
CP0_Config3_SP : MipsISA::CoreSpecific
CP0_Config3_TL : MipsISA::CoreSpecific
CP0_Config3_VEIC : MipsISA::CoreSpecific
CP0_Config3_VInt : MipsISA::CoreSpecific
CP0_Config_AR : MipsISA::CoreSpecific
CP0_Config_AT : MipsISA::CoreSpecific
CP0_Config_BE : MipsISA::CoreSpecific
CP0_Config_MT : MipsISA::CoreSpecific
CP0_Config_VI : MipsISA::CoreSpecific
CP0_EBase_CPUNum : MipsISA::CoreSpecific
CP0_IntCtl_IPPCI : MipsISA::CoreSpecific
CP0_IntCtl_IPTI : MipsISA::CoreSpecific
CP0_PerfCtr_M : MipsISA::CoreSpecific
CP0_PerfCtr_W : MipsISA::CoreSpecific
CP0_PRId : MipsISA::CoreSpecific
CP0_PRId_CompanyID : MipsISA::CoreSpecific
CP0_PRId_CompanyOptions : MipsISA::CoreSpecific
CP0_PRId_ProcessorID : MipsISA::CoreSpecific
CP0_PRId_Revision : MipsISA::CoreSpecific
CP0_SrsCtl_HSS : MipsISA::CoreSpecific
CP0_WatchHi_M : MipsISA::CoreSpecific
cp0Updated : MipsISA::ISA
CP_LdMiss : GPUCoalescer
cp_seq : Trace::InstRecord
cp_seq_valid : Trace::InstRecord
CP_StMiss : GPUCoalescer
CP_TCCLdHits : GPUCoalescer
CP_TCCStHits : GPUCoalescer
CP_TCPLdHits : GPUCoalescer
CP_TCPLdTransfers : GPUCoalescer
CP_TCPStHits : GPUCoalescer
CP_TCPStTransfers : GPUCoalescer
cpa : AnnotateDumpCallback , IGbE
CPBR : VGic
cpd : ecoff_fdr
cpi : FullO3CPU< Impl > , Minor::MinorStats , TraceCPU
cpl : Pl111
cpsr : ArmISA::RemoteGDB::AArch32GdbRegCache , ArmISA::RemoteGDB::AArch64GdbRegCache , ArmISA::TableWalker::WalkerState , ArmISA::TLB
cptDir : CheckpointIn
cpu : AlphaBackdoor , AlphaISA::Interrupts , ArmISA::Interrupts , AtomicSimpleCPU::AtomicCPUDPort , BaseDynInst< Impl > , BaseInterrupts , BaseKvmCPU::KVMCpuPort , CPUProgressEvent , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , ElasticTrace , GenericTimerISA , GpuDispatcher , InstructionQueue< Impl > , Iob::IntMan , LSQ< Impl > , LSQ< Impl >::DcachePort , LSQUnit< Impl > , Minor::Decode , Minor::ExecContext , Minor::Execute , Minor::Fetch1 , Minor::Fetch2 , Minor::LSQ , Minor::Pipeline , MinorCPU::MinorCPUPort , O3ThreadContext< Impl > , O3ThreadState< Impl > , PowerISA::Interrupts , RiscvISA::Interrupts , ROB< Impl > , SimpleExecContext , SparcISA::Interrupts , TimingSimpleCPU::FetchTranslation , TimingSimpleCPU::IprEvent , TimingSimpleCPU::TimingCPUPort , TimingSimpleCPU::TimingCPUPort::TickEvent , X86ISA::Interrupts
CPU_Exit_Pri : EventBase
cpu_id : GicV2
cpu_list : GicV2
CPU_MAX : GicV2
cpu_mondo_head : SparcISA::ISA
cpu_mondo_tail : SparcISA::ISA
CPU_Switch_Pri : EventBase
CPU_Tick_Pri : EventBase
cpuBpr : GicV2
cpuClock : AlphaAccess , MipsAccess
cpuControl : GicV2
cpuEventList : CpuEvent
cpuFlags : X86ISA::IntelMP::Processor
cpuHighestInt : GicV2
cpuId : Gicv3CPUInterface , Gicv3Redistributor , Trace::TarmacParser
CpuID : VGic
cpuInterface : Gicv3Redistributor
cpuInterfaces : Gicv3
cpuIntrEnable : Sinic::Base
cpuList : BaseCPU
cpuName : Trace::TarmacTracerRecordV8::TraceEntryV8
cpuPendingIntr : NSGigE , Sinic::Base
cpuPioDelay : GicV2
cpuPointer : Shader
cpuPorts : SimpleCache
cpuPpiActive : GicV2
cpuPpiPending : GicV2
cpuPriority : GicV2
cpuRange : GicV2 , KvmKernelGicV2
cpuSgiActive : GicV2
cpuSgiActiveExt : GicV2
cpuSgiPending : GicV2
cpuSgiPendingExt : GicV2
cpuSidePort : BaseCache , TLBCoalescer , X86ISA::GpuTLB
cpuSignature : X86ISA::IntelMP::Processor
cpuStack : AlphaAccess , MipsAccess
cpuTarget : GicV2
cpuThread : Shader
cpuWaitList : FullO3CPU< Impl >
cr : CopyEngine::CopyEngineChannel , PowerISA::RemoteGDB::PowerGdbRegCache
cr0 : SMMURegs
cr0ack : SMMURegs
cr1 : SMMURegs
cr2 : SMMURegs
CRDD : NSGigE
creatorID : X86ISA::ACPI::SysDescTable
creatorRevision : X86ISA::ACPI::SysDescTable
creditQueue : InputUnit
cRegCount : HsaKernelInfo , HsaQueueEntry
crfd : ecoff_fdr , ecoff_symhdr
CrsrImage : Pl111
CrsrImageSize : Pl111
cs : X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED , X86ISA::RemoteGDB::X86GdbRegCache
csr : RiscvISA::CSROp , SparcISA::RemoteGDB::SPARCGdbRegCache
csum : iGbReg::RxDesc
csym : ecoff_fdr
ct0 : TAGEBase::BranchInfo
ct1 : TAGEBase::BranchInfo
CTDD : NSGigE
ctidbgirq : FastModel::ScxEvsCortexA76< Types >
CTLR_QUIESCENT : Gicv3Its
ctr : AbstractController::StatsCallback , Network::StatsCallback , PowerISA::RemoteGDB::PowerGdbRegCache , TAGEBase::TageEntry
ctrInsts : BaseKvmCPU
ctrl : CopyEngineReg::ChanRegs , IdeDisk , iGbReg::Regs
ctrl32 : FXSave
ctrl64 : FXSave
CTRL_CNTACR_BASE : GenericTimerMem
CTRL_CNTFRQ : GenericTimerMem
CTRL_CNTNSAR : GenericTimerMem
CTRL_CNTTIDR : GenericTimerMem
CTRL_CNTVOFF_HI_BASE : GenericTimerMem
CTRL_CNTVOFF_LO_BASE : GenericTimerMem
ctrl_ext : iGbReg::Regs
ctrlOffset : IdeController
ctrlRange : GenericTimerMem
ctx : Fiber , sc_gem5::Thread
cu : GPUExecContext
cu_id : ComputeUnit , GPUDynInst
cuExitCallback : ComputeUnit
cuList : Shader
cuPort : LdsState
curAddr : ChunkGenerator , Pl111
curCid : NDRange
curDmaDesc : CopyEngine::CopyEngineChannel
curDoorbell : UFSHostDevice::UFSHostDeviceStats
curFetching : IGbE::DescCache< T >
curMacroStaticInst : BaseSimpleCPU , CheckerCPU
curMsg : Trace::InstPBTrace
curPrd : IdeDisk
curPrdAddr : IdeDisk
curPrefixPtr : Packet::PrintReqState
currBit : I2CBus
currElement : TraceCPU::FixedRetryGen , TraceGen
currELHOffset : ArmISA::ArmFault::FaultVals
currELTOffset : ArmISA::ArmFault::FaultVals
current : Stats::AvgStor , Trace::ArmNativeTrace::ThreadState
currentBBV : SimPoint
currentBBVInstCount : SimPoint
currentCode : BrigObject
currentDirectory : CheckpointIn
currentFunctionEnd : BaseCPU
currentFunctionStart : BaseCPU
currentIter : LoopPredictor::BranchInfo , LoopPredictor::LoopEntry
currentIterSpec : LoopPredictor::LoopEntry
currentProcess : sc_core::sc_sensitive
currentReadSSDQueue : UFSHostDevice::UFSHostDeviceStats
currentSCSIQueue : UFSHostDevice::UFSHostDeviceStats
currentTemp : ThermalDomain
currentWriteSSDQueue : UFSHostDevice::UFSHostDeviceStats
currRecordType : Trace::TarmacParserRecord
currState : ArmISA::TableWalker , TrafficGen
currStates : X86ISA::Walker
curSector : IdeDisk , MmDisk
curSize : ChunkGenerator
cursorImage : Pl111
curState : VncServer
curStaticInst : BaseSimpleCPU , CheckerCPU
curTask : GpuDispatcher
curThread : BaseSimpleCPU
curTime : MC146818
curTranType : ArmISA::TLB
cv : DistIface::Sync
cvec : Stats::DistData , Stats::DistStor , Stats::FormulaInfoProxy< Stat > , Stats::HistStor , Stats::Vector2dInfo , Stats::VectorInfoProxy< Stat >
cwp : SparcISA::ISA
cx_config : SparcISA::TLB
cx_tsb_ps0 : SparcISA::TLB
cx_tsb_ps1 : SparcISA::TLB
cycle : Clocked , instr
cycleCounter : ArmISA::PMU
cycleCounterEventId : ArmISA::PMU
cycleSem : SMMUv3
cyl_high : CommandReg
cyl_low : CommandReg