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iew.hh
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42 
43 #ifndef __CPU_O3_IEW_HH__
44 #define __CPU_O3_IEW_HH__
45 
46 #include <queue>
47 #include <set>
48 
49 #include "base/statistics.hh"
50 #include "cpu/o3/comm.hh"
51 #include "cpu/o3/lsq.hh"
52 #include "cpu/o3/scoreboard.hh"
53 #include "cpu/timebuf.hh"
54 #include "debug/IEW.hh"
55 #include "sim/probe/probe.hh"
56 
57 struct DerivO3CPUParams;
58 class FUPool;
59 
79 template<class Impl>
81 {
82  private:
83  //Typedefs from Impl
84  typedef typename Impl::CPUPol CPUPol;
85  typedef typename Impl::DynInstPtr DynInstPtr;
86  typedef typename Impl::O3CPU O3CPU;
87 
88  typedef typename CPUPol::IQ IQ;
89  typedef typename CPUPol::RenameMap RenameMap;
90  typedef typename CPUPol::LSQ LSQ;
91 
92  typedef typename CPUPol::TimeStruct TimeStruct;
93  typedef typename CPUPol::IEWStruct IEWStruct;
94  typedef typename CPUPol::RenameStruct RenameStruct;
95  typedef typename CPUPol::IssueStruct IssueStruct;
96 
97  public:
101  enum Status {
104  };
105 
107  enum StageStatus {
114  };
115 
116  private:
120  StageStatus dispatchStatus[Impl::MaxThreads];
125 
133 
134  public:
136  DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
137 
139  std::string name() const;
140 
142  void regStats();
143 
145  void regProbePoints();
146 
148  void startupStage();
149 
151  void clearStates(ThreadID tid);
152 
155 
158 
160  void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
161 
164 
166  void setScoreboard(Scoreboard *sb_ptr);
167 
169  void drainSanityCheck() const;
170 
172  bool isDrained() const;
173 
175  void takeOverFrom();
176 
178  void squash(ThreadID tid);
179 
181  void wakeDependents(const DynInstPtr &inst);
182 
186  void rescheduleMemInst(const DynInstPtr &inst);
187 
189  void replayMemInst(const DynInstPtr &inst);
190 
192  void blockMemInst(const DynInstPtr &inst);
193 
195  void cacheUnblocked();
196 
198  void instToCommit(const DynInstPtr &inst);
199 
201  void skidInsert(ThreadID tid);
202 
204  int skidCount();
205 
207  bool skidsEmpty();
208 
210  void updateStatus();
211 
213  void resetEntries();
214 
218  void wakeCPU();
219 
221  void activityThisCycle();
222 
224  inline void activateStage();
225 
227  inline void deactivateStage();
228 
230  bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
231 
233  bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
234 
236  void checkMisprediction(const DynInstPtr &inst);
237 
238  private:
242  void squashDueToBranch(const DynInstPtr &inst, ThreadID tid);
243 
247  void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid);
248 
250  void block(ThreadID tid);
251 
255  void unblock(ThreadID tid);
256 
258  void dispatch(ThreadID tid);
259 
261  void dispatchInsts(ThreadID tid);
262 
267  void executeInsts();
268 
274  void writebackInsts();
275 
279  unsigned validInstsFromRename();
280 
282  bool checkStall(ThreadID tid);
283 
286 
288  void emptyRenameInsts(ThreadID tid);
289 
291  void sortInsts();
292 
293  public:
297  void tick();
298 
299  private:
301  void updateExeInstStats(const DynInstPtr &inst);
302 
305 
308 
311 
314 
317 
320 
323 
326 
332 
335 
337  std::queue<DynInstPtr> insts[Impl::MaxThreads];
338 
340  std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
341 
344 
345  private:
347  O3CPU *cpu;
348 
353 
355  void printAvailableInsts();
356 
357  public:
360 
363 
370 
371  private:
373  bool fetchRedirect[Impl::MaxThreads];
374 
379 
382 
385 
392 
394  unsigned dispatchWidth;
395 
397  unsigned issueWidth;
398 
400  unsigned wbNumInst;
401 
407  unsigned wbCycle;
408 
410  unsigned wbWidth;
411 
414 
417 
419  unsigned skidBufferMax;
420 
451 
457 // Stats::Scalar iewExecStoreInsts;
472 
485 };
486 
487 #endif // __CPU_O3_IEW_HH__
Cycles renameToIEWDelay
Rename to IEW delay.
Definition: iew.hh:384
Stats::Vector iewExecutedBranches
Number of executed branches.
Definition: iew.hh:467
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets main time buffer used for backwards communication.
Definition: iew_impl.hh:341
unsigned issueWidth
Width of issue, in instructions.
Definition: iew.hh:397
Scoreboard * scoreboard
Scoreboard pointer.
Definition: iew.hh:343
bool fetchRedirect[Impl::MaxThreads]
Records if there is a fetch redirect on this cycle for each thread.
Definition: iew.hh:373
StageStatus exeStatus
Execute status.
Definition: iew.hh:122
Stats::Scalar iewDispStoreInsts
Stat for total number of dispatched store instructions.
Definition: iew.hh:436
Stats::Scalar iewExecutedInsts
Stat for total number of executed instructions.
Definition: iew.hh:453
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
bool hasStoresToWB(ThreadID tid)
Returns if the LSQ has any stores to writeback.
Definition: iew.hh:233
void setIEWQueue(TimeBuffer< IEWStruct > *iq_ptr)
Sets time buffer to pass on instructions to commit.
Definition: iew_impl.hh:369
CPUPol::LSQ LSQ
Definition: iew.hh:90
Status
Overall IEW stage status.
Definition: iew.hh:101
void rescheduleMemInst(const DynInstPtr &inst)
Tells memory dependence unit that a memory instruction needs to be rescheduled.
Definition: iew_impl.hh:595
Stats::Scalar iewIdleCycles
Stat for total number of idle cycles.
Definition: iew.hh:422
bool updatedQueues
Records if the queues have been changed (inserted or issued insts), so that IEW knows to broadcast th...
Definition: iew.hh:378
void setRenameQueue(TimeBuffer< RenameStruct > *rq_ptr)
Sets time buffer for getting instructions coming from rename.
Definition: iew_impl.hh:359
Stats::Scalar iewUnblockCycles
Stat for total number of unblocking cycles.
Definition: iew.hh:428
Stats::Scalar iewSquashCycles
Stat for total number of squashing cycles.
Definition: iew.hh:424
void startupStage()
Initializes stage; sends back the number of free IQ and LSQ entries.
Definition: iew_impl.hh:306
Stats::Formula iewExecRate
Number of instructions executed per cycle.
Definition: iew.hh:471
void unblock(ThreadID tid)
Unblocks Dispatch if the skid buffer is empty, and signals back to other stages to unblock...
Definition: iew_impl.hh:571
Stats::Scalar iewLSQFullEvents
Stat for number of times the LSQ becomes full.
Definition: iew.hh:442
DefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:80
Stats::Scalar iewIQFullEvents
Stat for number of times the IQ becomes full.
Definition: iew.hh:440
ThreadID numThreads
Number of active threads.
Definition: iew.hh:413
void printAvailableInsts()
Debug function to print instructions that are issued this cycle.
Definition: iew_impl.hh:1184
O3CPU * cpu
CPU pointer.
Definition: iew.hh:347
Cycles issueToExecuteDelay
Issue to execute delay.
Definition: iew.hh:391
TimeBuffer< TimeStruct > * timeBuffer
Pointer to main time buffer used for backwards communication.
Definition: iew.hh:304
Stats::Vector iewExecutedRefs
Number of executed meomory references.
Definition: iew.hh:465
DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
Constructs a DefaultIEW with the given parameters.
Definition: iew_impl.hh:68
bool hasStoresToWB()
Returns whether or not there are any stores to write back to memory.
Definition: lsq_impl.hh:640
void squash(ThreadID tid)
Squashes instructions in IEW for a specific thread.
Definition: iew_impl.hh:463
std::queue< DynInstPtr > insts[Impl::MaxThreads]
Queue of all instructions coming from rename this cycle.
Definition: iew.hh:337
A vector of scalar stats.
Definition: statistics.hh:2550
bool checkStall(ThreadID tid)
Checks if any of the stall conditions are currently true.
Definition: iew_impl.hh:765
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
Definition: iew.hh:416
unsigned wbNumInst
Index into queue of instructions being written back.
Definition: iew.hh:400
unsigned dispatchWidth
Width of dispatch, in instructions.
Definition: iew.hh:394
TimeBuffer< TimeStruct >::wire toFetch
Wire to write information heading to previous stages.
Definition: iew.hh:307
Declaration of Statistics objects.
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:2508
StageStatus wbStatus
Writeback status.
Definition: iew.hh:124
void instToCommit(const DynInstPtr &inst)
Sends an instruction to commit through the time buffer.
Definition: iew_impl.hh:623
unsigned validInstsFromRename()
Returns the number of valid, non-squashed instructions coming from rename to dispatch.
Definition: iew_impl.hh:652
TimeBuffer< IEWStruct > * iewQueue
IEW stage time buffer.
Definition: iew.hh:331
Stats::Vector iewExecutedSwp
Number of executed software prefetches.
Definition: iew.hh:461
ProbePointArg< DynInstPtr > * ppToCommit
To probe when instruction execution is complete.
Definition: iew.hh:132
Stats::Vector writebackCount
Number of instructions that writeback.
Definition: iew.hh:476
Stats::Scalar iewDispNonSpecInsts
Stat for total number of dispatched non speculative instructions.
Definition: iew.hh:438
Impl::CPUPol CPUPol
Definition: iew.hh:84
Implements a simple scoreboard to track which registers are ready.
Definition: scoreboard.hh:52
void cacheUnblocked()
Notifies that the cache has become unblocked.
Definition: iew_impl.hh:616
bool hasStoresToWB()
Returns if the LSQ has any stores to writeback.
Definition: iew.hh:230
IQ instQueue
Instruction queue.
Definition: iew.hh:359
TimeBuffer< IssueStruct >::wire fromIssue
Wire to read information from the issue stage time queue.
Definition: iew.hh:325
CPUPol::IssueStruct IssueStruct
Definition: iew.hh:95
void activateStage()
Tells CPU that the IEW stage is active and running.
Definition: iew_impl.hh:897
Pool of FU&#39;s, specific to the new CPU model.
Definition: fu_pool.hh:71
void dispatchInsts(ThreadID tid)
Dispatches instructions to IQ and LSQ.
Definition: iew_impl.hh:961
std::queue< DynInstPtr > skidBuffer[Impl::MaxThreads]
Skid buffer between rename and IEW.
Definition: iew.hh:340
Status _status
Overall stage status.
Definition: iew.hh:118
TimeBuffer< IssueStruct > issueToExecQueue
Issue stage queue.
Definition: iew.hh:322
ProbePointArg< DynInstPtr > * ppDispatch
Definition: iew.hh:128
Stats::Scalar iewExecSquashedInsts
Stat for total number of executed store instructions.
Definition: iew.hh:459
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit&#39;s output from backwards time buffer.
Definition: iew.hh:310
Stats::Scalar iewDispLoadInsts
Stat for total number of dispatched load instructions.
Definition: iew.hh:434
void takeOverFrom()
Takes over from another CPU&#39;s thread.
Definition: iew_impl.hh:435
Stats::Formula wbRate
Number of instructions per cycle written back.
Definition: iew.hh:482
Stats::Scalar iewDispatchedInsts
Stat for total number of instructions dispatched.
Definition: iew.hh:430
void tick()
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle...
Definition: iew_impl.hh:1504
void emptyRenameInsts(ThreadID tid)
Removes instructions from rename from a thread&#39;s instruction list.
Definition: iew_impl.hh:860
void checkSignalsAndUpdate(ThreadID tid)
Processes inputs and changes state accordingly.
Definition: iew_impl.hh:782
unsigned wbWidth
Writeback width.
Definition: iew.hh:410
void replayMemInst(const DynInstPtr &inst)
Re-executes all rescheduled memory instructions.
Definition: iew_impl.hh:602
CPUPol::TimeStruct TimeStruct
Definition: iew.hh:92
void wakeCPU()
Tells the CPU to wakeup if it has descheduled itself due to no activity.
Definition: iew_impl.hh:882
unsigned wbCycle
Cycle number within the queue of instructions being written back.
Definition: iew.hh:407
Stats::Vector iewExecutedNop
Number of executed nops.
Definition: iew.hh:463
CPUPol::IQ IQ
Definition: iew.hh:88
Cycles commitToIEWDelay
Commit to IEW delay.
Definition: iew.hh:381
Stats::Scalar iewDispSquashedInsts
Stat for total number of squashed instructions dispatch skips.
Definition: iew.hh:432
bool updateLSQNextCycle
Records if the LSQ needs to be updated on the next cycle, so that IEW knows if there will be activity...
Definition: iew.hh:369
Stats::Vector producerInst
Number of instructions that wake consumers.
Definition: iew.hh:478
bool isDrained() const
Has the stage drained?
Definition: iew_impl.hh:396
A formula for statistics that is calculated when printed.
Definition: statistics.hh:3012
Stats::Scalar predictedTakenIncorrect
Stat for total number of incorrect predicted taken branches.
Definition: iew.hh:446
void activityThisCycle()
Reports to the CPU that there is activity this cycle.
Definition: iew_impl.hh:889
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:227
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
Definition: iew_impl.hh:379
Stats::Scalar memOrderViolationEvents
Stat for total number of memory ordering violation events.
Definition: iew.hh:444
void regStats()
Registers statistics.
Definition: iew_impl.hh:146
void updateExeInstStats(const DynInstPtr &inst)
Updates execution stats based on the instruction.
Definition: iew_impl.hh:1634
int skidCount()
Returns the max of the number of entries in all of the skid buffers.
Definition: iew_impl.hh:688
void setScoreboard(Scoreboard *sb_ptr)
Sets pointer to the scoreboard.
Definition: iew_impl.hh:389
bool wroteToTimeBuffer
Records if IEW has written to the time buffer this cycle, so that the CPU can deschedule itself if th...
Definition: iew.hh:352
StageStatus
Status for Issue, Execute, and Writeback stages.
Definition: iew.hh:107
Stats::Formula iewExecStoreInsts
Number of executed store instructions.
Definition: iew.hh:469
void squashDueToBranch(const DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a branch mispredict.
Definition: iew_impl.hh:499
void executeInsts()
Executes instructions.
Definition: iew_impl.hh:1207
TimeBuffer< RenameStruct > * renameQueue
Rename instruction queue interface.
Definition: iew.hh:316
void writebackInsts()
Writebacks instructions.
Definition: iew_impl.hh:1454
void blockMemInst(const DynInstPtr &inst)
Moves memory instruction onto the list of cache blocked instructions.
Definition: iew_impl.hh:609
void wakeDependents(const DynInstPtr &inst)
Wakes all dependents of a completed instruction.
Definition: iew_impl.hh:588
std::string name() const
Returns the name of the DefaultIEW stage.
Definition: iew_impl.hh:119
void sortInsts()
Sorts instructions coming from rename into lists separated by thread.
Definition: iew_impl.hh:846
void checkMisprediction(const DynInstPtr &inst)
Check misprediction.
Definition: iew_impl.hh:1666
Stats::Vector iewInstsToCommit
Number of instructions sent to commit.
Definition: iew.hh:474
void dispatch(ThreadID tid)
Determines proper actions to take given Dispatch&#39;s status.
Definition: iew_impl.hh:913
void skidInsert(ThreadID tid)
Inserts unused instructions of a thread into the skid buffer.
Definition: iew_impl.hh:666
TimeBuffer< RenameStruct >::wire fromRename
Wire to get rename&#39;s output from rename queue.
Definition: iew.hh:319
LSQ ldstQueue
Load / store queue.
Definition: iew.hh:362
TimeBuffer< IEWStruct >::wire toCommit
Wire to write infromation heading to commit.
Definition: iew.hh:334
CPUPol::RenameStruct RenameStruct
Definition: iew.hh:94
Stats::Formula branchMispredicts
Stat for total number of mispredicted branches detected at execute.
Definition: iew.hh:450
void deactivateStage()
Tells CPU that the IEW stage is inactive and idle.
Definition: iew_impl.hh:905
bool skidsEmpty()
Returns if all of the skid buffers are empty.
Definition: iew_impl.hh:707
unsigned skidBufferMax
Maximum size of the skid buffer.
Definition: iew.hh:419
Impl::DynInstPtr DynInstPtr
Definition: iew.hh:85
ProbePointArg< DynInstPtr > * ppExecute
To probe when instruction execution begins.
Definition: iew.hh:130
void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a memory order violation.
Definition: iew_impl.hh:525
void resetEntries()
Resets entries of the IQ and the LSQ.
TimeBuffer< TimeStruct >::wire toRename
Wire to write information heading to previous stages.
Definition: iew.hh:313
StageStatus dispatchStatus[Impl::MaxThreads]
Dispatch status.
Definition: iew.hh:120
ProbePointArg< DynInstPtr > * ppMispredict
Probe points.
Definition: iew.hh:127
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: iew_impl.hh:328
void block(ThreadID tid)
Sets Dispatch to blocked, and signals back to other stages to block.
Definition: iew_impl.hh:552
Stats::Scalar predictedNotTakenIncorrect
Stat for total number of incorrect predicted not taken branches.
Definition: iew.hh:448
Impl::O3CPU O3CPU
Definition: iew.hh:86
Stats::Vector iewExecLoadInsts
Stat for total number of executed load instructions.
Definition: iew.hh:455
Stats::Vector consumerInst
Number of instructions that wake up from producers.
Definition: iew.hh:480
void regProbePoints()
Registers probes.
Definition: iew_impl.hh:126
CPUPol::IEWStruct IEWStruct
Definition: iew.hh:93
CPUPol::RenameMap RenameMap
Definition: iew.hh:89
Stats::Scalar iewBlockCycles
Stat for total number of blocking cycles.
Definition: iew.hh:426
void updateStatus()
Updates overall IEW status based on all of the stages&#39; statuses.
Definition: iew_impl.hh:724
FUPool * fuPool
Pointer to the functional unit pool.
Definition: iew.hh:365
Stats::Formula wbFanout
Average number of woken instructions per writeback.
Definition: iew.hh:484
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: iew_impl.hh:425

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